| /freebsd-14-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| HD | InstructionSelect.cpp | 90 InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector(); in runOnMachineFunction() local
91 ISel->setTargetPassConfig(&TPC); in runOnMachineFunction()
106 assert(ISel && "Cannot work without InstructionSelector"); in runOnMachineFunction()
107 ISel->setupMF(MF, KB, &CoverageInfo, PSI, BFI); in runOnMachineFunction()
111 ISel->setRemarkEmitter(&MORE); in runOnMachineFunction()
135 ISel->CurMBB = MBB; in runOnMachineFunction()
193 if (!ISel->select(MI)) { in runOnMachineFunction()
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelDAGToDAGHVX.cpp | 925 HexagonDAGToDAGISel &ISel; member
931 : Lower(getHexagonLowering(G)), ISel(HS), DAG(G), in HvxSelector()
1179 Ops.push_back(ISel.selectUndef(dl, MVT(SVT))); in materialize()
1215 ISel.ReplaceNode(InpN, OutN); in materialize()
1767 ISel.ReplaceNode(ISelN, N0); in select()
1832 ISel.ReplaceNode(ISelN, N0); in select()
1842 ISel.Select(S); in select()
1874 Ops.push_back(ISel.selectUndef(dl, LegalTy)); in scalarizeShuffle()
1918 ISel.ReplaceNode(N, IS.getNode()); in scalarizeShuffle()
2587 ISel.ReplaceNode(N, Ext.getNode()); in selectExtractSubvector()
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| HD | WebAssemblyInstrFormats.td | 48 // instructions are used for ISel and all MI passes. The stack versions of the
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| HD | WebAssemblyInstrCall.td | 33 // inserter hook after DAG ISel, so passes over MachineInstrs will only ever
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| HD | Relocation.txt | 37 to ISel which in turn relies on TableGen patterns to choose subtarget
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| HD | MSA.txt | 5 optimisation, reduce the size of the ISel matcher, and reduce repetition in
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
| HD | VVPInstrInfo.td | 18 // TODO explain how VVP nodes relate to VP SDNodes once VP ISel is uptream.
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| HD | VEInstrInfo.td | 1584 // Basic cast between registers. This is often used in ISel patterns, so make
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| /freebsd-14-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
| HD | IntrinsicsWebAssembly.td | 346 // TODO: Replace these intrinsic with normal ISel patterns once the XXX
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| HD | VPIntrinsics.def | 562 // VP_SETCC (ISel only)
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| HD | IntrinsicsARM.td | 21 // and return value are essentially chains, used to force ordering during ISel.
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| HD | IntrinsicsAArch64.td | 92 // ordering during ISel.
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| HD | ARMInstrThumb.td | 1662 // different to how ISel expects them for a post-inc load, so use a pseudo
1663 // and expand it just after ISel.
1672 // multiple registers) is the same in ISel as MachineInstr, so there's no need
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| HD | ARMInstrMVE.td | 246 // ISel patterns.
250 // of those in Vec, so we can use it in ISel patterns. It is up to the
255 // predicate bits, for use in ISel patterns that handle an IR
6375 // Multiclasses wrapping that to add ISel patterns for intrinsics.
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| HD | ARMInstrFormats.td | 201 // Transform to generate the inverse of a condition code during ISel
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| HD | ARMInstrInfo.td | 3262 // put the patterns on the instruction definitions directly as ISel wants
4190 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
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| HD | ARMInstrThumb2.td | 1770 // put the patterns on the instruction definitions directly as ISel wants
5623 // will be created post-ISel from a llvm.test.start.loop.iterations. This
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| /freebsd-14-stable/contrib/llvm-project/llvm/include/llvm/Support/ |
| HD | TargetOpcodes.def | 233 /// The following generic opcodes are not supposed to appear after ISel.
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAGISel.cpp | 244 OptLevelChanger(SelectionDAGISel &ISel, CodeGenOptLevel NewOptLevel) in OptLevelChanger() argument
245 : IS(ISel) { in OptLevelChanger()
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| /freebsd-14-stable/contrib/llvm-project/llvm/include/llvm/Target/ |
| HD | Target.td | 1892 // Pull in the common support for Global ISel register bank info generation.
1902 // Pull in the common support for the Global ISel DAG-based selector generation.
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| HD | R600Instructions.td | 1709 // ISel Patterns
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| HD | AVRInstrInfo.td | 835 // because we also need to be able to specify a pattern to match for ISel.
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| HD | RISCVInstrInfo.td | 2086 // Global ISel
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| HD | PPCInstr64Bit.td | 1754 // the instruction definitions directly as ISel wants the address base
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| HD | X86InstrMisc.td | 631 // bt instruction does not ignore the high bits of the index. From ISel's
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