1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/kernel.h>
33 #include <sys/lock.h>
34 #include <sys/module.h>
35 #include <sys/mutex.h>
36 #include <sys/rman.h>
37 #include <sys/resource.h>
38 #include <machine/bus.h>
39
40 #include <dev/ofw/ofw_bus.h>
41 #include <dev/ofw/ofw_bus_subr.h>
42
43 #include <dev/extres/clk/clk.h>
44 #include <dev/extres/hwreset/hwreset.h>
45 #include <dev/extres/syscon/syscon.h>
46
47 #include "syscon_if.h"
48
49 #include "opt_snd.h"
50 #include <dev/sound/pcm/sound.h>
51 #include <dev/sound/fdt/audio_dai.h>
52 #include "audio_dai_if.h"
53
54 #define I2S_TXCR 0x0000
55 #define I2S_CSR_2 (0 << 15)
56 #define I2S_CSR_4 (1 << 15)
57 #define I2S_CSR_6 (2 << 15)
58 #define I2S_CSR_8 (3 << 15)
59 #define I2S_TXCR_IBM_NORMAL (0 << 9)
60 #define I2S_TXCR_IBM_LJ (1 << 9)
61 #define I2S_TXCR_IBM_RJ (2 << 9)
62 #define I2S_TXCR_PBM_NODELAY (0 << 7)
63 #define I2S_TXCR_PBM_1 (1 << 7)
64 #define I2S_TXCR_PBM_2 (2 << 7)
65 #define I2S_TXCR_PBM_3 (3 << 7)
66 #define I2S_TXCR_TFS_I2S (0 << 5)
67 #define I2S_TXCR_TFS_PCM (1 << 5)
68 #define I2S_TXCR_VDW_16 (0xf << 0)
69 #define I2S_RXCR 0x0004
70 #define I2S_RXCR_IBM_NORMAL (0 << 9)
71 #define I2S_RXCR_IBM_LJ (1 << 9)
72 #define I2S_RXCR_IBM_RJ (2 << 9)
73 #define I2S_RXCR_PBM_NODELAY (0 << 7)
74 #define I2S_RXCR_PBM_1 (1 << 7)
75 #define I2S_RXCR_PBM_2 (2 << 7)
76 #define I2S_RXCR_PBM_3 (3 << 7)
77 #define I2S_RXCR_TFS_I2S (0 << 5)
78 #define I2S_RXCR_TFS_PCM (1 << 5)
79 #define I2S_RXCR_VDW_16 (0xf << 0)
80 #define I2S_CKR 0x0008
81 #define I2S_CKR_MSS_MASK (1 << 27)
82 #define I2S_CKR_MSS_MASTER (0 << 27)
83 #define I2S_CKR_MSS_SLAVE (1 << 27)
84 #define I2S_CKR_CKP (1 << 26)
85 #define I2S_CKR_MDIV(n) (((n) - 1) << 16)
86 #define I2S_CKR_MDIV_MASK (0xff << 16)
87 #define I2S_CKR_RSD(n) (((n) - 1) << 8)
88 #define I2S_CKR_RSD_MASK (0xff << 8)
89 #define I2S_CKR_TSD(n) (((n) - 1) << 0)
90 #define I2S_CKR_TSD_MASK (0xff << 0)
91 #define I2S_TXFIFOLR 0x000c
92 #define TXFIFO0LR_MASK 0x3f
93 #define I2S_DMACR 0x0010
94 #define I2S_DMACR_RDE_ENABLE (1 << 24)
95 #define I2S_DMACR_RDL(n) ((n) << 16)
96 #define I2S_DMACR_TDE_ENABLE (1 << 8)
97 #define I2S_DMACR_TDL(n) ((n) << 0)
98 #define I2S_INTCR 0x0014
99 #define I2S_INTCR_RFT(n) (((n) - 1) << 20)
100 #define I2S_INTCR_TFT(n) (((n) - 1) << 4)
101 #define I2S_INTCR_RXFIE (1 << 16)
102 #define I2S_INTCR_TXUIC (1 << 2)
103 #define I2S_INTCR_TXEIE (1 << 0)
104 #define I2S_INTSR 0x0018
105 #define I2S_INTSR_RXFI (1 << 16)
106 #define I2S_INTSR_TXUI (1 << 1)
107 #define I2S_INTSR_TXEI (1 << 0)
108 #define I2S_XFER 0x001c
109 #define I2S_XFER_RXS_START (1 << 1)
110 #define I2S_XFER_TXS_START (1 << 0)
111 #define I2S_CLR 0x0020
112 #define I2S_CLR_RXC (1 << 1)
113 #define I2S_CLR_TXC (1 << 0)
114 #define I2S_TXDR 0x0024
115 #define I2S_RXDR 0x0028
116 #define I2S_RXFIFOLR 0x002c
117 #define RXFIFO0LR_MASK 0x3f
118
119 /* syscon */
120 #define GRF_SOC_CON8 0xe220
121 #define I2S_IO_DIRECTION_MASK 7
122 #define I2S_IO_DIRECTION_SHIFT 11
123 #define I2S_IO_8CH_OUT_2CH_IN 0
124 #define I2S_IO_6CH_OUT_4CH_IN 4
125 #define I2S_IO_4CH_OUT_6CH_IN 6
126 #define I2S_IO_2CH_OUT_8CH_IN 7
127
128 #define DIV_ROUND_CLOSEST(n,d) (((n) + (d) / 2) / (d))
129
130 #define RK_I2S_SAMPLING_RATE 48000
131 #define FIFO_SIZE 32
132
133 static struct ofw_compat_data compat_data[] = {
134 { "rockchip,rk3066-i2s", 1 },
135 { "rockchip,rk3399-i2s", 1 },
136 { NULL, 0 }
137 };
138
139 static struct resource_spec rk_i2s_spec[] = {
140 { SYS_RES_MEMORY, 0, RF_ACTIVE },
141 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
142 { -1, 0 }
143 };
144
145 struct rk_i2s_softc {
146 device_t dev;
147 struct resource *res[2];
148 struct mtx mtx;
149 clk_t clk;
150 clk_t hclk;
151 void * intrhand;
152 struct syscon *grf;
153 /* pointers to playback/capture buffers */
154 uint32_t play_ptr;
155 uint32_t rec_ptr;
156 };
157
158 #define RK_I2S_LOCK(sc) mtx_lock(&(sc)->mtx)
159 #define RK_I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
160 #define RK_I2S_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))
161 #define RK_I2S_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
162
163 static int rk_i2s_probe(device_t dev);
164 static int rk_i2s_attach(device_t dev);
165 static int rk_i2s_detach(device_t dev);
166
167 static uint32_t sc_fmt[] = {
168 SND_FORMAT(AFMT_S16_LE, 2, 0),
169 0
170 };
171 static struct pcmchan_caps rk_i2s_caps = {RK_I2S_SAMPLING_RATE, RK_I2S_SAMPLING_RATE, sc_fmt, 0};
172
173
174 static int
rk_i2s_init(struct rk_i2s_softc * sc)175 rk_i2s_init(struct rk_i2s_softc *sc)
176 {
177 uint32_t val;
178 int error;
179
180 clk_set_freq(sc->clk, RK_I2S_SAMPLING_RATE * 256,
181 CLK_SET_ROUND_DOWN);
182 error = clk_enable(sc->clk);
183 if (error != 0) {
184 device_printf(sc->dev, "cannot enable i2s_clk clock\n");
185 return (ENXIO);
186 }
187
188 val = I2S_INTCR_TFT(FIFO_SIZE/2);
189 val |= I2S_INTCR_RFT(FIFO_SIZE/2);
190 RK_I2S_WRITE_4(sc, I2S_INTCR, val);
191
192 if (sc->grf && ofw_bus_is_compatible(sc->dev, "rockchip,rk3399-i2s")) {
193 val = (I2S_IO_2CH_OUT_8CH_IN << I2S_IO_DIRECTION_SHIFT);
194 val |= (I2S_IO_DIRECTION_MASK << I2S_IO_DIRECTION_SHIFT) << 16;
195 SYSCON_WRITE_4(sc->grf, GRF_SOC_CON8, val);
196
197 #if 0
198 // HACK: enable IO domain
199 val = (1 << 1);
200 val |= (1 << 1) << 16;
201 SYSCON_WRITE_4(sc->grf, 0xe640, val);
202 #endif
203 }
204
205 RK_I2S_WRITE_4(sc, I2S_XFER, 0);
206
207 return (0);
208 }
209
210 static int
rk_i2s_probe(device_t dev)211 rk_i2s_probe(device_t dev)
212 {
213 if (!ofw_bus_status_okay(dev))
214 return (ENXIO);
215
216 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
217 return (ENXIO);
218
219 device_set_desc(dev, "Rockchip I2S");
220 return (BUS_PROBE_DEFAULT);
221 }
222
223 static int
rk_i2s_attach(device_t dev)224 rk_i2s_attach(device_t dev)
225 {
226 struct rk_i2s_softc *sc;
227 int error;
228 phandle_t node;
229
230 sc = device_get_softc(dev);
231 sc->dev = dev;
232
233 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
234
235 if (bus_alloc_resources(dev, rk_i2s_spec, sc->res) != 0) {
236 device_printf(dev, "cannot allocate resources for device\n");
237 error = ENXIO;
238 goto fail;
239 }
240
241 error = clk_get_by_ofw_name(dev, 0, "i2s_hclk", &sc->hclk);
242 if (error != 0) {
243 device_printf(dev, "cannot get i2s_hclk clock\n");
244 goto fail;
245 }
246
247 error = clk_get_by_ofw_name(dev, 0, "i2s_clk", &sc->clk);
248 if (error != 0) {
249 device_printf(dev, "cannot get i2s_clk clock\n");
250 goto fail;
251 }
252
253 /* Activate the module clock. */
254 error = clk_enable(sc->hclk);
255 if (error != 0) {
256 device_printf(dev, "cannot enable i2s_hclk clock\n");
257 goto fail;
258 }
259
260 node = ofw_bus_get_node(dev);
261 if (OF_hasprop(node, "rockchip,grf") &&
262 syscon_get_by_ofw_property(dev, node,
263 "rockchip,grf", &sc->grf) != 0) {
264 device_printf(dev, "cannot get grf driver handle\n");
265 return (ENXIO);
266 }
267
268 rk_i2s_init(sc);
269
270 OF_device_register_xref(OF_xref_from_node(node), dev);
271
272 return (0);
273
274 fail:
275 rk_i2s_detach(dev);
276 return (error);
277 }
278
279 static int
rk_i2s_detach(device_t dev)280 rk_i2s_detach(device_t dev)
281 {
282 struct rk_i2s_softc *i2s;
283
284 i2s = device_get_softc(dev);
285
286 if (i2s->hclk != NULL)
287 clk_release(i2s->hclk);
288 if (i2s->clk)
289 clk_release(i2s->clk);
290
291 if (i2s->intrhand != NULL)
292 bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand);
293
294 bus_release_resources(dev, rk_i2s_spec, i2s->res);
295 mtx_destroy(&i2s->mtx);
296
297 return (0);
298 }
299
300 static int
rk_i2s_dai_init(device_t dev,uint32_t format)301 rk_i2s_dai_init(device_t dev, uint32_t format)
302 {
303 uint32_t val, txcr, rxcr;
304 struct rk_i2s_softc *sc;
305 int fmt, pol, clk;
306
307 sc = device_get_softc(dev);
308
309 fmt = AUDIO_DAI_FORMAT_FORMAT(format);
310 pol = AUDIO_DAI_FORMAT_POLARITY(format);
311 clk = AUDIO_DAI_FORMAT_CLOCK(format);
312
313 /* Set format */
314 val = RK_I2S_READ_4(sc, I2S_CKR);
315
316 val &= ~(I2S_CKR_MSS_MASK);
317 switch (clk) {
318 case AUDIO_DAI_CLOCK_CBM_CFM:
319 val |= I2S_CKR_MSS_MASTER;
320 break;
321 case AUDIO_DAI_CLOCK_CBS_CFS:
322 val |= I2S_CKR_MSS_SLAVE;
323 break;
324 default:
325 return (EINVAL);
326 }
327
328 switch (pol) {
329 case AUDIO_DAI_POLARITY_IB_NF:
330 val |= I2S_CKR_CKP;
331 break;
332 case AUDIO_DAI_POLARITY_NB_NF:
333 val &= ~I2S_CKR_CKP;
334 break;
335 default:
336 return (EINVAL);
337 }
338
339 RK_I2S_WRITE_4(sc, I2S_CKR, val);
340
341 txcr = I2S_TXCR_VDW_16 | I2S_CSR_2;
342 rxcr = I2S_RXCR_VDW_16 | I2S_CSR_2;
343
344 switch (fmt) {
345 case AUDIO_DAI_FORMAT_I2S:
346 txcr |= I2S_TXCR_IBM_NORMAL;
347 rxcr |= I2S_RXCR_IBM_NORMAL;
348 break;
349 case AUDIO_DAI_FORMAT_LJ:
350 txcr |= I2S_TXCR_IBM_LJ;
351 rxcr |= I2S_RXCR_IBM_LJ;
352 break;
353 case AUDIO_DAI_FORMAT_RJ:
354 txcr |= I2S_TXCR_IBM_RJ;
355 rxcr |= I2S_RXCR_IBM_RJ;
356 break;
357 case AUDIO_DAI_FORMAT_DSPA:
358 txcr |= I2S_TXCR_TFS_PCM;
359 rxcr |= I2S_RXCR_TFS_PCM;
360 txcr |= I2S_TXCR_PBM_1;
361 rxcr |= I2S_RXCR_PBM_1;
362 break;
363 case AUDIO_DAI_FORMAT_DSPB:
364 txcr |= I2S_TXCR_TFS_PCM;
365 rxcr |= I2S_RXCR_TFS_PCM;
366 txcr |= I2S_TXCR_PBM_2;
367 rxcr |= I2S_RXCR_PBM_2;
368 break;
369 default:
370 return EINVAL;
371 }
372
373 RK_I2S_WRITE_4(sc, I2S_TXCR, txcr);
374 RK_I2S_WRITE_4(sc, I2S_RXCR, rxcr);
375
376 RK_I2S_WRITE_4(sc, I2S_XFER, 0);
377
378 return (0);
379 }
380
381
382 static int
rk_i2s_dai_intr(device_t dev,struct snd_dbuf * play_buf,struct snd_dbuf * rec_buf)383 rk_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf)
384 {
385 struct rk_i2s_softc *sc;
386 uint32_t status;
387 uint32_t level;
388 uint32_t val = 0x00;
389 int ret = 0;
390
391 sc = device_get_softc(dev);
392
393 RK_I2S_LOCK(sc);
394 status = RK_I2S_READ_4(sc, I2S_INTSR);
395
396 if (status & I2S_INTSR_TXEI) {
397 level = RK_I2S_READ_4(sc, I2S_TXFIFOLR) & TXFIFO0LR_MASK;
398 uint8_t *samples;
399 uint32_t count, size, readyptr, written;
400 count = sndbuf_getready(play_buf);
401 if (count > FIFO_SIZE - 1)
402 count = FIFO_SIZE - 1;
403 size = sndbuf_getsize(play_buf);
404 readyptr = sndbuf_getreadyptr(play_buf);
405
406 samples = (uint8_t*)sndbuf_getbuf(play_buf);
407 written = 0;
408 for (; level < count; level++) {
409 val = (samples[readyptr++ % size] << 0);
410 val |= (samples[readyptr++ % size] << 8);
411 val |= (samples[readyptr++ % size] << 16);
412 val |= (samples[readyptr++ % size] << 24);
413 written += 4;
414 RK_I2S_WRITE_4(sc, I2S_TXDR, val);
415 }
416 sc->play_ptr += written;
417 sc->play_ptr %= size;
418 ret |= AUDIO_DAI_PLAY_INTR;
419 }
420
421 if (status & I2S_INTSR_RXFI) {
422 level = RK_I2S_READ_4(sc, I2S_RXFIFOLR) & RXFIFO0LR_MASK;
423 uint8_t *samples;
424 uint32_t count, size, freeptr, recorded;
425 count = sndbuf_getfree(rec_buf);
426 size = sndbuf_getsize(rec_buf);
427 freeptr = sndbuf_getfreeptr(rec_buf);
428 samples = (uint8_t*)sndbuf_getbuf(rec_buf);
429 recorded = 0;
430 if (level > count / 4)
431 level = count / 4;
432
433 for (; level > 0; level--) {
434 val = RK_I2S_READ_4(sc, I2S_RXDR);
435 samples[freeptr++ % size] = val & 0xff;
436 samples[freeptr++ % size] = (val >> 8) & 0xff;
437 samples[freeptr++ % size] = (val >> 16) & 0xff;
438 samples[freeptr++ % size] = (val >> 24) & 0xff;
439 recorded += 4;
440 }
441 sc->rec_ptr += recorded;
442 sc->rec_ptr %= size;
443 ret |= AUDIO_DAI_REC_INTR;
444 }
445
446 RK_I2S_UNLOCK(sc);
447
448 return (ret);
449 }
450
451 static struct pcmchan_caps *
rk_i2s_dai_get_caps(device_t dev)452 rk_i2s_dai_get_caps(device_t dev)
453 {
454 return (&rk_i2s_caps);
455 }
456
457 static int
rk_i2s_dai_trigger(device_t dev,int go,int pcm_dir)458 rk_i2s_dai_trigger(device_t dev, int go, int pcm_dir)
459 {
460 struct rk_i2s_softc *sc = device_get_softc(dev);
461 uint32_t val;
462 uint32_t clear_bit;
463
464 if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC))
465 return (EINVAL);
466
467 switch (go) {
468 case PCMTRIG_START:
469 val = RK_I2S_READ_4(sc, I2S_INTCR);
470 if (pcm_dir == PCMDIR_PLAY)
471 val |= I2S_INTCR_TXEIE;
472 else if (pcm_dir == PCMDIR_REC)
473 val |= I2S_INTCR_RXFIE;
474 RK_I2S_WRITE_4(sc, I2S_INTCR, val);
475
476 val = I2S_XFER_TXS_START | I2S_XFER_RXS_START;
477 RK_I2S_WRITE_4(sc, I2S_XFER, val);
478 break;
479
480 case PCMTRIG_STOP:
481 case PCMTRIG_ABORT:
482 val = RK_I2S_READ_4(sc, I2S_INTCR);
483 if (pcm_dir == PCMDIR_PLAY)
484 val &= ~I2S_INTCR_TXEIE;
485 else if (pcm_dir == PCMDIR_REC)
486 val &= ~I2S_INTCR_RXFIE;
487 RK_I2S_WRITE_4(sc, I2S_INTCR, val);
488
489 /*
490 * If there is no other activity going on, stop transfers
491 */
492 if ((val & (I2S_INTCR_TXEIE | I2S_INTCR_RXFIE)) == 0) {
493 RK_I2S_WRITE_4(sc, I2S_XFER, 0);
494
495 if (pcm_dir == PCMDIR_PLAY)
496 clear_bit = I2S_CLR_TXC;
497 else if (pcm_dir == PCMDIR_REC)
498 clear_bit = I2S_CLR_RXC;
499 else
500 return (EINVAL);
501
502 val = RK_I2S_READ_4(sc, I2S_CLR);
503 val |= clear_bit;
504 RK_I2S_WRITE_4(sc, I2S_CLR, val);
505
506 while ((RK_I2S_READ_4(sc, I2S_CLR) & clear_bit) != 0)
507 DELAY(1);
508 }
509
510 RK_I2S_LOCK(sc);
511 if (pcm_dir == PCMDIR_PLAY)
512 sc->play_ptr = 0;
513 else
514 sc->rec_ptr = 0;
515 RK_I2S_UNLOCK(sc);
516 break;
517 }
518
519 return (0);
520 }
521
522 static uint32_t
rk_i2s_dai_get_ptr(device_t dev,int pcm_dir)523 rk_i2s_dai_get_ptr(device_t dev, int pcm_dir)
524 {
525 struct rk_i2s_softc *sc;
526 uint32_t ptr;
527
528 sc = device_get_softc(dev);
529
530 RK_I2S_LOCK(sc);
531 if (pcm_dir == PCMDIR_PLAY)
532 ptr = sc->play_ptr;
533 else
534 ptr = sc->rec_ptr;
535 RK_I2S_UNLOCK(sc);
536
537 return ptr;
538 }
539
540 static int
rk_i2s_dai_setup_intr(device_t dev,driver_intr_t intr_handler,void * intr_arg)541 rk_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg)
542 {
543 struct rk_i2s_softc *sc = device_get_softc(dev);
544
545 if (bus_setup_intr(dev, sc->res[1],
546 INTR_TYPE_AV | INTR_MPSAFE, NULL, intr_handler, intr_arg,
547 &sc->intrhand)) {
548 device_printf(dev, "cannot setup interrupt handler\n");
549 return (ENXIO);
550 }
551
552 return (0);
553 }
554
555 static uint32_t
rk_i2s_dai_set_chanformat(device_t dev,uint32_t format)556 rk_i2s_dai_set_chanformat(device_t dev, uint32_t format)
557 {
558
559 return (0);
560 }
561
562 static int
rk_i2s_dai_set_sysclk(device_t dev,unsigned int rate,int dai_dir)563 rk_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir)
564 {
565 struct rk_i2s_softc *sc;
566 int error;
567
568 sc = device_get_softc(dev);
569 error = clk_disable(sc->clk);
570 if (error != 0) {
571 device_printf(sc->dev, "could not disable i2s_clk clock\n");
572 return (error);
573 }
574
575 error = clk_set_freq(sc->clk, rate, CLK_SET_ROUND_DOWN);
576 if (error != 0)
577 device_printf(sc->dev, "could not set i2s_clk freq\n");
578
579 error = clk_enable(sc->clk);
580 if (error != 0) {
581 device_printf(sc->dev, "could not enable i2s_clk clock\n");
582 return (error);
583 }
584
585 return (0);
586 }
587
588 static uint32_t
rk_i2s_dai_set_chanspeed(device_t dev,uint32_t speed)589 rk_i2s_dai_set_chanspeed(device_t dev, uint32_t speed)
590 {
591 struct rk_i2s_softc *sc;
592 int error;
593 uint32_t val;
594 uint32_t bus_clock_div, lr_clock_div;
595 uint64_t bus_clk_freq;
596 uint64_t clk_freq;
597
598 sc = device_get_softc(dev);
599
600 /* Set format */
601 val = RK_I2S_READ_4(sc, I2S_CKR);
602
603 if ((val & I2S_CKR_MSS_SLAVE) == 0) {
604 error = clk_get_freq(sc->clk, &clk_freq);
605 if (error != 0) {
606 device_printf(sc->dev, "failed to get clk frequency: err=%d\n", error);
607 return (error);
608 }
609 bus_clk_freq = 2 * 32 * speed;
610 bus_clock_div = DIV_ROUND_CLOSEST(clk_freq, bus_clk_freq);
611 lr_clock_div = bus_clk_freq / speed;
612
613 val &= ~(I2S_CKR_MDIV_MASK | I2S_CKR_RSD_MASK | I2S_CKR_TSD_MASK);
614 val |= I2S_CKR_MDIV(bus_clock_div);
615 val |= I2S_CKR_RSD(lr_clock_div);
616 val |= I2S_CKR_TSD(lr_clock_div);
617
618 RK_I2S_WRITE_4(sc, I2S_CKR, val);
619 }
620
621 return (speed);
622 }
623
624 static device_method_t rk_i2s_methods[] = {
625 /* Device interface */
626 DEVMETHOD(device_probe, rk_i2s_probe),
627 DEVMETHOD(device_attach, rk_i2s_attach),
628 DEVMETHOD(device_detach, rk_i2s_detach),
629
630 DEVMETHOD(audio_dai_init, rk_i2s_dai_init),
631 DEVMETHOD(audio_dai_setup_intr, rk_i2s_dai_setup_intr),
632 DEVMETHOD(audio_dai_set_sysclk, rk_i2s_dai_set_sysclk),
633 DEVMETHOD(audio_dai_set_chanspeed, rk_i2s_dai_set_chanspeed),
634 DEVMETHOD(audio_dai_set_chanformat, rk_i2s_dai_set_chanformat),
635 DEVMETHOD(audio_dai_intr, rk_i2s_dai_intr),
636 DEVMETHOD(audio_dai_get_caps, rk_i2s_dai_get_caps),
637 DEVMETHOD(audio_dai_trigger, rk_i2s_dai_trigger),
638 DEVMETHOD(audio_dai_get_ptr, rk_i2s_dai_get_ptr),
639
640 DEVMETHOD_END
641 };
642
643 static driver_t rk_i2s_driver = {
644 "i2s",
645 rk_i2s_methods,
646 sizeof(struct rk_i2s_softc),
647 };
648
649 DRIVER_MODULE(rk_i2s, simplebus, rk_i2s_driver, 0, 0);
650 SIMPLEBUS_PNP_INFO(compat_data);
651