Searched refs:FGETSIGN (Results 1 – 8 of 8) sorted by relevance
| /freebsd-14-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 511 FGETSIGN, enumerator
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAGDumper.cpp | 299 case ISD::FGETSIGN: return "fgetsign"; in getOperationName()
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| HD | TargetLowering.cpp | 2691 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT); in SimplifyDemandedBits()
2692 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); in SimplifyDemandedBits()
2699 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Src); in SimplifyDemandedBits()
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| HD | SelectionDAG.cpp | 3874 case ISD::FGETSIGN: in computeKnownBits()
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| HD | TargetLoweringBase.cpp | 712 setOperationAction({ISD::FGETSIGN, ISD::CONCAT_VECTORS, in initActions()
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| /freebsd-14-stable/contrib/llvm-project/llvm/include/llvm/Target/ |
| HD | TargetSelectionDAG.td | 521 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 716 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); in X86TargetLowering()
717 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); in X86TargetLowering()
32419 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); in LowerOperation()
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| /freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| HD | ARMISelLowering.cpp | 1060 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand); in ARMTargetLowering()
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