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Searched refs:D15 (Results 1 – 25 of 54) sorted by relevance

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/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
HDHexagonDisassembler.cpp220 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
228 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
236 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
244 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
252 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
260 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
268 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
276 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
607 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; in DecodeDoubleRegsRegisterClass()
/freebsd-14-stable/lib/msun/ld128/
HDs_expl.c194 D15 = 7.6478532249581686e-13, /* 0x1.ae892e3D16fcep-41 */ variable
252 dx * (D14 + dx * (D15 + dx * (D16 + in expm1l()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMBaseRegisterInfo.h105 case D15: case D14: case D13: case D12: in isARMArea3Register()
HDARMRegisterInfo.td136 def D15 : ARMReg<15, "d15", [S30, S31]>, DwarfRegNum<[271]>;
166 def Q7 : ARMReg< 7, "q7", [D14, D15]>;
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
HDAArch64BaseInfo.h146 case AArch64::D15: return AArch64::B15; in getBRegFromDReg()
186 case AArch64::B15: return AArch64::D15; in getDRegFromBReg()
/freebsd-14-stable/sys/contrib/device-tree/src/arm64/ti/
HDk3-am642-phyboard-electra-rdk.dts162 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
HDk3-am642-sk.dts242 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
HDk3-am642-evm.dts222 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonFrameLowering.cpp251 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) in getMax32BitSubRegister()
801 .addDef(Hexagon::D15) in insertEpilogueInBlock()
851 .addDef(Hexagon::D15) in insertEpilogueInBlock()
857 .addDef(Hexagon::D15) in insertEpilogueInBlock()
878 .addDef(Hexagon::D15) in insertEpilogueInBlock()
1115 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) { in insertCFIInstructionsAt()
HDHexagonDepMappings.td85 def L4_return_map_to_raw_fAlias : InstAlias<"if (!$Pv4) dealloc_return", (L4_return_f D15, PredRegs…
86 …tAlias : InstAlias<"if (!$Pv4.new) dealloc_return:nt", (L4_return_fnew_pnt D15, PredRegs:$Pv4, R30…
87 …_ptAlias : InstAlias<"if (!$Pv4.new) dealloc_return:t", (L4_return_fnew_pt D15, PredRegs:$Pv4, R30…
88 def L4_return_map_to_raw_tAlias : InstAlias<"if ($Pv4) dealloc_return", (L4_return_t D15, PredRegs:…
89 …ntAlias : InstAlias<"if ($Pv4.new) dealloc_return:nt", (L4_return_tnew_pnt D15, PredRegs:$Pv4, R30…
90 …w_ptAlias : InstAlias<"if ($Pv4.new) dealloc_return:t", (L4_return_tnew_pt D15, PredRegs:$Pv4, R30…
94 def L6_deallocframe_map_to_rawAlias : InstAlias<"deallocframe", (L2_deallocframe D15, R30)>;
95 def L6_return_map_to_rawAlias : InstAlias<"dealloc_return", (L4_return D15, R30)>;
HDHexagonRegisterInfo.td152 def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>;
546 (add (sequence "D%u", 0, 4), (sequence "D%u", 6, 13), D5, D14, D15)>;
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64PBQPRegAlloc.cpp63 case AArch64::D15: in isOdd()
HDAArch64CallingConvention.td493 CCIfType<[f64], CCAssignToReg<[D12, D13, D14, D15]>>,
561 D12, D13, D14, D15)>;
573 D12, D13, D14, D15)>;
682 D12, D13, D14, D15)>;
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
HDSparcRegisterInfo.td225 def D15 : Rd<30, "f30", [F30, F31]>, DwarfRegNum<[87]>;
288 def Q7 : Rq<28, "f28", [D14, D15]>;
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/
HDSparcDisassembler.cpp88 SP::D14, SP::D30, SP::D15, SP::D31 };
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
HDAArch64AsmBackend.cpp732 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15) in generateCompactUnwindEncoding()
HDAArch64MCTargetDesc.cpp188 {codeview::RegisterId::ARM64_D15, AArch64::D15}, in initLLVMToCVRegMapping()
/freebsd-14-stable/sys/contrib/device-tree/src/arm/
HDam335x-boneblue.dts455 "UART1_TX", /* D15 */
HDam335x-guardian.dts504 /* (D15) uart1_txd.uart1_txd */
HDste-ux500-samsung-codina-tmo.dts776 /* Data lines D12-D15 GPIO82..GPIO85 */
HDste-ux500-samsung-gavini.dts630 /* Data lines D12-D15 GPIO82..GPIO85 */
HDste-ux500-samsung-janice.dts719 /* Data lines D12-D15 GPIO82..GPIO85 */
HDste-ux500-samsung-codina.dts936 /* Data lines D12-D15 GPIO82..GPIO85 */
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
HDARMMCTargetDesc.cpp295 {codeview::RegisterId::ARM_ND15, ARM::D15}, in initLLVMToCVRegMapping()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsRegisterInfo.td411 D10, D11, D12, D13, D14, D15)>;

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