Searched refs:Cascade (Results 1 – 7 of 7) sorted by relevance
72 unsigned Cascade = 0; member106 unsigned getCascade(Register Reg) const { return Info[Reg].Cascade; } in getCascade()108 void setCascade(Register Reg, unsigned Cascade) { in setCascade() argument110 Info[Reg].Cascade = Cascade; in setCascade()114 unsigned Cascade = getCascade(Reg); in getOrAssignNewCascade() local115 if (!Cascade) { in getOrAssignNewCascade()116 Cascade = NextCascade++; in getOrAssignNewCascade()117 setCascade(Reg, Cascade); in getOrAssignNewCascade()119 return Cascade; in getOrAssignNewCascade()123 unsigned Cascade = getCascade(Reg); in getCascadeOrCurrentNext() local[all …]
202 unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg()); in canEvictInterferenceBasedOnCost() local240 if (Cascade == IntfCascade) in canEvictInterferenceBasedOnCost()243 if (Cascade < IntfCascade) { in canEvictInterferenceBasedOnCost()
487 unsigned Cascade = ExtraInfo->getOrAssignNewCascade(VirtReg.reg()); in evictInterference() local490 << " interference: Cascade " << Cascade << '\n'); in evictInterference()511 assert((ExtraInfo->getCascade(Intf->reg()) < Cascade || in evictInterference()514 ExtraInfo->setCascade(Intf->reg(), Cascade); in evictInterference()
615 unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg()); in loadInterferenceFeatures() local649 if (Cascade <= IntfCascade) { in loadInterferenceFeatures()
246 def : ReadAdvance<ReadFMA32Addend, 2>; // Cascade FMA248 def : ReadAdvance<ReadFMA64Addend, 2>; // Cascade FMA
1446 UINT8 Cascade[2]; member1465 UINT8 Cascade[8]; member1481 UINT8 Cascade; member1538 UINT8 Cascade; member
10209 Cascade fir