Home
last modified time | relevance | path

Searched refs:CONCAT_VECTORS (Results 1 – 25 of 27) sorted by relevance

12

/freebsd-14-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeVectorTypes.cpp767 case ISD::CONCAT_VECTORS: in ScalarizeVectorOperand()
1084 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; in SplitVectorResult()
1571 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps); in SplitVecRes_CONCAT_VECTORS()
1574 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps); in SplitVecRes_CONCAT_VECTORS()
1899 ISD::CONCAT_VECTORS, dl, OtherVT, in SplitVecRes_OverflowOp()
2553 DAG.getNode(ISD::CONCAT_VECTORS, dl, OtherVT, SDValue(LoNode, OtherNo), in SplitVecRes_FFREXP()
2733 if (Inputs[SrcRegIdx].getOpcode() == ISD::CONCAT_VECTORS && in SplitVecRes_VECTOR_SHUFFLE()
2774 ISD::CONCAT_VECTORS, DL, in SplitVecRes_VECTOR_SHUFFLE()
3144 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; in SplitVectorOperand()
3319 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); in SplitVecOp_VSELECT()
[all …]
HDDAGCombiner.cpp1957 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); in visit()
11780 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
11781 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
11821 ISD::CONCAT_VECTORS, DL, VT, in ConvertSelectToConcatVector()
12568 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
12569 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
13113 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads); in CombineExtLoad()
14884 if (!Src.hasOneUse() || Src.getOpcode() != ISD::CONCAT_VECTORS) in foldExtendVectorInregToExtendOfSubvector()
15121 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { in visitTRUNCATE()
15158 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds); in visitTRUNCATE()
[all …]
HDSelectionDAGDumper.cpp326 case ISD::CONCAT_VECTORS: return "concat_vectors"; in getOperationName()
HDSelectionDAG.cpp3281 case ISD::CONCAT_VECTORS: { in computeKnownBits()
4935 case ISD::CONCAT_VECTORS: { in ComputeNumSignBits()
5255 case ISD::CONCAT_VECTORS: in canCreateUndefOrPoison()
5967 case ISD::CONCAT_VECTORS: in getNode()
6381 if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::CONCAT_VECTORS) in FoldConstantArithmetic()
6927 case ISD::CONCAT_VECTORS: { in getNode()
7194 if (N2C && N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
7312 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
7452 case ISD::CONCAT_VECTORS: { in getNode()
10061 case ISD::CONCAT_VECTORS: in getNode()
HDLegalizeDAG.cpp1508 Node->getOpcode() == ISD::CONCAT_VECTORS) && in ExpandVectorBuildThroughStack()
3465 case ISD::CONCAT_VECTORS: in ExpandNode()
5617 DAG.getNode(MidVT == NewEltVT ? ISD::BUILD_VECTOR : ISD::CONCAT_VECTORS, in PromoteNode()
5740 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts); in PromoteNode()
HDSelectionDAGBuilder.cpp406 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
4079 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps)); in visitShuffleVector()
4097 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1); in visitShuffleVector()
4098 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2); in visitShuffleVector()
5964 case ISD::CONCAT_VECTORS: in getUnderlyingArgRegs()
12468 SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, InVec0, InVec1); in visitVectorInterleave()
12476 Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Res.getValue(0), in visitVectorInterleave()
HDLegalizeIntegerTypes.cpp147 case ISD::CONCAT_VECTORS: in PromoteIntegerResult()
1673 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); in PromoteIntRes_TRUNCATE()
1927 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; in PromoteIntegerOperand()
5955 DAG.getNode(ISD::CONCAT_VECTORS, dl, in PromoteIntRes_CONCAT_VECTORS()
HDTargetLowering.cpp1325 case ISD::CONCAT_VECTORS: { in SimplifyDemandedBits()
3272 case ISD::CONCAT_VECTORS: { in SimplifyDemandedVectorElts()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonISelLoweringHVX.cpp177 setOperationAction(ISD::CONCAT_VECTORS, P, Custom); in initializeHVXLowering()
231 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
275 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
388 setOperationAction(ISD::CONCAT_VECTORS, BoolV, Custom); in initializeHVXLowering()
439 setTargetDAGCombine({ISD::CONCAT_VECTORS, ISD::TRUNCATE, ISD::VSELECT}); in initializeHVXLowering()
550 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
1391 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SubV, V1}); in insertHvxSubvectorReg()
1392 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SubV}); in insertHvxSubvectorReg()
1438 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SingleV, V1}); in insertHvxSubvectorReg()
1439 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SingleV}); in insertHvxSubvectorReg()
[all …]
HDHexagonISelLowering.cpp1665 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE, in HexagonTargetLowering()
1715 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom); in HexagonTargetLowering()
2195 return Op.getOpcode() == ISD::CONCAT_VECTORS || in isTargetCanonicalConstantNode()
2457 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, in LowerVECTOR_SHIFT()
2918 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, Concats); in appendUndef()
3364 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
HDHexagonISelDAGToDAGHVX.cpp1910 LV = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, {L0, L1}); in scalarizeShuffle()
/freebsd-14-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDISDOpcodes.h557 CONCAT_VECTORS, enumerator
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86ISelLowering.cpp1651 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
1748 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
2004 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
2144 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
2272 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32f16, Custom); in X86TargetLowering()
2310 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f16, Custom); in X86TargetLowering()
2339 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
2358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32bf16, Custom); in X86TargetLowering()
2511 ISD::CONCAT_VECTORS, in X86TargetLowering()
4055 if (N->getOpcode() == ISD::CONCAT_VECTORS) { in collectConcatOps()
[all …]
HDX86ISelLoweringCall.cpp1051 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v64i1, Lo, Hi); in getv64i1Argument()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/VE/
HDVECustomDAG.cpp253 case ISD::CONCAT_VECTORS: in getIdiomaticVectorType()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp1101 ISD::SIGN_EXTEND_INREG, ISD::CONCAT_VECTORS, in AArch64TargetLowering()
1519 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in AArch64TargetLowering()
1583 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in AArch64TargetLowering()
1660 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in AArch64TargetLowering()
1876 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
2044 setOperationAction(ISD::CONCAT_VECTORS, VT, Default); in addTypeForFixedLengthSVE()
6411 SDValue TruncExt = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i16, in LowerTruncateVectorStore()
6854 case ISD::CONCAT_VECTORS: in LowerOperation()
12028 SourceVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v16i8, SourceVec, in ReconstructShuffleWithRuntimeMask()
12149 Src = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v16i8, Src, in ReconstructShuffle()
[all …]
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
HDWebAssemblyISelLowering.cpp193 ISD::FP_ROUND, ISD::CONCAT_VECTORS}); in WebAssemblyTargetLowering()
2603 if (N->getOpcode() == ISD::CONCAT_VECTORS) { in performVectorTruncZeroCombine()
2772 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, PackedVT, Lo, Hi); in truncateVectorWithNARROW()
2900 case ISD::CONCAT_VECTORS: in PerformDAGCombine()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVISelLowering.cpp752 setOperationAction({ISD::TRUNCATE, ISD::CONCAT_VECTORS, in RISCVTargetLowering()
878 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1020 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1073 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1103 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1157 setOperationAction({ISD::BUILD_VECTOR, ISD::CONCAT_VECTORS}, VT, in RISCVTargetLowering()
1303 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1497 ISD::BUILD_VECTOR, ISD::CONCAT_VECTORS, in RISCVTargetLowering()
5121 if (V.getOpcode() == ISD::CONCAT_VECTORS) { in lowerVECTOR_SHUFFLE()
6159 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Op.getValueType(), LoRes, HiRes); in SplitVectorOp()
[all …]
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMISelLowering.cpp197 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
457 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in addMVEVectorTypes()
8146 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper); in LowerBUILD_VECTOR()
8284 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8925 if (ST->hasNEON() && V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) { in LowerVECTOR_SHUFFLE()
8943 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0), in LowerVECTOR_SHUFFLE()
9410 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ToVT, Ext, Ext1); in LowerVectorExtend()
9798 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
9835 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
10621 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG, Subtarget); in LowerOperation()
[all …]
/freebsd-14-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDTargetLoweringBase.cpp712 setOperationAction({ISD::FGETSIGN, ISD::CONCAT_VECTORS, in initActions()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDSIISelLowering.cpp335 case ISD::CONCAT_VECTORS: in SITargetLowering()
636 case ISD::CONCAT_VECTORS: in SITargetLowering()
5690 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitUnaryVectorOp()
5716 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitBinaryVectorOp()
5748 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitTernaryVectorOp()
6269 return DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, Pieces); in lowerLaneOp()
7433 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces); in lowerVECTOR_SHUFFLE()
8355 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads); in lowerSBuffer()
HDAMDGPUISelLowering.cpp434 setOperationAction(ISD::CONCAT_VECTORS, in AMDGPUTargetLowering()
1377 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
1811 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad); in SplitVectorLoad()
/freebsd-14-stable/contrib/llvm-project/llvm/include/llvm/Target/
HDTargetSelectionDAG.td797 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp2773 case ISD::CONCAT_VECTORS: in LowerOperation()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/LoongArch/
HDLoongArchISelLowering.cpp298 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in LoongArchTargetLowering()

12