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Searched refs:BUILD_VECTOR (Results 1 – 25 of 41) sorted by relevance

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/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDR600ISelDAGToDAG.cpp112 case ISD::BUILD_VECTOR: { in Select()
HDR600ISelLowering.cpp1773 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
1785 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1815 if (Arg.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1822 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && in PerformDAGCombine()
1882 if (Arg.getOpcode() != ISD::BUILD_VECTOR) in PerformDAGCombine()
1900 if (Arg.getOpcode() != ISD::BUILD_VECTOR) in PerformDAGCombine()
HDAMDGPUISelDAGToDAG.h50 assert(N->getOpcode() == ISD::BUILD_VECTOR && N->getNumOperands() == 2); in packConstantV2I16()
HDSIISelLowering.cpp325 case ISD::BUILD_VECTOR: in SITargetLowering()
353 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote); in SITargetLowering()
354 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32); in SITargetLowering()
367 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote); in SITargetLowering()
368 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v6i32); in SITargetLowering()
381 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote); in SITargetLowering()
382 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v8i32); in SITargetLowering()
395 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote); in SITargetLowering()
396 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v16i32); in SITargetLowering()
409 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote); in SITargetLowering()
[all …]
HDAMDGPUISelDAGToDAG.cpp312 case ISD::BUILD_VECTOR: in PreprocessISelDAG()
549 case ISD::BUILD_VECTOR: { in Select()
553 if (Opc == ISD::BUILD_VECTOR && NumVectorElts == 2) { in Select()
734 Addr.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) { in getBaseWithOffsetUsingSplitOR()
2993 if (Src.getOpcode() == ISD::BUILD_VECTOR && Src.getNumOperands() == 2 && in SelectVOP3PMods()
HDAMDGPUISelLowering.cpp688 if (BCSrc.getOpcode() == ISD::BUILD_VECTOR) { in fnegFoldsIntoOp()
4014 isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)) { in performShlCombine()
4150 if (Vec.getOpcode() == ISD::BUILD_VECTOR) { in performTruncateCombine()
4171 if (BV.getOpcode() == ISD::BUILD_VECTOR && in performTruncateCombine()
4949 if (BCSrc.getOpcode() == ISD::BUILD_VECTOR) { in performFNegCombine()
4973 DAG.getNode(ISD::BUILD_VECTOR, SL, BCSrc.getValueType(), Ops); in performFNegCombine()
5062 if (Src.getOpcode() == ISD::BUILD_VECTOR && in PerformDAGCombine()
5064 isOperationLegal(ISD::BUILD_VECTOR, DestVT))) { in PerformDAGCombine()
5094 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
5104 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
/freebsd-14-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDISDOpcodes.h529 BUILD_VECTOR, enumerator
HDSelectionDAG.h842 return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
851 return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
869 return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/LoongArch/
HDLoongArchISelDAGToDAG.cpp92 case ISD::BUILD_VECTOR: { in INITIALIZE_PASS()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/VE/
HDVECustomDAG.cpp256 case ISD::BUILD_VECTOR: in getIdiomaticVectorType()
HDVEISelLowering.cpp311 setOperationAction(ISD::BUILD_VECTOR, LegalMaskVT, Custom); in initVPUActions()
317 setOperationAction(ISD::BUILD_VECTOR, LegalVecVT, Custom); in initVPUActions()
1906 case ISD::BUILD_VECTOR: in LowerOperation()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAG.cpp190 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isConstantSplatVectorAllOnes()
239 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isConstantSplatVectorAllZeros()
280 if (N->getOpcode() != ISD::BUILD_VECTOR) in isBuildVectorOfConstantSDNodes()
293 if (N->getOpcode() != ISD::BUILD_VECTOR) in isBuildVectorOfConstantFPSDNodes()
323 if (N->getOpcode() != ISD::BUILD_VECTOR) in isVectorShrinkable()
364 if (ISD::BUILD_VECTOR != Op.getOpcode() && in matchUnaryPredicateImpl()
402 (LHS.getOpcode() != ISD::BUILD_VECTOR && in matchBinaryPredicate()
1136 case ISD::BUILD_VECTOR: { in VerifySDNode()
2803 case ISD::BUILD_VECTOR: { in isSplatValue()
3221 case ISD::BUILD_VECTOR: in computeKnownBits()
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HDDAGCombiner.cpp723 case ISD::BUILD_VECTOR: in getStoreSource()
1042 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) in isConstantOrConstantVector()
1059 if (V.getOpcode() != ISD::BUILD_VECTOR) in isAnyConstantBuildVector()
1956 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); in visit()
3790 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) in tryFoldToZero()
4539 assert(N1.getOpcode() == ISD::BUILD_VECTOR && "Unknown constant vector"); in visitMUL()
10368 if (N1.getOpcode() == ISD::BUILD_VECTOR) in visitSRA()
11782 Cond.getOpcode() == ISD::BUILD_VECTOR); in ConvertSelectToConcatVector()
12458 (OpRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
12514 if (OpRHS.getOpcode() == ISD::BUILD_VECTOR || in visitVSELECT()
[all …]
HDLegalizeVectorTypes.cpp58 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; in ScalarizeVectorResult()
1083 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; in SplitVectorResult()
2646 assert(Input1->getOpcode() == ISD::BUILD_VECTOR && in SplitVecRes_VECTOR_SHUFFLE()
2647 Input2->getOpcode() == ISD::BUILD_VECTOR && in SplitVecRes_VECTOR_SHUFFLE()
2949 if (Inputs[Idx]->getOpcode() == ISD::BUILD_VECTOR) in SplitVecRes_VECTOR_SHUFFLE()
2960 if (Inputs[Idx1]->getOpcode() == ISD::BUILD_VECTOR && in SplitVecRes_VECTOR_SHUFFLE()
2961 Inputs[Idx2]->getOpcode() == ISD::BUILD_VECTOR) in SplitVecRes_VECTOR_SHUFFLE()
2967 if (TmpInputs[Idx1]->getOpcode() == ISD::BUILD_VECTOR && in SplitVecRes_VECTOR_SHUFFLE()
2968 TmpInputs[Idx2]->getOpcode() == ISD::BUILD_VECTOR) in SplitVecRes_VECTOR_SHUFFLE()
4320 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; in WidenVectorResult()
[all …]
HDSelectionDAGDumper.cpp167 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; in getOperationName()
HDLegalizeVectorOps.cpp1168 TLI.getOperationAction(VT.isFixedLengthVector() ? ISD::BUILD_VECTOR in ExpandSELECT()
1513 !TLI.isOperationLegalOrCustom(ISD::BUILD_VECTOR, EVLVecVT)) || in ExpandVP_MERGE()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonISelLoweringHVX.cpp144 setOperationAction(ISD::BUILD_VECTOR, T, Custom); in initializeHVXLowering()
150 setOperationAction(ISD::BUILD_VECTOR, MVT::f16, Custom); in initializeHVXLowering()
175 setOperationAction(ISD::BUILD_VECTOR, P, Custom); in initializeHVXLowering()
229 setOperationAction(ISD::BUILD_VECTOR, T, Custom); in initializeHVXLowering()
273 setOperationAction(ISD::BUILD_VECTOR, T, Custom); in initializeHVXLowering()
387 setOperationAction(ISD::BUILD_VECTOR, BoolV, Custom); in initializeHVXLowering()
1637 SDValue T0 = DAG.getNode(ISD::BUILD_VECTOR, dl, in LowerHvxBuildVector()
3203 case ISD::BUILD_VECTOR: return LowerHvxBuildVector(Op, DAG); in LowerHvxOperation()
HDHexagonISelLowering.cpp1662 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR, in HexagonTargetLowering()
1710 setOperationAction(ISD::BUILD_VECTOR, NativeVT, Custom); in HexagonTargetLowering()
2380 case ISD::BUILD_VECTOR: in getSplatValue()
3369 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); in LowerOperation()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMISelLowering.cpp195 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in addTypeForNEON()
266 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in addMVEVectorTypes()
346 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in addMVEVectorTypes()
347 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom); in addMVEVectorTypes()
411 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in addMVEVectorTypes()
454 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in addMVEVectorTypes()
1033 {ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, ISD::INSERT_SUBVECTOR, in ARMTargetLowering()
1862 MAKE_CASE(ARMISD::BUILD_VECTOR) in getTargetNodeName()
7669 assert(BV.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!"); in LowerBuildVectorOfFPTrunc()
7722 assert(BV.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!"); in LowerBuildVectorOfFPExt()
[all …]
HDARMISelLowering.h294 BUILD_VECTOR, enumerator
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp493 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom); in NVPTXTargetLowering()
506 setOperationAction(ISD::BUILD_VECTOR, MVT::v2bf16, Custom); in NVPTXTargetLowering()
517 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom); in NVPTXTargetLowering()
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i8, Custom); in NVPTXTargetLowering()
2748 DAG.getNode(ISD::BUILD_VECTOR, DL, Op.getValueType(), VecElements); in LowerVectorArith()
2763 case ISD::BUILD_VECTOR: in LowerOperation()
3062 SDValue V2 = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, E0, E1); in LowerSTOREVector()
5887 return DCI.DAG.getNode(ISD::BUILD_VECTOR, DL, CCType, CCNode.getValue(0), in PerformSETCCCombine()
5970 return DCI.DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i8, E); in PerformVSELECTCombine()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
HDWebAssemblyISelLowering.cpp209 setOperationAction(ISD::BUILD_VECTOR, T, Custom); in WebAssemblyTargetLowering()
986 if (Op.getOpcode() == ISD::BUILD_VECTOR && TLO.LegalOps && TLO.LegalTys) in shouldSimplifyDemandedVectorElts()
1487 case ISD::BUILD_VECTOR: in LowerOperation()
2713 if (Vec.getOpcode() == ISD::BUILD_VECTOR) in extractSubVector()
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp872 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); in PPCTargetLowering()
989 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); in PPCTargetLowering()
990 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); in PPCTargetLowering()
991 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
992 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
1142 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); in PPCTargetLowering()
1143 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); in PPCTargetLowering()
1351 setOperationAction(ISD::BUILD_VECTOR, MVT::v512i1, Custom); in PPCTargetLowering()
1391 ISD::MUL, ISD::FMA, ISD::SINT_TO_FP, ISD::BUILD_VECTOR}); in PPCTargetLowering()
10057 if (RHS->getOpcode() != ISD::BUILD_VECTOR) { in lowerToXXSPLTI32DX()
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/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp1103 ISD::STORE, ISD::BUILD_VECTOR}); in AArch64TargetLowering()
1867 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in addTypeForNEON()
2043 setOperationAction(ISD::BUILD_VECTOR, VT, Default); in addTypeForFixedLengthSVE()
5003 if (N.getOpcode() != ISD::BUILD_VECTOR) in isExtendedBUILD_VECTOR()
5043 assert(N.getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR"); in skipExtensionForVectorMULL()
6860 case ISD::BUILD_VECTOR: in LowerOperation()
11954 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!"); in ReconstructShuffleWithRuntimeMask()
12046 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!"); in ReconstructShuffle()
13174 if (V1.getOpcode() == ISD::BUILD_VECTOR && in LowerVECTOR_SHUFFLE()
13839 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!"); in NormalizeBuildVector()
[all …]
/freebsd-14-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsSEISelDAGToDAG.cpp1081 case ISD::BUILD_VECTOR: { in trySelect()

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