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Searched refs:v16i16 (Results 1 – 25 of 34) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/clang/lib/Headers/
HDlasxintrin.h19 typedef short v16i16 __attribute__((vector_size(32), aligned(32))); typedef
52 return (__m256i)__builtin_lasx_xvsll_h((v16i16)_1, (v16i16)_2); in __lasx_xvsll_h()
71 ((__m256i)__builtin_lasx_xvslli_h((v16i16)(_1), (_2)))
88 return (__m256i)__builtin_lasx_xvsra_h((v16i16)_1, (v16i16)_2); in __lasx_xvsra_h()
107 ((__m256i)__builtin_lasx_xvsrai_h((v16i16)(_1), (_2)))
124 return (__m256i)__builtin_lasx_xvsrar_h((v16i16)_1, (v16i16)_2); in __lasx_xvsrar_h()
143 ((__m256i)__builtin_lasx_xvsrari_h((v16i16)(_1), (_2)))
160 return (__m256i)__builtin_lasx_xvsrl_h((v16i16)_1, (v16i16)_2); in __lasx_xvsrl_h()
179 ((__m256i)__builtin_lasx_xvsrli_h((v16i16)(_1), (_2)))
196 return (__m256i)__builtin_lasx_xvsrlr_h((v16i16)_1, (v16i16)_2); in __lasx_xvsrlr_h()
[all …]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/LoongArch/
HDLoongArchLASXInstrInfo.td27 (v16i16 (build_vector node:$e0, node:$e0, node:$e0, node:$e0,
1070 def PseudoXVBNZ_H : VecCond<loongarch_vall_nonzero, v16i16, LASX256>;
1076 def PseudoXVBZ_H : VecCond<loongarch_vall_zero, v16i16, LASX256>;
1093 def : Pat<(v16i16 (OpNode (v16i16 LASX256:$xj))),
1111 def : Pat<(OpNode (v16i16 LASX256:$xj), (v16i16 LASX256:$xk)),
1129 def : Pat<(OpNode (v16i16 LASX256:$xj), (v16i16 LASX256:$xk)),
1140 def : Pat<(OpNode (v16i16 LASX256:$xj), (v16i16 (SplatPat_simm5 simm5:$imm))),
1151 def : Pat<(OpNode (v16i16 LASX256:$xj), (v16i16 (SplatPat_uimm5 uimm5:$imm))),
1163 def : Pat<(OpNode (v16i16 LASX256:$xd), (v16i16 LASX256:$xj),
1164 (v16i16 LASX256:$xk)),
[all …]
HDLoongArchISelDAGToDAG.cpp119 ViaVecTy = Is256Vec ? MVT::v16i16 : MVT::v8i16; in INITIALIZE_PASS()
HDLoongArchRegisterInfo.td207 [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
HDLoongArchISelLowering.cpp62 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::v8f32, MVT::v4f64}; in LoongArchTargetLowering()
304 for (MVT VT : {MVT::v4i64, MVT::v8i32, MVT::v16i16, MVT::v32i8}) { in LoongArchTargetLowering()
1257 assert((VT.SimpleTy == MVT::v32i8 || VT.SimpleTy == MVT::v16i16 || in lower256BitShuffle()
1404 ViaVecTy = Is128Vec ? MVT::v8i16 : MVT::v16i16; in lowerBUILD_VECTOR()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86TargetTransformInfo.cpp403 { ISD::SHL, MVT::v16i16, { 1, 1, 1, 1 } }, // psllw in getArithmeticInstrCost()
404 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
405 { ISD::SRA, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
422 { ISD::SHL, MVT::v16i16, { 2, 7, 4, 4 } }, // psllw + split. in getArithmeticInstrCost()
423 { ISD::SRL, MVT::v16i16, { 2, 7, 4, 4 } }, // psrlw + split. in getArithmeticInstrCost()
424 { ISD::SRA, MVT::v16i16, { 2, 7, 4, 4 } }, // psraw + split. in getArithmeticInstrCost()
464 { ISD::SHL, MVT::v16i16,{ 2, 2, 1, 2 } }, // psllw in getArithmeticInstrCost()
465 { ISD::SRL, MVT::v16i16,{ 2, 2, 1, 2 } }, // psrlw in getArithmeticInstrCost()
466 { ISD::SRA, MVT::v16i16,{ 2, 2, 1, 2 } }, // psraw in getArithmeticInstrCost()
505 { ISD::SHL, MVT::v16i16,{ 3, 6, 4, 5 } }, // psllw + split. in getArithmeticInstrCost()
[all …]
HDX86InstrVecCompiler.td83 defm : subvector_subreg_lowering<VR128, v8i16, VR256, v16i16, sub_xmm>;
109 defm : subvector_subreg_lowering<VR256, v16i16, VR512, v32i16, sub_ymm>;
132 defm : subvec_zero_lowering<"DQA", VR128, v16i16, v8i16, sub_xmm>;
144 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i16, v8i16, sub_xmm>;
158 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v32i16, v16i16, sub_ymm>;
174 defm : subvec_zero_lowering<"DQAY", VR256, v32i16, v16i16, sub_ymm>;
HDX86CallingConv.td153 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
184 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
229 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
280 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64],
601 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64],
623 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64],
661 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], CCPassIndirect<i64>>,
725 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
768 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64],
784 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64],
[all …]
HDX86InstrSSE.td162 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
560 def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst),
568 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
2363 def : Pat<(v16i16 (and VR256:$src1, VR256:$src2)),
2370 def : Pat<(v16i16 (or VR256:$src1, VR256:$src2)),
2377 def : Pat<(v16i16 (xor VR256:$src1, VR256:$src2)),
2384 def : Pat<(v16i16 (X86andnp VR256:$src1, VR256:$src2)),
2423 def : Pat<(v16i16 (and VR256:$src1, VR256:$src2)),
2432 def : Pat<(v16i16 (or VR256:$src1, VR256:$src2)),
2441 def : Pat<(v16i16 (xor VR256:$src1, VR256:$src2)),
[all …]
HDX86ISelLowering.cpp1281 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom); in X86TargetLowering()
1403 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1418 addRegisterClass(MVT::v16i16, Subtarget.hasVLX() ? &X86::VR256XRegClass in X86TargetLowering()
1492 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1514 setOperationAction(ISD::SELECT, MVT::v16i16, Custom); in X86TargetLowering()
1519 for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1530 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1557 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1564 setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
1569 setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
[all …]
HDX86InstrFragmentsSIMD.td833 def loadv16i16 : PatFrag<(ops node:$ptr), (v16i16 (load node:$ptr))>;
902 (v16i16 (alignedload node:$ptr))>;
955 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
HDX86RegisterInfo.td773 def VR256 : RegisterClass<"X86", [v8f32, v4f64, v16f16, v16bf16, v32i8, v16i16, v8i32, v4i64],
808 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v16f16, v16bf16, v32i8, v16i16, v8i32, v4i64],
HDX86InstrAVX512.td338 def : Pat<(v16i16 immAllZerosV), (AVX512_256_SET0)>;
848 (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
881 (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
1438 def : Pat<(v16i16 (X86SubVBroadcastld128 addr:$src)),
3650 def : Pat<(alignedstore (v16i16 VR256X:$src), addr:$dst),
3660 def : Pat<(store (v16i16 VR256X:$src), addr:$dst),
4461 def : Pat<(v16i16 (X86vzmovl (v16i16 VR256X:$src))),
4464 (v8i16 (EXTRACT_SUBREG (v16i16 VR256X:$src), sub_xmm)))), sub_xmm)>;
4623 def : Pat<(alignednontemporalstore (v16i16 VR256X:$src), addr:$dst),
4636 def : Pat<(v16i16 (alignednontemporalload addr:$src)),
[all …]
HDX86InstrXOP.td398 def : Pat<(v16i16 (or (and VR256:$src3, VR256:$src1),
HDX86FastISel.cpp424 case MVT::v16i16: in X86FastEmitLoad()
596 case MVT::v16i16: in X86FastEmitStore()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDVOP3PInstructions.td837 def VOP_V8F32_V16I16_V16I16_V8F32 : VOPProfile <[v8f32, v16i16, v16i16, v8f32]>;
839 def VOP_V16I16_V16I16_V16I16_V16I16 : VOPProfile <[v16i16, v16i16, v16i16, v16i16]>;
844 def VOP_V4F32_V16I16_V16I16_V4F32 : VOPProfile <[v4f32, v16i16, v16i16, v4f32]>;
846 def VOP_V8I16_V16I16_V16I16_V8I16 : VOPProfile <[v8i16, v16i16, v16i16, v8i16]>;
1202 def F32_BF16_SWMMAC_w32 : VOP3PWMMA_Profile<[v8f32, v8i16, v16i16, v8f32], 1, 16, 0, 0>;
1204 def BF16_BF16_SWMMAC_w32 : VOP3PWMMA_Profile<[v8i16, v8i16, v16i16, v8i16], 1, 16, 0, 0>;
HDSIInstructions.td1714 def : BitConvert <v16i16, v16f16, SReg_256>;
1715 def : BitConvert <v16f16, v16i16, SReg_256>;
1716 def : BitConvert <v16i16, v16f16, VReg_256>;
1717 def : BitConvert <v16f16, v16i16, VReg_256>;
1719 def : BitConvert <v16i16, v8i32, VReg_256>;
1721 def : BitConvert <v16i16, v8f32, VReg_256>;
1723 def : BitConvert <v8i32, v16i16, VReg_256>;
1725 def : BitConvert <v8f32, v16i16, VReg_256>;
1727 def : BitConvert <v16i16, v4i64, VReg_256>;
1729 def : BitConvert <v16i16, v4f64, VReg_256>;
[all …]
HDSIISelLowering.cpp172 addRegisterClass(MVT::v16i16, &AMDGPU::SGPR_256RegClass); in SITargetLowering()
242 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand); in SITargetLowering()
252 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Expand); in SITargetLowering()
318 MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, MVT::v16f16, in SITargetLowering()
620 MVT::v4bf16, MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, in SITargetLowering()
706 setOperationAction(ISD::LOAD, MVT::v16i16, Promote); in SITargetLowering()
707 AddPromotedToType(ISD::LOAD, MVT::v16i16, MVT::v8i32); in SITargetLowering()
713 setOperationAction(ISD::STORE, MVT::v16i16, Promote); in SITargetLowering()
714 AddPromotedToType(ISD::STORE, MVT::v16i16, MVT::v8i32); in SITargetLowering()
764 {MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, MVT::v16f16, in SITargetLowering()
[all …]
HDSIRegisterInfo.td915 defm "" : SRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16, v16bf16], SGPR_256Regs, TTMP_25…
969 defm VReg_256 : VRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16, v16bf16], (add VGPR_256)>;
HDR600ISelLowering.cpp74 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Custom); in R600TargetLowering()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp554 {ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1}, in getCastInstrCost()
555 {ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1}, in getCastInstrCost()
584 {ISD::TRUNCATE, MVT::v16i16, MVT::v16i8, 1}, in getCastInstrCost()
704 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
705 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
731 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
732 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64TargetTransformInfo.cpp2537 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 1}, // uzp1 in getCastInstrCost()
2540 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2}, // 2 x uzp1 in getCastInstrCost()
2541 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i64, 6}, // (4 + 2) x uzp1 in getCastInstrCost()
2575 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
2576 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
2831 {ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f16, 2}, // 2*fcvtzs in getCastInstrCost()
2832 {ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f16, 2}, in getCastInstrCost()
3279 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 }, in getCmpSelInstrCost()
HDAArch64CallingConvention.td251 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], CCPassIndirect<i64>>,
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDValueTypes.td120 def v16i16 : VTVec<16, i16, 51>; // 16 x i16 vector value
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonPatternsHVX.td595 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i16)),

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