| /freebsd-13-stable/sys/contrib/openzfs/module/zfs/ |
| HD | bpobj.c | 928 struct space_range_arg *sra = arg; in space_range_cb() local 930 if (bp->blk_birth > sra->mintxg && bp->blk_birth <= sra->maxtxg) { in space_range_cb() 931 if (dsl_pool_sync_context(spa_get_dsl(sra->spa))) in space_range_cb() 932 sra->used += bp_get_dsize_sync(sra->spa, bp); in space_range_cb() 934 sra->used += bp_get_dsize(sra->spa, bp); in space_range_cb() 935 sra->comp += BP_GET_PSIZE(bp); in space_range_cb() 936 sra->uncomp += BP_GET_UCSIZE(bp); in space_range_cb() 968 struct space_range_arg sra = { 0 }; in bpobj_space_range() local 980 sra.spa = dmu_objset_spa(bpo->bpo_os); in bpobj_space_range() 981 sra.mintxg = mintxg; in bpobj_space_range() [all …]
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| /freebsd-13-stable/sys/contrib/openzfs/config/ |
| HD | always-compiler-options.m4 | 261 dnl # Check if cc supports -fno-ipa-sra option. 264 AC_MSG_CHECKING([whether $CC supports -fno-ipa-sra]) 267 CFLAGS="$CFLAGS -Werror -fno-ipa-sra" 270 NO_IPA_SRA=-fno-ipa-sra 282 dnl # Check if kernel cc supports -fno-ipa-sra option. 285 AC_MSG_CHECKING([whether $KERNEL_CC supports -fno-ipa-sra]) 290 CFLAGS="$CFLAGS -Werror -fno-ipa-sra" 300 KERNEL_NO_IPA_SRA=-fno-ipa-sra
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| HD | MipsInstrCompiler.td | 32 [(sra node:$src0, node:$src1), (sra node:$src0, (shiftMask node:$src1))]>;
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| HD | MicroMipsInstrInfo.td | 782 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>, 1233 def : MipsPat<(sra GPR32:$src, immZExt5:$imm), 1235 def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs), 1370 def : MipsInstAlias<"sra $rd, $rt, $rs", 1376 def : MipsInstAlias<"sra $rd, $rt", 1382 def : MipsInstAlias<"sra $rd, $shamt",
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| HD | MipsMSAInstrInfo.td | 2585 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>; 2586 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>; 2587 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>; 2588 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>; 2590 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3, 2592 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4, 2594 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5, 2596 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6, 3854 defm : MSAShiftPats<sra, "SRA">;
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| /freebsd-13-stable/sys/mips/include/ |
| HD | asm.h | 345 #define PTR_SRA sra 392 #define INT_SRA sra 438 #define LONG_SRA sra 477 #define REG_SRA sra
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| /freebsd-13-stable/lib/libtelnet/ |
| HD | Makefile | 19 SRCS+= encrypt.c auth.c enc_des.c sra.c pk.c
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| HD | WebAssemblyInstrInteger.td | 67 defm SHR_S : BinaryInt<sra, "shr_s", 0x75, 0x87>; 98 def : Pat<(sra I32:$lhs, (and I32:$rhs, 31)), (SHR_S_I32 I32:$lhs, I32:$rhs)>; 101 def : Pat<(sra I64:$lhs, (and I64:$rhs, 63)), (SHR_S_I64 I64:$lhs, I64:$rhs)>;
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| /freebsd-13-stable/usr.bin/sort/nls/ |
| HD | hu_HU.ISO8859-2.msg | 11 8 "A f�jl nem nyithat� meg olvas�sra"
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| /freebsd-13-stable/crypto/openssl/crypto/bn/asm/ |
| HD | s390x.S | 31 sra %r4,2 // cnt=len/4 140 sra %r4,2 // cnt=len/4 269 sra %r5,2 // len/4, use sra because it sets condition code 323 sra %r5,2 // len/4, use sra because it sets condition code
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| HD | sparcv8plus.S | 178 sra %o2,%g0,%o2 ! signx %o2 280 sra %o2,%g0,%o2 ! signx %o2 368 sra %o2,%g0,%o2 ! signx %o2 473 sra %o3,%g0,%o3 ! signx %o3 551 sra %o3,%g0,%o3 ! signx %o3
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/M68k/ |
| HD | M68kInstrShiftRotate.td | 95 defm ASR : MxSROp<"asr", sra, MxRODI_R, MxROOP_AS>;
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| /freebsd-13-stable/crypto/openssl/crypto/ |
| HD | sparccpuid.S | 209 sra %i2,%g0,%i0 222 sra %o0,%g0,%o0 ! we return signed int, remember?
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| HD | RISCVInstrInfo.td | 684 def SRA : ALU_rr<0b0100000, 0b101, "sra">, 1033 def : InstAlias<"sra $rd, $rs1, $shamt", 1268 def : PatGprUimmLog2XLen<sra, SRAI>; 1313 def : PatGprGpr<shiftop<sra>, SRA>; 1867 def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt), 1869 def : Pat<(i64 (sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt)), 1884 // occurs because SimplifyDemandedBits prefers srl over sra. 2004 def : PatGprGpr<shiftopw<sra>, SRAW, i32, i64>; 2017 def : PatGprImm<sra, SRAIW, uimm5, i32>;
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| HD | RISCVGISel.td | 94 def : Pat<(i32 (sra GPR:$rs1, (i32 GPR:$rs2))), (SRAW GPR:$rs1, GPR:$rs2)>;
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| HD | XtensaInstrInfo.td | 113 "sra\t$r, $t", []> { 152 [(set AR:$r, (sra AR:$t, uimm5:$sa))]> {
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| HD | PPCInstrAltivec.td | 1101 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 1103 def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 1105 def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 1151 def : Pat<(v4i32 (sra (sub v4i32:$vA, (vnot v4i32:$vB)), 1153 def : Pat<(v8i16 (sra (sub v8i16:$vA, (v8i16 (bitconvert(vnot v4i32:$vB)))), 1155 def : Pat<(v16i8 (sra (sub v16i8:$vA, (v16i8 (bitconvert(vnot v4i32:$vB)))), 1257 def : Pat<(v2i64 (sra v2i64:$vA, v2i64:$vB)),
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| HD | SparcInstr64Bit.td | 35 // Finally, sra shifts the low 32 bits and sign-extends to 64 bits. 47 defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, shift_imm6, I64Regs>;
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| /freebsd-13-stable/usr.bin/ee/nls/hu_HU.ISO8859-2/ |
| HD | ee.msg | 171 162 ".init.ee nem nyithat� meg �r�sra, konfigur�ci� nem lett mentve!"
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| HD | X86InstrShiftRotate.td | 228 defm SAR: ShiftRotate<"sar", MRM7r, MRM7m, sra, WriteShiftCL, WriteShift, WriteShiftCLLd, WriteShif… 681 defm SARX : ShiftX_Pats<sra>; 688 defm SARX : ShiftX_Pats<sra, "_EVEX">;
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| HD | ARMInstrInfo.td | 402 (i32 (sra node:$a, (i32 16)))>; 407 (mul (sext_bottom_16 node:$a), (sra node:$b, (i32 16)))>; 409 (mul (sra node:$a, (i32 16)), (sext_bottom_16 node:$b))>; 411 (mul (sra node:$a, (i32 16)), (sra node:$b, (i32 16)))>; 771 [shl, srl, sra, rotr]> { 782 [shl, srl, sra, rotr]> { 793 [shl,srl,sra,rotr]> { 804 [shl,srl,sra,rotr]> { 4158 def : ARMV6Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos), 4162 def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos), [all …]
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| HD | AMDGPUInstructions.td | 307 [(sra node:$src0, node:$src1), (sra node:$src0, (csh_mask node:$src1))]>;
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/ |
| HD | SelectionDAGCompat.td | 77 def : GINodeEquiv<G_ASHR, sra>;
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| HD | HexagonPatterns.td | 372 def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>; 1183 def: Pat<(sra I32:$Rs, (i32 16)), (A2_asrh I32:$Rs)>; 1290 def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)), 1292 def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)), 1451 def: Pat<(sra V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1457 def: Pat<(sra V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1733 def: Pat<(i32 (trunc (sra (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1761 def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1769 def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)),
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| HD | CSKYInstrInfo16Instr.td | 83 def ASR16 : R16_XZ_BINOP<0b1100, 0b10, "asr16", BinOpFrag<(sra node:$LHS, node:$RHS)>>; 114 def ASRI16 : I16_XZ_IMM5<2, "asri16", sra>;
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