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/freebsd-13-stable/sys/dev/cpufreq/
HDichss.c62 struct cf_setting sets[2]; /* Only two settings. */ member
98 static int ichss_settings(device_t dev, struct cf_setting *sets,
270 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; in ichss_attach()
271 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; in ichss_attach()
272 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; in ichss_attach()
273 sc->sets[0].lat = 1000; in ichss_attach()
274 sc->sets[0].dev = dev; in ichss_attach()
275 sc->sets[1] = sc->sets[0]; in ichss_attach()
289 ichss_settings(device_t dev, struct cf_setting *sets, int *count) in ichss_settings() argument
295 if (sets == NULL || count == NULL) in ichss_settings()
[all …]
/freebsd-13-stable/sys/contrib/device-tree/src/arm64/amazon/
HDalpine-v3.dtsi30 d-cache-sets = <256>;
33 i-cache-sets = <256>;
44 d-cache-sets = <256>;
47 i-cache-sets = <256>;
58 d-cache-sets = <256>;
61 i-cache-sets = <256>;
72 d-cache-sets = <256>;
75 i-cache-sets = <256>;
86 d-cache-sets = <256>;
89 i-cache-sets = <256>;
[all …]
/freebsd-13-stable/sys/x86/cpufreq/
HDsmist.c74 struct cf_setting sets[2]; /* Only two settings. */ member
83 static int smist_settings(device_t dev, struct cf_setting *sets,
392 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; in smist_attach()
393 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; in smist_attach()
394 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; in smist_attach()
395 sc->sets[0].lat = 1000; in smist_attach()
396 sc->sets[0].dev = dev; in smist_attach()
397 sc->sets[1] = sc->sets[0]; in smist_attach()
412 smist_settings(device_t dev, struct cf_setting *sets, int *count) in smist_settings() argument
418 if (sets == NULL || count == NULL) in smist_settings()
[all …]
HDp4tcc.c77 static int p4tcc_settings(device_t dev, struct cf_setting *sets,
236 p4tcc_settings(device_t dev, struct cf_setting *sets, int *count) in p4tcc_settings() argument
242 if (sets == NULL || count == NULL) in p4tcc_settings()
248 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count); in p4tcc_settings()
251 sets[i].freq = TCC_SPEED_PERCENT(val); in p4tcc_settings()
252 sets[i].dev = dev; in p4tcc_settings()
HDest.c867 static int est_settings(device_t dev, struct cf_setting *sets, int *count);
1063 struct cf_setting *sets; in est_acpi_info() local
1076 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); in est_acpi_info()
1077 if (sets == NULL) in est_acpi_info()
1080 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); in est_acpi_info()
1095 if (sets[i].freq > 0) { in est_acpi_info()
1096 error = est_set_id16(dev, sets[i].spec[0], strict); in est_acpi_info()
1100 "ignored.\n", sets[i].freq); in est_acpi_info()
1103 table[j].freq = sets[i].freq; in est_acpi_info()
1104 table[j].volts = sets[i].volts; in est_acpi_info()
[all …]
HDhwpstate_amd.c118 static int hwpstate_settings(device_t dev, struct cf_setting *sets, int *count);
287 hwpstate_settings(device_t dev, struct cf_setting *sets, int *count) in hwpstate_settings() argument
293 if (sets == NULL || count == NULL) in hwpstate_settings()
298 for (i = 0; i < sc->cfnum; i++, sets++) { in hwpstate_settings()
300 sets->freq = set.freq; in hwpstate_settings()
301 sets->volts = set.volts; in hwpstate_settings()
302 sets->power = set.power; in hwpstate_settings()
303 sets->lat = set.lat; in hwpstate_settings()
304 sets->dev = dev; in hwpstate_settings()
/freebsd-13-stable/sys/powerpc/cpufreq/
HDdfs.c47 static int dfs_settings(device_t dev, struct cf_setting *sets, int *count);
140 dfs_settings(device_t dev, struct cf_setting *sets, int *count) in dfs_settings() argument
147 if (sets == NULL || count == NULL) in dfs_settings()
153 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * states); in dfs_settings()
155 sets[0].freq = 10000; sets[0].dev = dev; in dfs_settings()
156 sets[1].freq = 5000; sets[1].dev = dev; in dfs_settings()
158 sets[2].freq = 2500; in dfs_settings()
159 sets[2].dev = dev; in dfs_settings()
HDpmufreq.c55 static int pmufreq_settings(device_t dev, struct cf_setting *sets, int *count);
149 pmufreq_settings(device_t dev, struct cf_setting *sets, int *count) in pmufreq_settings() argument
154 if (sets == NULL || count == NULL) in pmufreq_settings()
160 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * 2); in pmufreq_settings()
162 sets[0].freq = sc->maxfreq; sets[0].dev = dev; in pmufreq_settings()
163 sets[1].freq = sc->minfreq; sets[1].dev = dev; in pmufreq_settings()
165 sets[0].lat = INT_MAX; in pmufreq_settings()
166 sets[1].lat = INT_MAX; in pmufreq_settings()
HDpcr.c50 static int pcr_settings(device_t dev, struct cf_setting *sets, int *count);
236 pcr_settings(device_t dev, struct cf_setting *sets, int *count) in pcr_settings() argument
241 if (sets == NULL || count == NULL) in pcr_settings()
247 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->nmodes); in pcr_settings()
249 sets[0].freq = 10000; sets[0].dev = dev; in pcr_settings()
250 sets[1].freq = 5000; sets[1].dev = dev; in pcr_settings()
252 sets[2].freq = 2500; in pcr_settings()
253 sets[2].dev = dev; in pcr_settings()
HDpmcr.c87 static int pmcr_settings(device_t dev, struct cf_setting *sets, int *count);
157 pmcr_settings(device_t dev, struct cf_setting *sets, int *count) in pmcr_settings() argument
163 if (sets == NULL || count == NULL) in pmcr_settings()
169 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * npstates); in pmcr_settings()
172 sets[i].freq = pstate_freqs[i]; in pmcr_settings()
173 sets[i].spec[0] = pstate_ids[i]; in pmcr_settings()
174 sets[i].spec[1] = i; in pmcr_settings()
175 sets[i].dev = dev; in pmcr_settings()
HDmpc85xx_jog.c73 static int mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count);
214 mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count) in mpc85xx_jog_settings() argument
221 if (sets == NULL || count == NULL) in mpc85xx_jog_settings()
228 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->high); in mpc85xx_jog_settings()
231 sets[sc->high - i].freq = sysclk * i / MHZ; in mpc85xx_jog_settings()
232 sets[sc->high - i].dev = dev; in mpc85xx_jog_settings()
233 sets[sc->high - i].spec[0] = i; in mpc85xx_jog_settings()
/freebsd-13-stable/sys/contrib/device-tree/src/arm64/marvell/
HDarmada-ap806-quad.dtsi27 i-cache-sets = <256>;
30 d-cache-sets = <256>;
42 i-cache-sets = <256>;
45 d-cache-sets = <256>;
57 i-cache-sets = <256>;
60 d-cache-sets = <256>;
72 i-cache-sets = <256>;
75 d-cache-sets = <256>;
83 cache-sets = <512>;
90 cache-sets = <512>;
HDarmada-ap807-quad.dtsi27 i-cache-sets = <256>;
30 d-cache-sets = <256>;
42 i-cache-sets = <256>;
45 d-cache-sets = <256>;
57 i-cache-sets = <256>;
60 d-cache-sets = <256>;
72 i-cache-sets = <256>;
75 d-cache-sets = <256>;
83 cache-sets = <512>;
90 cache-sets = <512>;
HDarmada-ap806-dual.dtsi27 i-cache-sets = <256>;
30 d-cache-sets = <256>;
42 i-cache-sets = <256>;
45 d-cache-sets = <256>;
53 cache-sets = <512>;
/freebsd-13-stable/sys/contrib/device-tree/src/arm64/ti/
HDk3-am654.dtsi43 i-cache-sets = <256>;
46 d-cache-sets = <128>;
57 i-cache-sets = <256>;
60 d-cache-sets = <128>;
71 i-cache-sets = <256>;
74 d-cache-sets = <128>;
85 i-cache-sets = <256>;
88 d-cache-sets = <128>;
98 cache-sets = <512>;
107 cache-sets = <512>;
/freebsd-13-stable/sys/contrib/device-tree/src/riscv/sifive/
HDfu540-c000.dtsi29 i-cache-sets = <128>;
43 d-cache-sets = <64>;
45 d-tlb-sets = <1>;
49 i-cache-sets = <64>;
51 i-tlb-sets = <1>;
67 d-cache-sets = <64>;
69 d-tlb-sets = <1>;
73 i-cache-sets = <64>;
75 i-tlb-sets = <1>;
91 d-cache-sets = <64>;
[all …]
/freebsd-13-stable/sys/contrib/device-tree/src/arm64/arm/
HDjuno-r1.dts94 i-cache-sets = <256>;
97 d-cache-sets = <256>;
111 i-cache-sets = <256>;
114 d-cache-sets = <256>;
128 i-cache-sets = <256>;
131 d-cache-sets = <128>;
145 i-cache-sets = <256>;
148 d-cache-sets = <128>;
162 i-cache-sets = <256>;
165 d-cache-sets = <128>;
[all …]
HDjuno.dts93 i-cache-sets = <256>;
96 d-cache-sets = <256>;
111 i-cache-sets = <256>;
114 d-cache-sets = <256>;
129 i-cache-sets = <256>;
132 d-cache-sets = <128>;
147 i-cache-sets = <256>;
150 d-cache-sets = <128>;
165 i-cache-sets = <256>;
168 d-cache-sets = <128>;
[all …]
HDjuno-r2.dts94 i-cache-sets = <256>;
97 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
130 i-cache-sets = <256>;
133 d-cache-sets = <128>;
148 i-cache-sets = <256>;
151 d-cache-sets = <128>;
166 i-cache-sets = <256>;
169 d-cache-sets = <128>;
[all …]
/freebsd-13-stable/lib/libc/regex/
HDregfree.c74 if (g->sets != NULL) { in regfree()
76 free(g->sets[i].ranges); in regfree()
77 free(g->sets[i].wides); in regfree()
78 free(g->sets[i].types); in regfree()
80 free((char *)g->sets); in regfree()
/freebsd-13-stable/sys/kern/
HDkern_cpu.c84 struct cf_setting sets[MAX_SETTINGS]; member
111 struct cf_setting *sets, int count);
579 struct cf_setting *sets; in cpufreq_add_levels() local
604 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); in cpufreq_add_levels()
605 if (sets == NULL) in cpufreq_add_levels()
609 error = CPUFREQ_DRV_SETTINGS(dev, sets, &set_count); in cpufreq_add_levels()
616 error = cpufreq_insert_abs(sc, sets, set_count); in cpufreq_add_levels()
625 bcopy(sets, set_arr->sets, set_count * sizeof(*sets)); in cpufreq_add_levels()
634 free(sets, M_TEMP); in cpufreq_add_levels()
737 cpufreq_insert_abs(struct cpufreq_softc *sc, struct cf_setting *sets, in cpufreq_insert_abs() argument
[all …]
/freebsd-13-stable/sys/contrib/device-tree/src/arm64/freescale/
HDfsl-lx2160a.dtsi36 d-cache-sets = <128>;
39 i-cache-sets = <192>;
53 d-cache-sets = <128>;
56 i-cache-sets = <192>;
70 d-cache-sets = <128>;
73 i-cache-sets = <192>;
87 d-cache-sets = <128>;
90 i-cache-sets = <192>;
104 d-cache-sets = <128>;
107 i-cache-sets = <192>;
[all …]
/freebsd-13-stable/crypto/openssl/doc/man3/
HDEVP_PKEY_CTX_ctrl.pod170 The EVP_PKEY_CTX_set_signature_md() macro sets the message digest type used
189 The EVP_PKEY_CTX_set_rsa_padding() macro sets the RSA padding mode for B<ctx>.
208 The EVP_PKEY_CTX_set_rsa_pss_saltlen() macro sets the RSA PSS salt length to
210 values are supported: B<RSA_PSS_SALTLEN_DIGEST> sets the salt length to the
211 digest length, B<RSA_PSS_SALTLEN_MAX> sets the salt length to the maximum
220 The EVP_PKEY_CTX_set_rsa_keygen_bits() macro sets the RSA key length for
223 The EVP_PKEY_CTX_set_rsa_keygen_pubexp() macro sets the public exponent value
228 The EVP_PKEY_CTX_set_rsa_keygen_primes() macro sets the number of primes for
231 The EVP_PKEY_CTX_set_rsa_mgf1_md() macro sets the MGF1 digest for RSA padding
240 The EVP_PKEY_CTX_set_rsa_oaep_md() macro sets the message digest type used
[all …]
/freebsd-13-stable/tools/tools/ifinfo/
HDrfc1650.c86 #define vendor(name, sets) { name, sets, (sizeof sets)/(sizeof sets[0]) } argument
/freebsd-13-stable/sys/arm64/nvidia/tegra210/
HDtegra210_cpufreq.c249 tegra210_cpufreq_settings(device_t dev, struct cf_setting *sets, int *count) in tegra210_cpufreq_settings() argument
254 if (sets == NULL || count == NULL) in tegra210_cpufreq_settings()
258 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * (*count)); in tegra210_cpufreq_settings()
264 sets[i].freq = sc->speed_points[j].freq / 1000000; in tegra210_cpufreq_settings()
265 sets[i].volts = sc->speed_points[j].uvolt / 1000; in tegra210_cpufreq_settings()
266 sets[i].lat = sc->latency; in tegra210_cpufreq_settings()
267 sets[i].dev = dev; in tegra210_cpufreq_settings()

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