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/freebsd-13-stable/sys/dev/isci/scil/
HDscic_sds_phy_registers.h78 #define scu_transport_layer_read(phy, reg) \ argument
80 scic_sds_phy_get_controller(phy), \
81 (phy)->transport_layer_registers->reg \
88 #define scu_transport_layer_write(phy, reg, value) \ argument
90 scic_sds_phy_get_controller(phy), \
91 (phy)->transport_layer_registers->reg, \
102 #define SCU_TLCR_READ(phy) \ argument
103 scu_transport_layer_read(phy, control)
108 #define SCU_TLCR_WRITE(phy, value) \ argument
109 scu_transport_layer_write(phy, control, value)
[all …]
HDscic_sds_phy.h345 #define scic_sds_phy_get_index(phy) \ argument
346 ((phy)->phy_index)
351 #define scic_sds_phy_get_controller(phy) \ argument
352 (scic_sds_port_get_controller((phy)->owning_port))
357 #define scic_sds_phy_get_base_state_machine(phy) \ argument
358 (&(phy)->parent.state_machine)
364 #define scic_sds_phy_get_starting_substate_machine(phy) \ argument
365 (&(phy)->starting_substate_machine)
370 #define scic_sds_phy_set_state_handlers(phy, handlers) \ argument
371 ((phy)->state_handlers = (handlers))
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/freebsd-13-stable/sys/net80211/
HDieee80211_phy.c79 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },/* 1 Mb */
80 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },/* 2 Mb */
81 [2] = { .phy = CCK, 5500, 0x04, B(11), 1 },/* 5.5 Mb */
82 [3] = { .phy = CCK, 11000, 0x04, B(22), 1 },/* 11 Mb */
83 [4] = { .phy = PBCC, 22000, 0x04, 44, 3 } /* 22 Mb */
92 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },
93 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },
94 [2] = { .phy = CCK, 5500, 0x04, B(11), 2 },
95 [3] = { .phy = CCK, 11000, 0x04, B(22), 3 },
96 [4] = { .phy = OFDM, 6000, 0x00, 12, 4 },
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/freebsd-13-stable/sys/dev/cxgb/common/
HDcxgb_ael1002.c97 static int ael2xxx_get_module_type(struct cphy *phy, int delay_ms);
99 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) in set_phy_regs() argument
105 err = mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs()
108 err = t3_mdio_change_bits(phy, rv->mmd_addr, in set_phy_regs()
115 static void ael100x_txon(struct cphy *phy) in ael100x_txon() argument
117 int tx_on_gpio = phy->addr == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL; in ael100x_txon()
120 t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio); in ael100x_txon()
127 static int ael_i2c_rd(struct cphy *phy, int dev_addr, int word_addr) in ael_i2c_rd() argument
132 err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL, in ael_i2c_rd()
139 err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat); in ael_i2c_rd()
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HDcxgb_aq100x.c66 #define AQ_WRITE_REGS(phy, regs) do { \ argument
69 (void) mdio_write(phy, regs[i].mmd, regs[i].reg, regs[i].val); \
72 #define AQ_READ_REGS(phy, regs) do { \ argument
75 (void) mdio_read(phy, regs[i].mmd, regs[i].reg, &v); \
83 aq100x_temperature(struct cphy *phy) in aq100x_temperature() argument
87 if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL2, &v) || in aq100x_temperature()
91 if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL1, &v)) in aq100x_temperature()
98 aq100x_set_defaults(struct cphy *phy) in aq100x_set_defaults() argument
100 return mdio_write(phy, MDIO_DEV_VEND1, AQ_THERMAL_THR, 0x6c00); in aq100x_set_defaults()
104 aq100x_reset(struct cphy *phy, int wait) in aq100x_reset() argument
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/freebsd-13-stable/sys/dev/e1000/
HDe1000_phy.c72 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_ops_generic() local
76 phy->ops.init_params = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
77 phy->ops.acquire = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
78 phy->ops.check_polarity = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
79 phy->ops.check_reset_block = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
80 phy->ops.commit = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
81 phy->ops.force_speed_duplex = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
82 phy->ops.get_cfg_done = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
83 phy->ops.get_cable_length = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
84 phy->ops.get_info = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
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HDe1000_82541.c87 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82541() local
92 phy->addr = 1; in e1000_init_phy_params_82541()
93 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82541()
94 phy->reset_delay_us = 10000; in e1000_init_phy_params_82541()
95 phy->type = e1000_phy_igp; in e1000_init_phy_params_82541()
98 phy->ops.check_polarity = e1000_check_polarity_igp; in e1000_init_phy_params_82541()
99 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; in e1000_init_phy_params_82541()
100 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541; in e1000_init_phy_params_82541()
101 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; in e1000_init_phy_params_82541()
102 phy->ops.get_info = e1000_get_phy_info_igp; in e1000_init_phy_params_82541()
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HDe1000_82575.c160 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82575() local
166 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic; in e1000_init_phy_params_82575()
167 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic; in e1000_init_phy_params_82575()
169 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82575()
170 phy->type = e1000_phy_none; in e1000_init_phy_params_82575()
174 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_82575()
175 phy->ops.power_down = e1000_power_down_phy_copper_base; in e1000_init_phy_params_82575()
177 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82575()
178 phy->reset_delay_us = 100; in e1000_init_phy_params_82575()
180 phy->ops.acquire = e1000_acquire_phy_base; in e1000_init_phy_params_82575()
[all …]
/freebsd-13-stable/sys/dev/igc/
HDigc_phy.c20 struct igc_phy_info *phy = &hw->phy; in igc_init_phy_ops_generic() local
24 phy->ops.init_params = igc_null_ops_generic; in igc_init_phy_ops_generic()
25 phy->ops.acquire = igc_null_ops_generic; in igc_init_phy_ops_generic()
26 phy->ops.check_reset_block = igc_null_ops_generic; in igc_init_phy_ops_generic()
27 phy->ops.force_speed_duplex = igc_null_ops_generic; in igc_init_phy_ops_generic()
28 phy->ops.get_info = igc_null_ops_generic; in igc_init_phy_ops_generic()
29 phy->ops.set_page = igc_null_set_page; in igc_init_phy_ops_generic()
30 phy->ops.read_reg = igc_null_read_reg; in igc_init_phy_ops_generic()
31 phy->ops.read_reg_locked = igc_null_read_reg; in igc_init_phy_ops_generic()
32 phy->ops.read_reg_page = igc_null_read_reg; in igc_init_phy_ops_generic()
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/freebsd-13-stable/sys/dev/bxe/
HDbxe_elink.c757 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
948 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
2250 params->phy[phy_index].mdio_ctrl); in elink_set_mdio_emac_per_phy()
2543 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) { in elink_xmac_enable()
2574 (params->phy[ELINK_INT_PHY].supported & in elink_xmac_enable()
3413 struct elink_phy *phy, in elink_cl22_write() argument
3420 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in elink_cl22_write()
3421 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in elink_cl22_write()
3425 tmp = ((phy->addr << 21) | (reg << 16) | val | in elink_cl22_write()
3428 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in elink_cl22_write()
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/freebsd-13-stable/sys/dev/ixgbe/
HDixgbe_phy.c112 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_read_i2c_combined_generic_int()
189 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_write_i2c_combined_generic_int()
249 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_generic() local
254 phy->ops.identify = ixgbe_identify_phy_generic; in ixgbe_init_phy_ops_generic()
255 phy->ops.reset = ixgbe_reset_phy_generic; in ixgbe_init_phy_ops_generic()
256 phy->ops.read_reg = ixgbe_read_phy_reg_generic; in ixgbe_init_phy_ops_generic()
257 phy->ops.write_reg = ixgbe_write_phy_reg_generic; in ixgbe_init_phy_ops_generic()
258 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; in ixgbe_init_phy_ops_generic()
259 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; in ixgbe_init_phy_ops_generic()
260 phy->ops.setup_link = ixgbe_setup_phy_link_generic; in ixgbe_init_phy_ops_generic()
[all …]
/freebsd-13-stable/sys/dev/etherswitch/arswitch/
HDarswitch_reg.c65 arswitch_split_setpage(device_t dev, uint32_t addr, uint16_t *phy, in arswitch_split_setpage() argument
72 *phy = (addr >> 6) & 0x7; in arswitch_split_setpage()
90 uint16_t phy, reg; in arswitch_readreg16() local
92 arswitch_split_setpage(dev, addr, &phy, &reg); in arswitch_readreg16()
93 return (MDIO_READREG(device_get_parent(dev), 0x10 | phy, reg)); in arswitch_readreg16()
102 uint16_t phy, reg; in arswitch_writereg16() local
104 arswitch_split_setpage(dev, addr, &phy, &reg); in arswitch_writereg16()
105 return (MDIO_WRITEREG(device_get_parent(dev), 0x10 | phy, reg, data)); in arswitch_writereg16()
118 arswitch_writedbg(device_t dev, int phy, uint16_t dbg_addr, in arswitch_writedbg() argument
121 (void) MDIO_WRITEREG(device_get_parent(dev), phy, in arswitch_writedbg()
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/freebsd-13-stable/tools/tools/net80211/wlantxtime/
HDwlantxtime.c51 uint8_t phy; /* CCK/OFDM/TURBO */ member
102 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },/* 1 Mb */
103 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },/* 2 Mb */
104 [2] = { .phy = CCK, 5500, 0x04, B(11), 1 },/* 5.5 Mb */
105 [3] = { .phy = CCK, 11000, 0x04, B(22), 1 },/* 11 Mb */
106 [4] = { .phy = PBCC, 22000, 0x04, 44, 3 } /* 22 Mb */
115 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },
116 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },
117 [2] = { .phy = CCK, 5500, 0x04, B(11), 2 },
118 [3] = { .phy = CCK, 11000, 0x04, B(22), 3 },
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/freebsd-13-stable/sys/dev/bwi/
HDbwiphy.c156 struct bwi_phy *phy = &mac->mac_phy; in bwi_phy_attach() local
180 phy->phy_init = bwi_phy_init_11a; in bwi_phy_attach()
181 phy->phy_mode = IEEE80211_MODE_11A; in bwi_phy_attach()
182 phy->phy_tbl_ctrl = BWI_PHYR_TBL_CTRL_11A; in bwi_phy_attach()
183 phy->phy_tbl_data_lo = BWI_PHYR_TBL_DATA_LO_11A; in bwi_phy_attach()
184 phy->phy_tbl_data_hi = BWI_PHYR_TBL_DATA_HI_11A; in bwi_phy_attach()
189 phy->phy_init = bwi_sup_bphy[i].init; in bwi_phy_attach()
198 phy->phy_mode = IEEE80211_MODE_11B; in bwi_phy_attach()
206 phy->phy_init = bwi_phy_init_11g; in bwi_phy_attach()
207 phy->phy_mode = IEEE80211_MODE_11G; in bwi_phy_attach()
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/phy/
HDsamsung-phy.txt6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
20 For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
26 "samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy"
35 - "samsung,exynos5250-dp-video-phy"
36 - "samsung,exynos5420-dp-video-phy"
39 - #phy-cells : from the generic PHY bindings, must be 0;
46 - "samsung,exynos3250-usb2-phy"
[all …]
HDbrcm-sata-phy.txt5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
16 - reg-names: should be "phy" and "phy-ctrl"
17 The "phy-ctrl" registers are only required for
[all …]
Dbrcm,stingray-usb-phy.txt5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
8 - #phy-cells:
9 - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
11 - Must be 0 for brcm,sr-usb-hs-phy.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
16 usbphy0: usb-phy@0 {
17 compatible = "brcm,sr-usb-combo-phy";
19 #phy-cells = <1>;
22 usbphy1: usb-phy@10000 {
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/freebsd-13-stable/sys/contrib/device-tree/src/powerpc/fsl/
HDt4240qds.dts151 phyrgmii1: ethernet-phy@1 {
155 phyrgmii2: ethernet-phy@2 {
166 phy1: ethernet-phy@0 {
170 phy2: ethernet-phy@1 {
174 phy3: ethernet-phy@2 {
178 phy4: ethernet-phy@3 {
182 sgmiiphy11: ethernet-phy@1c {
186 sgmiiphy12: ethernet-phy@1d {
190 sgmiiphy13: ethernet-phy@1e {
194 sgmiiphy14: ethernet-phy@1f {
[all …]
HDt2081qds.dts58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&rgmii_phy1>;
69 phy-connection-type = "rgmii";
73 phy-handle = <&rgmii_phy2>;
74 phy-connection-type = "rgmii";
78 phy-handle = <&phy_sgmii_s3_1c>;
79 phy-connection-type = "sgmii";
[all …]
HDt2080qds.dts66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
71 phy-handle = <&phy_sgmii_s3_1f>;
72 phy-connection-type = "xgmii";
76 phy-handle = <&rgmii_phy1>;
77 phy-connection-type = "rgmii";
81 phy-handle = <&rgmii_phy2>;
82 phy-connection-type = "rgmii";
86 phy-handle = <&phy_sgmii_s2_1e>;
87 phy-connection-type = "sgmii";
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/freebsd-13-stable/sys/contrib/device-tree/src/arm64/broadcom/stingray/
HDstingray-sata.dtsi51 phy-names = "sata-phy";
56 compatible = "brcm,iproc-sr-sata-phy";
58 reg-names = "phy";
63 sata0_phy0: sata-phy@0 {
65 #phy-cells = <0>;
81 phy-names = "sata-phy";
86 compatible = "brcm,iproc-sr-sata-phy";
88 reg-names = "phy";
93 sata1_phy0: sata-phy@0 {
95 #phy-cells = <0>;
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/freebsd-13-stable/sys/dev/bwn/
HDif_bwn_phy_g.c152 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_g_attach() local
153 struct bwn_phy_g *pg = &phy->phy_g; in bwn_phy_g_attach()
239 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_g_init_pre() local
240 struct bwn_phy_g *pg = &phy->phy_g; in bwn_phy_g_init_pre()
272 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_g_prepare_hw() local
273 struct bwn_phy_g *pg = &phy->phy_g; in bwn_phy_g_prepare_hw()
293 KASSERT(phy->type == BWN_PHYTYPE_G, ("%s fail", __func__)); in bwn_phy_g_prepare_hw()
295 if (phy->rf_ver == 0x2050 && phy->rf_rev < 6) in bwn_phy_g_prepare_hw()
314 if (phy->type == BWN_PHYTYPE_A) { in bwn_phy_g_prepare_hw()
319 switch (phy->rf_ver) { in bwn_phy_g_prepare_hw()
[all …]
/freebsd-13-stable/sys/contrib/device-tree/src/mips/mscc/
HDocelot_pcb120.dts8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
45 phy7: ethernet-phy@0 {
51 phy6: ethernet-phy@1 {
57 phy5: ethernet-phy@2 {
63 phy4: ethernet-phy@3 {
72 phy-handle = <&phy0>;
76 phy-handle = <&phy1>;
80 phy-handle = <&phy2>;
84 phy-handle = <&phy3>;
88 phy-handle = <&phy7>;
[all …]
/freebsd-13-stable/sys/dev/axgbe/
HDxgbe-phy-v2.c739 XGBE_ZERO_SUP(&pdata->phy); in xgbe_phy_sfp_phy_settings()
742 pdata->phy.speed = SPEED_UNKNOWN; in xgbe_phy_sfp_phy_settings()
743 pdata->phy.duplex = DUPLEX_UNKNOWN; in xgbe_phy_sfp_phy_settings()
744 pdata->phy.autoneg = AUTONEG_ENABLE; in xgbe_phy_sfp_phy_settings()
745 pdata->phy.pause_autoneg = AUTONEG_ENABLE; in xgbe_phy_sfp_phy_settings()
747 XGBE_SET_SUP(&pdata->phy, Autoneg); in xgbe_phy_sfp_phy_settings()
748 XGBE_SET_SUP(&pdata->phy, Pause); in xgbe_phy_sfp_phy_settings()
749 XGBE_SET_SUP(&pdata->phy, Asym_Pause); in xgbe_phy_sfp_phy_settings()
750 XGBE_SET_SUP(&pdata->phy, TP); in xgbe_phy_sfp_phy_settings()
751 XGBE_SET_SUP(&pdata->phy, FIBRE); in xgbe_phy_sfp_phy_settings()
[all …]
/freebsd-13-stable/sys/dev/extres/phy/
HDphy.c297 struct phy *phy; in phy_create() local
301 phy = malloc(sizeof(struct phy), M_PHY, M_WAITOK | M_ZERO); in phy_create()
302 phy->cdev = cdev; in phy_create()
303 phy->phynode = phynode; in phy_create()
304 phy->enable_cnt = 0; in phy_create()
308 TAILQ_INSERT_TAIL(&phynode->consumers_list, phy, link); in phy_create()
311 return (phy); in phy_create()
315 phy_enable(phy_t phy) in phy_enable() argument
320 phynode = phy->phynode; in phy_enable()
327 phy->enable_cnt++; in phy_enable()
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