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Searched refs:f16 (Results 1 – 25 of 160) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVInstrInfoZfh.td42 f16, FPR16, FPR32, ?, FPR16>;
44 f16, FPR16, FPR32, ?, FPR16>;
52 f16, FPR16INX, FPR32INX, ?, FPR16INX>;
55 f16, FPR16INX, FPR32INX, ?, FPR16INX>;
267 def : Pat<(f16 (any_fsqrt FPR16:$rs1)), (FSQRT_H FPR16:$rs1, FRM_DYN)>;
269 def : Pat<(f16 (fneg FPR16:$rs1)), (FSGNJN_H $rs1, $rs1)>;
270 def : Pat<(f16 (fabs FPR16:$rs1)), (FSGNJX_H $rs1, $rs1)>;
272 def : Pat<(riscv_fclass (f16 FPR16:$rs1)), (FCLASS_H $rs1)>;
274 def : PatFprFpr<fcopysign, FSGNJ_H, FPR16, f16>;
275 def : Pat<(f16 (fcopysign FPR16:$rs1, (f16 (fneg FPR16:$rs2)))), (FSGNJN_H $rs1, $rs2)>;
[all …]
HDRISCVInstrInfoZfa.td242 def: PatFprFpr<fminimum, FMINM_H, FPR16, f16>;
243 def: PatFprFpr<fmaximum, FMAXM_H, FPR16, f16>;
247 def: Pat<(f16 (any_frint FPR16:$rs1)), (FROUNDNX_H FPR16:$rs1, FRM_DYN)>;
250 def: Pat<(f16 (any_fnearbyint FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_DYN)>;
252 def: Pat<(f16 (any_fround FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RMM)>;
253 def: Pat<(f16 (any_froundeven FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RNE)>;
254 def: Pat<(f16 (any_ffloor FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RDN)>;
255 def: Pat<(f16 (any_fceil FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RUP)>;
256 def: Pat<(f16 (any_ftrunc FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RTZ)>;
258 def: PatSetCC<FPR16, strict_fsetcc, SETLT, FLTQ_H, f16>;
[all …]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMInstrVFP.td45 def vfp_f16imm : Operand<f16>,
46 PatLeaf<(f16 fpimm), [{
171 [(set HPR:$Sd, (f16 (alignedload16 addrmode5fp16:$addr)))]>,
206 [(alignedstore16 (f16 HPR:$Sd), addrmode5fp16:$addr)]>,
446 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm",
447 [(set (f16 HPR:$Sd), (fadd (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
471 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm",
472 [(set (f16 HPR:$Sd), (fsub (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
492 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm",
493 [(set (f16 HPR:$Sd), (fdiv (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
[all …]
/freebsd-13-stable/crypto/openssl/crypto/aes/asm/
HDaest4-sparcv9.pl134 ldd [$key + 32], %f16
145 aes_eround01 %f16, %f4, %f2, %f0
147 ldd [$key + 16], %f16
155 aes_eround01_l %f16, %f4, %f2, %f0
212 ldd [$key + 32], %f16
223 aes_dround01 %f16, %f4, %f2, %f0
225 ldd [$key + 16], %f16
233 aes_dround01_l %f16, %f4, %f2, %f0
606 aes_eround01 %f16, %f0, %f2, %f4
608 ldd [$key + 208], %f16
[all …]
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDValueTypes.td75 def f16 : VTFP<16, 11>; // 16-bit floating point value
161 def v1f16 : VTVec<1, f16, 88>; // 1 x f16 vector value
162 def v2f16 : VTVec<2, f16, 89>; // 2 x f16 vector value
163 def v3f16 : VTVec<3, f16, 90>; // 3 x f16 vector value
164 def v4f16 : VTVec<4, f16, 91>; // 4 x f16 vector value
165 def v8f16 : VTVec<8, f16, 92>; // 8 x f16 vector value
166 def v16f16 : VTVec<16, f16, 93>; // 16 x f16 vector value
167 def v32f16 : VTVec<32, f16, 94>; // 32 x f16 vector value
168 def v64f16 : VTVec<64, f16, 95>; // 64 x f16 vector value
169 def v128f16 : VTVec<128, f16, 96>; // 128 x f16 vector value
[all …]
/freebsd-13-stable/crypto/openssl/crypto/camellia/asm/
HDcmllt4-sparcv9.pl101 ldd [$key + 32], %f16
118 camellia_f %f16, %f2, %f0, %f2
119 ldd [$key + 16], %f16
136 camellia_f %f16, %f2, %f0, %f2
196 ldd [$key - 24], %f16
213 camellia_f %f16, %f2, %f0, %f2
214 ldd [$key - 24], %f16
231 camellia_f %f16, %f2, %f0, %f2
347 ldd [%o4 + 0], %f16
352 camellia_f %f16, %f2, %f0, %f2
[all …]
/freebsd-13-stable/crypto/openssl/crypto/des/asm/
HDdest4-sparcv9.pl78 des_kexpand %f14, 1, %f16
80 des_kexpand %f16, 3, %f20
82 des_kexpand %f16, 2, %f18
83 std %f16, [$out + 0x40]
133 ldd [$key + 0x30], %f16
164 des_round %f16, %f18, %f0, %f0
234 ldd [$key + 0x48], %f16
264 des_round %f16, %f18, %f0, %f0
342 ldd [$key + 0x30], %f16
373 des_round %f16, %f18, %f0, %f0
[all …]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPUCallingConv.td25 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
32 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
39 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
46 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
71 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
81 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
114 CCIfType<[f32, f16, v2f16, bf16, v2bf16] , CCAssignToReg<[
193 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
197 CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg<[
202 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
[all …]
HDVOP3PInstructions.td24 // Their operands are only sort of f16 operands. Depending on
26 // values are really f16 converted to f32, so we treat these as f16
147 // At least one of the operands needs to be an fpextend of an f16
151 (f32 (fma_like (f32 (VOP3PMadMixModsExt f16:$src0, i32:$src0_mods)),
152 (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_mods)),
153 (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_mods)))),
157 (f32 (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_mods)),
158 (f32 (VOP3PMadMixModsExt f16:$src1, i32:$src1_mods)),
163 (f32 (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_mods)),
165 (f32 (VOP3PMadMixModsExt f16:$src2, i32:$src2_mods)))),
[all …]
HDSIInstructions.td237 [(set f16:$vdst, (SIfptrunc_round_upward f32:$src0))]>;
241 [(set f16:$vdst, (SIfptrunc_round_downward f32:$src0))]>;
1135 (f64 (any_fpextend f16:$src)),
1146 (i32 (fp_to_sint f16:$src)),
1151 (i32 (fp_to_uint f16:$src)),
1156 (f16 (sint_to_fp i32:$src)),
1161 (f16 (uint_to_fp i32:$src)),
1222 def : FMADPat <f16, V_MAC_F16_e64>;
1248 def : VOPSelectPat <f16>;
1505 def : BitConvert <i16, f16, VGPR_32>;
[all …]
HDVINTERPInstructions.td116 VINTERP_Pseudo <"v_interp_p2_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
123 VINTERP_Pseudo <"v_interp_p2_rtz_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
174 V_INTERP_P2_F16_F32_inreg, f16,
180 V_INTERP_P2_RTZ_F16_F32_inreg, f16,
HDAMDGPUCombine.td39 (match (G_FSQRT f16:$sqrt, $x, (MIFlags FmContract)),
40 (G_FDIV f16:$dst, $y, $sqrt, (MIFlags FmContract)):$root,
129 // For gfx8, expand f16-fmed3-as-f32 into a min/max f16 sequence. This
HDSIInstrInfo.td850 def fp16_zeros_high_16bits : PatLeaf<(f16 VGPR_32:$src), [{
1008 def SDWASrc_f16 : SDWASrc<f16>;
1552 !eq(VT, f16) : !if(IsTrue16,
1595 !eq(VT, f16) : !if(IsTrue16, VSrcT_f16, VSrc_f16),
1617 !eq(VT, f16) : VCSrc_f16,
1628 bit ret = !or(!eq(SrcVT.Value, f16.Value),
1663 Operand ret = !cond(!eq(VT, f16) : FP16InputMods,
1678 !if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
1688 !if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
1695 Operand ret = !if(!eq(VT.Value, f16.Value), FP16SDWAInputMods,
[all …]
HDVOPCInstructions.td395 defm VOPC_I1_F16_F16 : VOPC_Profile_t16<[Write32Bit], f16>;
402 defm VOPC_F16_F16 : VOPC_NoSdst_Profile_t16<[Write32Bit], f16>;
795 def NAME : VOPC_Class_Profile<sched, f16>;
796 def _t16 : VOPC_Class_Profile<sched, f16, i16> {
822 def NAME : VOPC_Class_NoSdst_Profile<sched, f16>;
823 def _t16 : VOPC_Class_NoSdst_Profile<sched, f16, i16> {
1123 defm : FCMP_Pattern <COND_O, V_CMP_O_F16_t16_e64, f16>;
1124 defm : FCMP_Pattern <COND_UO, V_CMP_U_F16_t16_e64, f16>;
1125 defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_t16_e64, f16>;
1126 defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_t16_e64, f16>;
[all …]
/freebsd-13-stable/crypto/openssl/crypto/sha/asm/
HDsha1-sparcv9.pl227 ldd [%o1 + 0x20], %f16
256 ldd [%o1 + 0x18], %f16
268 faligndata %f14, %f16, %f12
269 faligndata %f16, %f18, %f14
270 faligndata %f18, %f20, %f16
HDsha512-sparcv9.pl501 ldd [%o1 + 0x00], %f16
565 faligndata %f18, %f20, %f16
607 ldd [%o1 + 0x20], %f16
639 ldd [%o1 + 0x18], %f16
651 faligndata %f14, %f16, %f12
652 faligndata %f16, %f18, %f14
653 faligndata %f18, %f20, %f16
/freebsd-13-stable/crypto/openssl/crypto/md5/asm/
HDmd5-sparcv9.pl242 ldd [%o1 + 0x20], %f16
272 ldd [%o1 + 0x18], %f16
284 faligndata %f14, %f16, %f12
285 faligndata %f16, %f18, %f14
286 faligndata %f18, %f20, %f16
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
HDNVPTXInstrInfo.td16 def f16imm : Operand<f16>;
193 !eq(name, "f16"): Int16Regs,
317 !strconcat(OpcStr, ".ftz.f16 \t$dst, $a, $b;"),
318 [(set Int16Regs:$dst, (OpNode (f16 Int16Regs:$a), (f16 Int16Regs:$b)))]>,
323 !strconcat(OpcStr, ".f16 \t$dst, $a, $b;"),
324 [(set Int16Regs:$dst, (OpNode (f16 Int16Regs:$a), (f16 Int16Regs:$b)))]>,
416 !strconcat(OpcStr, ".ftz.f16 \t$dst, $a, $b;"),
417 [(set Int16Regs:$dst, (OpNode (f16 Int16Regs:$a), (f16 Int16Regs:$b)))]>,
422 !strconcat(OpcStr, ".f16 \t$dst, $a, $b;"),
423 [(set Int16Regs:$dst, (OpNode (f16 Int16Regs:$a), (f16 Int16Regs:$b)))]>,
[all …]
/freebsd-13-stable/lib/libc/powerpc/gen/
HD_setjmp.S61 stfd %f16,112+2*8(%r3)
88 lfd %f16,112+2*8(%r3)
HDsetjmp.S71 stfd %f16,112+2*8(%r6)
99 lfd %f16,112+2*8(%r3)
HDsigsetjmp.S76 stfd %f16,112+2*8(%r6)
103 lfd %f16,112+2*8(%r3)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDTargetLoweringBase.cpp121 if (OpVT == MVT::f16) { in getFPEXT()
156 if (RetVT == MVT::f16) { in getFPROUND()
199 if (OpVT == MVT::f16) { in getFPTOSINT()
248 if (OpVT == MVT::f16) { in getFPTOUINT()
298 if (RetVT == MVT::f16) in getSINTTOFP()
311 if (RetVT == MVT::f16) in getSINTTOFP()
324 if (RetVT == MVT::f16) in getSINTTOFP()
344 if (RetVT == MVT::f16) in getUINTTOFP()
357 if (RetVT == MVT::f16) in getUINTTOFP()
370 if (RetVT == MVT::f16) in getUINTTOFP()
[all …]
/freebsd-13-stable/usr.sbin/bsdconfig/console/
HDfont174 [ "$f8" -a "$f14" -a "$f16" ] || f_die 1 "$msg_unknown_font_selection"
178 f_eval_catch "$0" f_sysrc_set 'f_sysrc_set font8x16 "%s"' "$f16" || f_die
/freebsd-13-stable/contrib/llvm-project/compiler-rt/lib/xray/
HDxray_trampoline_mips64.S39 sdc1 $f16, 32($sp)
66 ldc1 $f16, 32($sp)
/freebsd-13-stable/lib/libc/powerpc64/gen/
HD_setjmp.S61 stfd %f16,40 + 25*8(%r3)
107 lfd %f16,40 + 25*8(%r3)

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