1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003-2008 Joseph Koshy
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/types.h>
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/pmc.h>
34 #include <sys/syscall.h>
35
36 #include <assert.h>
37 #include <ctype.h>
38 #include <errno.h>
39 #include <err.h>
40 #include <fcntl.h>
41 #include <pmc.h>
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <string.h>
45 #include <strings.h>
46 #include <sysexits.h>
47 #include <unistd.h>
48
49 #include "libpmcinternal.h"
50
51 /* Function prototypes */
52 #if defined(__amd64__) || defined(__i386__)
53 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
54 struct pmc_op_pmcallocate *_pmc_config);
55 #endif
56 #if defined(__amd64__) || defined(__i386__)
57 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
58 struct pmc_op_pmcallocate *_pmc_config);
59 #endif
60 #if defined(__arm__)
61 static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
62 struct pmc_op_pmcallocate *_pmc_config);
63 #endif
64 #if defined(__aarch64__)
65 static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
66 struct pmc_op_pmcallocate *_pmc_config);
67 #endif
68 #if defined(__mips__)
69 static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec,
70 struct pmc_op_pmcallocate *_pmc_config);
71 #endif /* __mips__ */
72 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
73 struct pmc_op_pmcallocate *_pmc_config);
74
75 #if defined(__powerpc__)
76 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec,
77 struct pmc_op_pmcallocate *_pmc_config);
78 #endif /* __powerpc__ */
79
80 #define PMC_CALL(op, params) syscall(pmc_syscall, (op), (params))
81
82 /*
83 * Event aliases provide a way for the user to ask for generic events
84 * like "cache-misses", or "instructions-retired". These aliases are
85 * mapped to the appropriate canonical event descriptions using a
86 * lookup table.
87 */
88 struct pmc_event_alias {
89 const char *pm_alias;
90 const char *pm_spec;
91 };
92
93 static const struct pmc_event_alias *pmc_mdep_event_aliases;
94
95 /*
96 * The pmc_event_descr structure maps symbolic names known to the user
97 * to integer codes used by the PMC KLD.
98 */
99 struct pmc_event_descr {
100 const char *pm_ev_name;
101 enum pmc_event pm_ev_code;
102 };
103
104 /*
105 * The pmc_class_descr structure maps class name prefixes for
106 * event names to event tables and other PMC class data.
107 */
108 struct pmc_class_descr {
109 const char *pm_evc_name;
110 size_t pm_evc_name_size;
111 enum pmc_class pm_evc_class;
112 const struct pmc_event_descr *pm_evc_event_table;
113 size_t pm_evc_event_table_size;
114 int (*pm_evc_allocate_pmc)(enum pmc_event _pe,
115 char *_ctrspec, struct pmc_op_pmcallocate *_pa);
116 };
117
118 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0]))
119 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table)
120
121 #undef __PMC_EV
122 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N },
123
124 /*
125 * PMC_CLASSDEP_TABLE(NAME, CLASS)
126 *
127 * Define a table mapping event names and aliases to HWPMC event IDs.
128 */
129 #define PMC_CLASSDEP_TABLE(N, C) \
130 static const struct pmc_event_descr N##_event_table[] = \
131 { \
132 __PMC_EV_##C() \
133 }
134
135 PMC_CLASSDEP_TABLE(iaf, IAF);
136 PMC_CLASSDEP_TABLE(k8, K8);
137 PMC_CLASSDEP_TABLE(armv7, ARMV7);
138 PMC_CLASSDEP_TABLE(armv8, ARMV8);
139 PMC_CLASSDEP_TABLE(beri, BERI);
140 PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
141 PMC_CLASSDEP_TABLE(mips74k, MIPS74K);
142 PMC_CLASSDEP_TABLE(octeon, OCTEON);
143 PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
144 PMC_CLASSDEP_TABLE(ppc970, PPC970);
145 PMC_CLASSDEP_TABLE(power8, POWER8);
146 PMC_CLASSDEP_TABLE(e500, E500);
147
148 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT];
149
150 #undef __PMC_EV_ALIAS
151 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE },
152
153 /*
154 * TODO: Factor out the __PMC_EV_ARMV7/8 list into a single separate table
155 * rather than duplicating for each core.
156 */
157
158 static const struct pmc_event_descr cortex_a8_event_table[] =
159 {
160 __PMC_EV_ALIAS_ARMV7_CORTEX_A8()
161 __PMC_EV_ARMV7()
162 };
163
164 static const struct pmc_event_descr cortex_a9_event_table[] =
165 {
166 __PMC_EV_ALIAS_ARMV7_CORTEX_A9()
167 __PMC_EV_ARMV7()
168 };
169
170 static const struct pmc_event_descr cortex_a53_event_table[] =
171 {
172 __PMC_EV_ALIAS_ARMV8_CORTEX_A53()
173 __PMC_EV_ARMV8()
174 };
175
176 static const struct pmc_event_descr cortex_a57_event_table[] =
177 {
178 __PMC_EV_ALIAS_ARMV8_CORTEX_A57()
179 __PMC_EV_ARMV8()
180 };
181
182 static const struct pmc_event_descr cortex_a76_event_table[] =
183 {
184 __PMC_EV_ALIAS_ARMV8_CORTEX_A76()
185 __PMC_EV_ARMV8()
186 };
187
188 static const struct pmc_event_descr tsc_event_table[] =
189 {
190 __PMC_EV_ALIAS_TSC()
191 };
192
193 #undef PMC_CLASS_TABLE_DESC
194 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \
195 static const struct pmc_class_descr NAME##_class_table_descr = \
196 { \
197 .pm_evc_name = #CLASS "-", \
198 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \
199 .pm_evc_class = PMC_CLASS_##CLASS , \
200 .pm_evc_event_table = EVENTS##_event_table , \
201 .pm_evc_event_table_size = \
202 PMC_EVENT_TABLE_SIZE(EVENTS), \
203 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \
204 }
205
206 #if defined(__i386__) || defined(__amd64__)
207 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
208 #endif
209 #if defined(__i386__) || defined(__amd64__)
210 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
211 #endif
212 #if defined(__arm__)
213 PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7);
214 PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7);
215 #endif
216 #if defined(__aarch64__)
217 PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64);
218 PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64);
219 PMC_CLASS_TABLE_DESC(cortex_a76, ARMV8, cortex_a76, arm64);
220 #endif
221 #if defined(__mips__)
222 PMC_CLASS_TABLE_DESC(beri, BERI, beri, mips);
223 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips);
224 PMC_CLASS_TABLE_DESC(mips74k, MIPS74K, mips74k, mips);
225 PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips);
226 #endif /* __mips__ */
227 #if defined(__powerpc__)
228 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc);
229 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc);
230 PMC_CLASS_TABLE_DESC(power8, POWER8, power8, powerpc);
231 PMC_CLASS_TABLE_DESC(e500, E500, e500, powerpc);
232 #endif
233
234 static struct pmc_class_descr soft_class_table_descr =
235 {
236 .pm_evc_name = "SOFT-",
237 .pm_evc_name_size = sizeof("SOFT-") - 1,
238 .pm_evc_class = PMC_CLASS_SOFT,
239 .pm_evc_event_table = NULL,
240 .pm_evc_event_table_size = 0,
241 .pm_evc_allocate_pmc = soft_allocate_pmc
242 };
243
244 #undef PMC_CLASS_TABLE_DESC
245
246 static const struct pmc_class_descr **pmc_class_table;
247 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass
248
249 /*
250 * Mapping tables, mapping enumeration values to human readable
251 * strings.
252 */
253
254 static const char * pmc_capability_names[] = {
255 #undef __PMC_CAP
256 #define __PMC_CAP(N,V,D) #N ,
257 __PMC_CAPS()
258 };
259
260 struct pmc_class_map {
261 enum pmc_class pm_class;
262 const char *pm_name;
263 };
264
265 static const struct pmc_class_map pmc_class_names[] = {
266 #undef __PMC_CLASS
267 #define __PMC_CLASS(S,V,D) { .pm_class = PMC_CLASS_##S, .pm_name = #S } ,
268 __PMC_CLASSES()
269 };
270
271 struct pmc_cputype_map {
272 enum pmc_cputype pm_cputype;
273 const char *pm_name;
274 };
275
276 static const struct pmc_cputype_map pmc_cputype_names[] = {
277 #undef __PMC_CPU
278 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } ,
279 __PMC_CPUS()
280 };
281
282 static const char * pmc_disposition_names[] = {
283 #undef __PMC_DISP
284 #define __PMC_DISP(D) #D ,
285 __PMC_DISPOSITIONS()
286 };
287
288 static const char * pmc_mode_names[] = {
289 #undef __PMC_MODE
290 #define __PMC_MODE(M,N) #M ,
291 __PMC_MODES()
292 };
293
294 static const char * pmc_state_names[] = {
295 #undef __PMC_STATE
296 #define __PMC_STATE(S) #S ,
297 __PMC_STATES()
298 };
299
300 /*
301 * Filled in by pmc_init().
302 */
303 static int pmc_syscall = -1;
304 static struct pmc_cpuinfo cpu_info;
305 static struct pmc_op_getdyneventinfo soft_event_info;
306
307 /* Event masks for events */
308 struct pmc_masks {
309 const char *pm_name;
310 const uint64_t pm_value;
311 };
312 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) }
313 #define NULLMASK { .pm_name = NULL }
314
315 #if defined(__amd64__) || defined(__i386__)
316 static int
pmc_parse_mask(const struct pmc_masks * pmask,char * p,uint64_t * evmask)317 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask)
318 {
319 const struct pmc_masks *pm;
320 char *q, *r;
321 int c;
322
323 if (pmask == NULL) /* no mask keywords */
324 return (-1);
325 q = strchr(p, '='); /* skip '=' */
326 if (*++q == '\0') /* no more data */
327 return (-1);
328 c = 0; /* count of mask keywords seen */
329 while ((r = strsep(&q, "+")) != NULL) {
330 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name);
331 pm++)
332 ;
333 if (pm->pm_name == NULL) /* not found */
334 return (-1);
335 *evmask |= pm->pm_value;
336 c++;
337 }
338 return (c);
339 }
340 #endif
341
342 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0)
343 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
344 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S }
345
346 #if defined(__amd64__) || defined(__i386__)
347 /*
348 * AMD K8 PMCs.
349 *
350 */
351
352 static struct pmc_event_alias k8_aliases[] = {
353 EV_ALIAS("branches", "k8-fr-retired-taken-branches"),
354 EV_ALIAS("branch-mispredicts",
355 "k8-fr-retired-taken-branches-mispredicted"),
356 EV_ALIAS("cycles", "tsc"),
357 EV_ALIAS("dc-misses", "k8-dc-miss"),
358 EV_ALIAS("ic-misses", "k8-ic-miss"),
359 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"),
360 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"),
361 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"),
362 EV_ALIAS(NULL, NULL)
363 };
364
365 #define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
366
367 /*
368 * Parsing tables
369 */
370
371 /* fp dispatched fpu ops */
372 static const struct pmc_masks k8_mask_fdfo[] = {
373 __K8MASK(add-pipe-excluding-junk-ops, 0),
374 __K8MASK(multiply-pipe-excluding-junk-ops, 1),
375 __K8MASK(store-pipe-excluding-junk-ops, 2),
376 __K8MASK(add-pipe-junk-ops, 3),
377 __K8MASK(multiply-pipe-junk-ops, 4),
378 __K8MASK(store-pipe-junk-ops, 5),
379 NULLMASK
380 };
381
382 /* ls segment register loads */
383 static const struct pmc_masks k8_mask_lsrl[] = {
384 __K8MASK(es, 0),
385 __K8MASK(cs, 1),
386 __K8MASK(ss, 2),
387 __K8MASK(ds, 3),
388 __K8MASK(fs, 4),
389 __K8MASK(gs, 5),
390 __K8MASK(hs, 6),
391 NULLMASK
392 };
393
394 /* ls locked operation */
395 static const struct pmc_masks k8_mask_llo[] = {
396 __K8MASK(locked-instructions, 0),
397 __K8MASK(cycles-in-request, 1),
398 __K8MASK(cycles-to-complete, 2),
399 NULLMASK
400 };
401
402 /* dc refill from {l2,system} and dc copyback */
403 static const struct pmc_masks k8_mask_dc[] = {
404 __K8MASK(invalid, 0),
405 __K8MASK(shared, 1),
406 __K8MASK(exclusive, 2),
407 __K8MASK(owner, 3),
408 __K8MASK(modified, 4),
409 NULLMASK
410 };
411
412 /* dc one bit ecc error */
413 static const struct pmc_masks k8_mask_dobee[] = {
414 __K8MASK(scrubber, 0),
415 __K8MASK(piggyback, 1),
416 NULLMASK
417 };
418
419 /* dc dispatched prefetch instructions */
420 static const struct pmc_masks k8_mask_ddpi[] = {
421 __K8MASK(load, 0),
422 __K8MASK(store, 1),
423 __K8MASK(nta, 2),
424 NULLMASK
425 };
426
427 /* dc dcache accesses by locks */
428 static const struct pmc_masks k8_mask_dabl[] = {
429 __K8MASK(accesses, 0),
430 __K8MASK(misses, 1),
431 NULLMASK
432 };
433
434 /* bu internal l2 request */
435 static const struct pmc_masks k8_mask_bilr[] = {
436 __K8MASK(ic-fill, 0),
437 __K8MASK(dc-fill, 1),
438 __K8MASK(tlb-reload, 2),
439 __K8MASK(tag-snoop, 3),
440 __K8MASK(cancelled, 4),
441 NULLMASK
442 };
443
444 /* bu fill request l2 miss */
445 static const struct pmc_masks k8_mask_bfrlm[] = {
446 __K8MASK(ic-fill, 0),
447 __K8MASK(dc-fill, 1),
448 __K8MASK(tlb-reload, 2),
449 NULLMASK
450 };
451
452 /* bu fill into l2 */
453 static const struct pmc_masks k8_mask_bfil[] = {
454 __K8MASK(dirty-l2-victim, 0),
455 __K8MASK(victim-from-l2, 1),
456 NULLMASK
457 };
458
459 /* fr retired fpu instructions */
460 static const struct pmc_masks k8_mask_frfi[] = {
461 __K8MASK(x87, 0),
462 __K8MASK(mmx-3dnow, 1),
463 __K8MASK(packed-sse-sse2, 2),
464 __K8MASK(scalar-sse-sse2, 3),
465 NULLMASK
466 };
467
468 /* fr retired fastpath double op instructions */
469 static const struct pmc_masks k8_mask_frfdoi[] = {
470 __K8MASK(low-op-pos-0, 0),
471 __K8MASK(low-op-pos-1, 1),
472 __K8MASK(low-op-pos-2, 2),
473 NULLMASK
474 };
475
476 /* fr fpu exceptions */
477 static const struct pmc_masks k8_mask_ffe[] = {
478 __K8MASK(x87-reclass-microfaults, 0),
479 __K8MASK(sse-retype-microfaults, 1),
480 __K8MASK(sse-reclass-microfaults, 2),
481 __K8MASK(sse-and-x87-microtraps, 3),
482 NULLMASK
483 };
484
485 /* nb memory controller page access event */
486 static const struct pmc_masks k8_mask_nmcpae[] = {
487 __K8MASK(page-hit, 0),
488 __K8MASK(page-miss, 1),
489 __K8MASK(page-conflict, 2),
490 NULLMASK
491 };
492
493 /* nb memory controller turnaround */
494 static const struct pmc_masks k8_mask_nmct[] = {
495 __K8MASK(dimm-turnaround, 0),
496 __K8MASK(read-to-write-turnaround, 1),
497 __K8MASK(write-to-read-turnaround, 2),
498 NULLMASK
499 };
500
501 /* nb memory controller bypass saturation */
502 static const struct pmc_masks k8_mask_nmcbs[] = {
503 __K8MASK(memory-controller-hi-pri-bypass, 0),
504 __K8MASK(memory-controller-lo-pri-bypass, 1),
505 __K8MASK(dram-controller-interface-bypass, 2),
506 __K8MASK(dram-controller-queue-bypass, 3),
507 NULLMASK
508 };
509
510 /* nb sized commands */
511 static const struct pmc_masks k8_mask_nsc[] = {
512 __K8MASK(nonpostwrszbyte, 0),
513 __K8MASK(nonpostwrszdword, 1),
514 __K8MASK(postwrszbyte, 2),
515 __K8MASK(postwrszdword, 3),
516 __K8MASK(rdszbyte, 4),
517 __K8MASK(rdszdword, 5),
518 __K8MASK(rdmodwr, 6),
519 NULLMASK
520 };
521
522 /* nb probe result */
523 static const struct pmc_masks k8_mask_npr[] = {
524 __K8MASK(probe-miss, 0),
525 __K8MASK(probe-hit, 1),
526 __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
527 __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
528 NULLMASK
529 };
530
531 /* nb hypertransport bus bandwidth */
532 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
533 __K8MASK(command, 0),
534 __K8MASK(data, 1),
535 __K8MASK(buffer-release, 2),
536 __K8MASK(nop, 3),
537 NULLMASK
538 };
539
540 #undef __K8MASK
541
542 #define K8_KW_COUNT "count"
543 #define K8_KW_EDGE "edge"
544 #define K8_KW_INV "inv"
545 #define K8_KW_MASK "mask"
546 #define K8_KW_OS "os"
547 #define K8_KW_USR "usr"
548
549 static int
k8_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)550 k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
551 struct pmc_op_pmcallocate *pmc_config)
552 {
553 char *e, *p, *q;
554 int n;
555 uint32_t count;
556 uint64_t evmask;
557 const struct pmc_masks *pm, *pmask;
558
559 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
560 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
561
562 pmask = NULL;
563 evmask = 0;
564
565 #define __K8SETMASK(M) pmask = k8_mask_##M
566
567 /* setup parsing tables */
568 switch (pe) {
569 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
570 __K8SETMASK(fdfo);
571 break;
572 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
573 __K8SETMASK(lsrl);
574 break;
575 case PMC_EV_K8_LS_LOCKED_OPERATION:
576 __K8SETMASK(llo);
577 break;
578 case PMC_EV_K8_DC_REFILL_FROM_L2:
579 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
580 case PMC_EV_K8_DC_COPYBACK:
581 __K8SETMASK(dc);
582 break;
583 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
584 __K8SETMASK(dobee);
585 break;
586 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
587 __K8SETMASK(ddpi);
588 break;
589 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
590 __K8SETMASK(dabl);
591 break;
592 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
593 __K8SETMASK(bilr);
594 break;
595 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
596 __K8SETMASK(bfrlm);
597 break;
598 case PMC_EV_K8_BU_FILL_INTO_L2:
599 __K8SETMASK(bfil);
600 break;
601 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
602 __K8SETMASK(frfi);
603 break;
604 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
605 __K8SETMASK(frfdoi);
606 break;
607 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
608 __K8SETMASK(ffe);
609 break;
610 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
611 __K8SETMASK(nmcpae);
612 break;
613 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
614 __K8SETMASK(nmct);
615 break;
616 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
617 __K8SETMASK(nmcbs);
618 break;
619 case PMC_EV_K8_NB_SIZED_COMMANDS:
620 __K8SETMASK(nsc);
621 break;
622 case PMC_EV_K8_NB_PROBE_RESULT:
623 __K8SETMASK(npr);
624 break;
625 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
626 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
627 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
628 __K8SETMASK(nhbb);
629 break;
630
631 default:
632 break; /* no options defined */
633 }
634
635 while ((p = strsep(&ctrspec, ",")) != NULL) {
636 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
637 q = strchr(p, '=');
638 if (*++q == '\0') /* skip '=' */
639 return (-1);
640
641 count = strtol(q, &e, 0);
642 if (e == q || *e != '\0')
643 return (-1);
644
645 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
646 pmc_config->pm_md.pm_amd.pm_amd_config |=
647 AMD_PMC_TO_COUNTER(count);
648
649 } else if (KWMATCH(p, K8_KW_EDGE)) {
650 pmc_config->pm_caps |= PMC_CAP_EDGE;
651 } else if (KWMATCH(p, K8_KW_INV)) {
652 pmc_config->pm_caps |= PMC_CAP_INVERT;
653 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
654 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
655 return (-1);
656 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
657 } else if (KWMATCH(p, K8_KW_OS)) {
658 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
659 } else if (KWMATCH(p, K8_KW_USR)) {
660 pmc_config->pm_caps |= PMC_CAP_USER;
661 } else
662 return (-1);
663 }
664
665 /* other post processing */
666 switch (pe) {
667 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
668 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
669 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
670 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
671 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
672 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
673 /* XXX only available in rev B and later */
674 break;
675 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
676 /* XXX only available in rev C and later */
677 break;
678 case PMC_EV_K8_LS_LOCKED_OPERATION:
679 /* XXX CPU Rev A,B evmask is to be zero */
680 if (evmask & (evmask - 1)) /* > 1 bit set */
681 return (-1);
682 if (evmask == 0) {
683 evmask = 0x01; /* Rev C and later: #instrs */
684 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
685 }
686 break;
687 default:
688 if (evmask == 0 && pmask != NULL) {
689 for (pm = pmask; pm->pm_name; pm++)
690 evmask |= pm->pm_value;
691 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
692 }
693 }
694
695 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
696 pmc_config->pm_md.pm_amd.pm_amd_config =
697 AMD_PMC_TO_UNITMASK(evmask);
698
699 return (0);
700 }
701
702 #endif
703
704 #if defined(__i386__) || defined(__amd64__)
705 static int
tsc_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)706 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec,
707 struct pmc_op_pmcallocate *pmc_config)
708 {
709 if (pe != PMC_EV_TSC_TSC)
710 return (-1);
711
712 /* TSC events must be unqualified. */
713 if (ctrspec && *ctrspec != '\0')
714 return (-1);
715
716 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
717 pmc_config->pm_caps |= PMC_CAP_READ;
718
719 return (0);
720 }
721 #endif
722
723 static struct pmc_event_alias generic_aliases[] = {
724 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"),
725 EV_ALIAS(NULL, NULL)
726 };
727
728 static int
soft_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)729 soft_allocate_pmc(enum pmc_event pe, char *ctrspec,
730 struct pmc_op_pmcallocate *pmc_config)
731 {
732 (void)ctrspec;
733 (void)pmc_config;
734
735 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST)
736 return (-1);
737
738 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
739 return (0);
740 }
741
742 #if defined(__arm__)
743 static struct pmc_event_alias cortex_a8_aliases[] = {
744 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"),
745 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"),
746 EV_ALIAS("instructions", "INSTR_EXECUTED"),
747 EV_ALIAS(NULL, NULL)
748 };
749
750 static struct pmc_event_alias cortex_a9_aliases[] = {
751 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"),
752 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"),
753 EV_ALIAS("instructions", "INSTR_EXECUTED"),
754 EV_ALIAS(NULL, NULL)
755 };
756
757 static int
armv7_allocate_pmc(enum pmc_event pe,char * ctrspec __unused,struct pmc_op_pmcallocate * pmc_config __unused)758 armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
759 struct pmc_op_pmcallocate *pmc_config __unused)
760 {
761 switch (pe) {
762 default:
763 break;
764 }
765
766 return (0);
767 }
768 #endif
769
770 #if defined(__aarch64__)
771 static struct pmc_event_alias cortex_a53_aliases[] = {
772 EV_ALIAS(NULL, NULL)
773 };
774 static struct pmc_event_alias cortex_a57_aliases[] = {
775 EV_ALIAS(NULL, NULL)
776 };
777 static struct pmc_event_alias cortex_a76_aliases[] = {
778 EV_ALIAS(NULL, NULL)
779 };
780
781 static int
arm64_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)782 arm64_allocate_pmc(enum pmc_event pe, char *ctrspec,
783 struct pmc_op_pmcallocate *pmc_config)
784 {
785 char *p;
786
787 while ((p = strsep(&ctrspec, ",")) != NULL) {
788 if (KWMATCH(p, "os"))
789 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
790 else if (KWMATCH(p, "usr"))
791 pmc_config->pm_caps |= PMC_CAP_USER;
792 else
793 return (-1);
794 }
795
796 return (0);
797 }
798 #endif
799
800 #if defined(__mips__)
801
802 static struct pmc_event_alias beri_aliases[] = {
803 EV_ALIAS("instructions", "INST"),
804 EV_ALIAS(NULL, NULL)
805 };
806
807 static struct pmc_event_alias mips24k_aliases[] = {
808 EV_ALIAS("instructions", "INSTR_EXECUTED"),
809 EV_ALIAS("branches", "BRANCH_COMPLETED"),
810 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"),
811 EV_ALIAS(NULL, NULL)
812 };
813
814 static struct pmc_event_alias mips74k_aliases[] = {
815 EV_ALIAS("instructions", "INSTR_EXECUTED"),
816 EV_ALIAS("branches", "BRANCH_INSNS"),
817 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCH_INSNS"),
818 EV_ALIAS(NULL, NULL)
819 };
820
821 static struct pmc_event_alias octeon_aliases[] = {
822 EV_ALIAS("instructions", "RET"),
823 EV_ALIAS("branches", "BR"),
824 EV_ALIAS("branch-mispredicts", "BRMIS"),
825 EV_ALIAS(NULL, NULL)
826 };
827
828 #define MIPS_KW_OS "os"
829 #define MIPS_KW_USR "usr"
830 #define MIPS_KW_ANYTHREAD "anythread"
831
832 static int
mips_allocate_pmc(enum pmc_event pe,char * ctrspec __unused,struct pmc_op_pmcallocate * pmc_config __unused)833 mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
834 struct pmc_op_pmcallocate *pmc_config __unused)
835 {
836 char *p;
837
838 (void) pe;
839
840 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
841
842 while ((p = strsep(&ctrspec, ",")) != NULL) {
843 if (KWMATCH(p, MIPS_KW_OS))
844 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
845 else if (KWMATCH(p, MIPS_KW_USR))
846 pmc_config->pm_caps |= PMC_CAP_USER;
847 else if (KWMATCH(p, MIPS_KW_ANYTHREAD))
848 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
849 else
850 return (-1);
851 }
852
853 return (0);
854 }
855
856 #endif /* __mips__ */
857
858 #if defined(__powerpc__)
859
860 static struct pmc_event_alias ppc7450_aliases[] = {
861 EV_ALIAS("instructions", "INSTR_COMPLETED"),
862 EV_ALIAS("branches", "BRANCHES_COMPLETED"),
863 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"),
864 EV_ALIAS(NULL, NULL)
865 };
866
867 static struct pmc_event_alias ppc970_aliases[] = {
868 EV_ALIAS("instructions", "INSTR_COMPLETED"),
869 EV_ALIAS("cycles", "CYCLES"),
870 EV_ALIAS(NULL, NULL)
871 };
872
873 static struct pmc_event_alias power8_aliases[] = {
874 EV_ALIAS("instructions", "INSTR_COMPLETED"),
875 EV_ALIAS("cycles", "CYCLES"),
876 EV_ALIAS(NULL, NULL)
877 };
878
879 static struct pmc_event_alias e500_aliases[] = {
880 EV_ALIAS("instructions", "INSTR_COMPLETED"),
881 EV_ALIAS("cycles", "CYCLES"),
882 EV_ALIAS(NULL, NULL)
883 };
884
885 #define POWERPC_KW_OS "os"
886 #define POWERPC_KW_USR "usr"
887 #define POWERPC_KW_ANYTHREAD "anythread"
888
889 static int
powerpc_allocate_pmc(enum pmc_event pe,char * ctrspec __unused,struct pmc_op_pmcallocate * pmc_config __unused)890 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
891 struct pmc_op_pmcallocate *pmc_config __unused)
892 {
893 char *p;
894
895 (void) pe;
896
897 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
898
899 while ((p = strsep(&ctrspec, ",")) != NULL) {
900 if (KWMATCH(p, POWERPC_KW_OS))
901 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
902 else if (KWMATCH(p, POWERPC_KW_USR))
903 pmc_config->pm_caps |= PMC_CAP_USER;
904 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD))
905 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
906 else
907 return (-1);
908 }
909
910 return (0);
911 }
912
913 #endif /* __powerpc__ */
914
915
916 /*
917 * Match an event name `name' with its canonical form.
918 *
919 * Matches are case insensitive and spaces, periods, underscores and
920 * hyphen characters are considered to match each other.
921 *
922 * Returns 1 for a match, 0 otherwise.
923 */
924
925 static int
pmc_match_event_name(const char * name,const char * canonicalname)926 pmc_match_event_name(const char *name, const char *canonicalname)
927 {
928 int cc, nc;
929 const unsigned char *c, *n;
930
931 c = (const unsigned char *) canonicalname;
932 n = (const unsigned char *) name;
933
934 for (; (nc = *n) && (cc = *c); n++, c++) {
935
936 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') &&
937 (cc == ' ' || cc == '_' || cc == '-' || cc == '.'))
938 continue;
939
940 if (toupper(nc) == toupper(cc))
941 continue;
942
943
944 return (0);
945 }
946
947 if (*n == '\0' && *c == '\0')
948 return (1);
949
950 return (0);
951 }
952
953 /*
954 * Match an event name against all the event named supported by a
955 * PMC class.
956 *
957 * Returns an event descriptor pointer on match or NULL otherwise.
958 */
959 static const struct pmc_event_descr *
pmc_match_event_class(const char * name,const struct pmc_class_descr * pcd)960 pmc_match_event_class(const char *name,
961 const struct pmc_class_descr *pcd)
962 {
963 size_t n;
964 const struct pmc_event_descr *ev;
965
966 ev = pcd->pm_evc_event_table;
967 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++)
968 if (pmc_match_event_name(name, ev->pm_ev_name))
969 return (ev);
970
971 return (NULL);
972 }
973
974 /*
975 * API entry points
976 */
977
978 int
pmc_allocate(const char * ctrspec,enum pmc_mode mode,uint32_t flags,int cpu,pmc_id_t * pmcid,uint64_t count)979 pmc_allocate(const char *ctrspec, enum pmc_mode mode,
980 uint32_t flags, int cpu, pmc_id_t *pmcid,
981 uint64_t count)
982 {
983 size_t n;
984 int retval;
985 char *r, *spec_copy;
986 const char *ctrname;
987 const struct pmc_event_descr *ev;
988 const struct pmc_event_alias *alias;
989 struct pmc_op_pmcallocate pmc_config;
990 const struct pmc_class_descr *pcd;
991
992 spec_copy = NULL;
993 retval = -1;
994
995 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
996 mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
997 errno = EINVAL;
998 goto out;
999 }
1000 bzero(&pmc_config, sizeof(pmc_config));
1001 pmc_config.pm_cpu = cpu;
1002 pmc_config.pm_mode = mode;
1003 pmc_config.pm_flags = flags;
1004 pmc_config.pm_count = count;
1005 if (PMC_IS_SAMPLING_MODE(mode))
1006 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
1007
1008 /*
1009 * Try to pull the raw event ID directly from the pmu-events table. If
1010 * this is unsupported on the platform, or the event is not found,
1011 * continue with searching the regular event tables.
1012 */
1013 r = spec_copy = strdup(ctrspec);
1014 ctrname = strsep(&r, ",");
1015 if (pmc_pmu_enabled()) {
1016 if (pmc_pmu_pmcallocate(ctrname, &pmc_config) == 0) {
1017 /*
1018 * XXX: pmclog_get_event exploits this to disambiguate
1019 * PMU from PMC event codes in PMCALLOCATE events.
1020 */
1021 assert(pmc_config.pm_ev < PMC_EVENT_FIRST);
1022 goto found;
1023 }
1024
1025 /* Otherwise, reset any changes */
1026 pmc_config.pm_ev = 0;
1027 pmc_config.pm_caps = 0;
1028 pmc_config.pm_class = 0;
1029 }
1030 free(spec_copy);
1031 spec_copy = NULL;
1032
1033 /* replace an event alias with the canonical event specifier */
1034 if (pmc_mdep_event_aliases)
1035 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++)
1036 if (!strcasecmp(ctrspec, alias->pm_alias)) {
1037 spec_copy = strdup(alias->pm_spec);
1038 break;
1039 }
1040
1041 if (spec_copy == NULL)
1042 spec_copy = strdup(ctrspec);
1043
1044 r = spec_copy;
1045 ctrname = strsep(&r, ",");
1046
1047 /*
1048 * If a explicit class prefix was given by the user, restrict the
1049 * search for the event to the specified PMC class.
1050 */
1051 ev = NULL;
1052 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) {
1053 pcd = pmc_class_table[n];
1054 if (pcd != NULL && strncasecmp(ctrname, pcd->pm_evc_name,
1055 pcd->pm_evc_name_size) == 0) {
1056 if ((ev = pmc_match_event_class(ctrname +
1057 pcd->pm_evc_name_size, pcd)) == NULL) {
1058 errno = EINVAL;
1059 goto out;
1060 }
1061 break;
1062 }
1063 }
1064
1065 /*
1066 * Otherwise, search for this event in all compatible PMC
1067 * classes.
1068 */
1069 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) {
1070 pcd = pmc_class_table[n];
1071 if (pcd != NULL)
1072 ev = pmc_match_event_class(ctrname, pcd);
1073 }
1074
1075 if (ev == NULL) {
1076 errno = EINVAL;
1077 goto out;
1078 }
1079
1080 pmc_config.pm_ev = ev->pm_ev_code;
1081 pmc_config.pm_class = pcd->pm_evc_class;
1082
1083 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) {
1084 errno = EINVAL;
1085 goto out;
1086 }
1087
1088 found:
1089 if (PMC_CALL(PMC_OP_PMCALLOCATE, &pmc_config) == 0) {
1090 *pmcid = pmc_config.pm_pmcid;
1091 retval = 0;
1092 }
1093 out:
1094 if (spec_copy)
1095 free(spec_copy);
1096
1097 return (retval);
1098 }
1099
1100 int
pmc_attach(pmc_id_t pmc,pid_t pid)1101 pmc_attach(pmc_id_t pmc, pid_t pid)
1102 {
1103 struct pmc_op_pmcattach pmc_attach_args;
1104
1105 pmc_attach_args.pm_pmc = pmc;
1106 pmc_attach_args.pm_pid = pid;
1107
1108 return (PMC_CALL(PMC_OP_PMCATTACH, &pmc_attach_args));
1109 }
1110
1111 int
pmc_capabilities(pmc_id_t pmcid,uint32_t * caps)1112 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps)
1113 {
1114 unsigned int i;
1115 enum pmc_class cl;
1116
1117 cl = PMC_ID_TO_CLASS(pmcid);
1118 for (i = 0; i < cpu_info.pm_nclass; i++)
1119 if (cpu_info.pm_classes[i].pm_class == cl) {
1120 *caps = cpu_info.pm_classes[i].pm_caps;
1121 return (0);
1122 }
1123 errno = EINVAL;
1124 return (-1);
1125 }
1126
1127 int
pmc_configure_logfile(int fd)1128 pmc_configure_logfile(int fd)
1129 {
1130 struct pmc_op_configurelog cla;
1131
1132 cla.pm_logfd = fd;
1133 if (PMC_CALL(PMC_OP_CONFIGURELOG, &cla) < 0)
1134 return (-1);
1135 return (0);
1136 }
1137
1138 int
pmc_cpuinfo(const struct pmc_cpuinfo ** pci)1139 pmc_cpuinfo(const struct pmc_cpuinfo **pci)
1140 {
1141 if (pmc_syscall == -1) {
1142 errno = ENXIO;
1143 return (-1);
1144 }
1145
1146 *pci = &cpu_info;
1147 return (0);
1148 }
1149
1150 int
pmc_detach(pmc_id_t pmc,pid_t pid)1151 pmc_detach(pmc_id_t pmc, pid_t pid)
1152 {
1153 struct pmc_op_pmcattach pmc_detach_args;
1154
1155 pmc_detach_args.pm_pmc = pmc;
1156 pmc_detach_args.pm_pid = pid;
1157 return (PMC_CALL(PMC_OP_PMCDETACH, &pmc_detach_args));
1158 }
1159
1160 int
pmc_disable(int cpu,int pmc)1161 pmc_disable(int cpu, int pmc)
1162 {
1163 struct pmc_op_pmcadmin ssa;
1164
1165 ssa.pm_cpu = cpu;
1166 ssa.pm_pmc = pmc;
1167 ssa.pm_state = PMC_STATE_DISABLED;
1168 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa));
1169 }
1170
1171 int
pmc_enable(int cpu,int pmc)1172 pmc_enable(int cpu, int pmc)
1173 {
1174 struct pmc_op_pmcadmin ssa;
1175
1176 ssa.pm_cpu = cpu;
1177 ssa.pm_pmc = pmc;
1178 ssa.pm_state = PMC_STATE_FREE;
1179 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa));
1180 }
1181
1182 /*
1183 * Return a list of events known to a given PMC class. 'cl' is the
1184 * PMC class identifier, 'eventnames' is the returned list of 'const
1185 * char *' pointers pointing to the names of the events. 'nevents' is
1186 * the number of event name pointers returned.
1187 *
1188 * The space for 'eventnames' is allocated using malloc(3). The caller
1189 * is responsible for freeing this space when done.
1190 */
1191 int
pmc_event_names_of_class(enum pmc_class cl,const char *** eventnames,int * nevents)1192 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
1193 int *nevents)
1194 {
1195 int count;
1196 const char **names;
1197 const struct pmc_event_descr *ev;
1198
1199 switch (cl)
1200 {
1201 case PMC_CLASS_IAF:
1202 ev = iaf_event_table;
1203 count = PMC_EVENT_TABLE_SIZE(iaf);
1204 break;
1205 case PMC_CLASS_TSC:
1206 ev = tsc_event_table;
1207 count = PMC_EVENT_TABLE_SIZE(tsc);
1208 break;
1209 case PMC_CLASS_K8:
1210 ev = k8_event_table;
1211 count = PMC_EVENT_TABLE_SIZE(k8);
1212 break;
1213 case PMC_CLASS_ARMV7:
1214 switch (cpu_info.pm_cputype) {
1215 default:
1216 case PMC_CPU_ARMV7_CORTEX_A8:
1217 ev = cortex_a8_event_table;
1218 count = PMC_EVENT_TABLE_SIZE(cortex_a8);
1219 break;
1220 case PMC_CPU_ARMV7_CORTEX_A9:
1221 ev = cortex_a9_event_table;
1222 count = PMC_EVENT_TABLE_SIZE(cortex_a9);
1223 break;
1224 }
1225 break;
1226 case PMC_CLASS_ARMV8:
1227 switch (cpu_info.pm_cputype) {
1228 default:
1229 case PMC_CPU_ARMV8_CORTEX_A53:
1230 ev = cortex_a53_event_table;
1231 count = PMC_EVENT_TABLE_SIZE(cortex_a53);
1232 break;
1233 case PMC_CPU_ARMV8_CORTEX_A57:
1234 ev = cortex_a57_event_table;
1235 count = PMC_EVENT_TABLE_SIZE(cortex_a57);
1236 break;
1237 case PMC_CPU_ARMV8_CORTEX_A76:
1238 ev = cortex_a76_event_table;
1239 count = PMC_EVENT_TABLE_SIZE(cortex_a76);
1240 break;
1241 }
1242 break;
1243 case PMC_CLASS_BERI:
1244 ev = beri_event_table;
1245 count = PMC_EVENT_TABLE_SIZE(beri);
1246 break;
1247 case PMC_CLASS_MIPS24K:
1248 ev = mips24k_event_table;
1249 count = PMC_EVENT_TABLE_SIZE(mips24k);
1250 break;
1251 case PMC_CLASS_MIPS74K:
1252 ev = mips74k_event_table;
1253 count = PMC_EVENT_TABLE_SIZE(mips74k);
1254 break;
1255 case PMC_CLASS_OCTEON:
1256 ev = octeon_event_table;
1257 count = PMC_EVENT_TABLE_SIZE(octeon);
1258 break;
1259 case PMC_CLASS_PPC7450:
1260 ev = ppc7450_event_table;
1261 count = PMC_EVENT_TABLE_SIZE(ppc7450);
1262 break;
1263 case PMC_CLASS_PPC970:
1264 ev = ppc970_event_table;
1265 count = PMC_EVENT_TABLE_SIZE(ppc970);
1266 break;
1267 case PMC_CLASS_POWER8:
1268 ev = power8_event_table;
1269 count = PMC_EVENT_TABLE_SIZE(power8);
1270 break;
1271 case PMC_CLASS_E500:
1272 ev = e500_event_table;
1273 count = PMC_EVENT_TABLE_SIZE(e500);
1274 break;
1275 case PMC_CLASS_SOFT:
1276 ev = soft_event_table;
1277 count = soft_event_info.pm_nevent;
1278 break;
1279 default:
1280 errno = EINVAL;
1281 return (-1);
1282 }
1283
1284 if ((names = malloc(count * sizeof(const char *))) == NULL)
1285 return (-1);
1286
1287 *eventnames = names;
1288 *nevents = count;
1289
1290 for (;count--; ev++, names++)
1291 *names = ev->pm_ev_name;
1292
1293 return (0);
1294 }
1295
1296 int
pmc_flush_logfile(void)1297 pmc_flush_logfile(void)
1298 {
1299 return (PMC_CALL(PMC_OP_FLUSHLOG, 0));
1300 }
1301
1302 int
pmc_close_logfile(void)1303 pmc_close_logfile(void)
1304 {
1305 return (PMC_CALL(PMC_OP_CLOSELOG, 0));
1306 }
1307
1308 int
pmc_get_driver_stats(struct pmc_driverstats * ds)1309 pmc_get_driver_stats(struct pmc_driverstats *ds)
1310 {
1311 struct pmc_op_getdriverstats gms;
1312
1313 if (PMC_CALL(PMC_OP_GETDRIVERSTATS, &gms) < 0)
1314 return (-1);
1315
1316 /* copy out fields in the current userland<->library interface */
1317 ds->pm_intr_ignored = gms.pm_intr_ignored;
1318 ds->pm_intr_processed = gms.pm_intr_processed;
1319 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull;
1320 ds->pm_syscalls = gms.pm_syscalls;
1321 ds->pm_syscall_errors = gms.pm_syscall_errors;
1322 ds->pm_buffer_requests = gms.pm_buffer_requests;
1323 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed;
1324 ds->pm_log_sweeps = gms.pm_log_sweeps;
1325 return (0);
1326 }
1327
1328 int
pmc_get_msr(pmc_id_t pmc,uint32_t * msr)1329 pmc_get_msr(pmc_id_t pmc, uint32_t *msr)
1330 {
1331 struct pmc_op_getmsr gm;
1332
1333 gm.pm_pmcid = pmc;
1334 if (PMC_CALL(PMC_OP_PMCGETMSR, &gm) < 0)
1335 return (-1);
1336 *msr = gm.pm_msr;
1337 return (0);
1338 }
1339
1340 int
pmc_init(void)1341 pmc_init(void)
1342 {
1343 int error, pmc_mod_id;
1344 unsigned int n;
1345 uint32_t abi_version;
1346 struct module_stat pmc_modstat;
1347 struct pmc_op_getcpuinfo op_cpu_info;
1348
1349 if (pmc_syscall != -1) /* already inited */
1350 return (0);
1351
1352 /* retrieve the system call number from the KLD */
1353 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
1354 return (-1);
1355
1356 pmc_modstat.version = sizeof(struct module_stat);
1357 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
1358 return (-1);
1359
1360 pmc_syscall = pmc_modstat.data.intval;
1361
1362 /* check the kernel module's ABI against our compiled-in version */
1363 abi_version = PMC_VERSION;
1364 if (PMC_CALL(PMC_OP_GETMODULEVERSION, &abi_version) < 0)
1365 return (pmc_syscall = -1);
1366
1367 /* ignore patch & minor numbers for the comparison */
1368 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) {
1369 errno = EPROGMISMATCH;
1370 return (pmc_syscall = -1);
1371 }
1372
1373 bzero(&op_cpu_info, sizeof(op_cpu_info));
1374 if (PMC_CALL(PMC_OP_GETCPUINFO, &op_cpu_info) < 0)
1375 return (pmc_syscall = -1);
1376
1377 cpu_info.pm_cputype = op_cpu_info.pm_cputype;
1378 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu;
1379 cpu_info.pm_npmc = op_cpu_info.pm_npmc;
1380 cpu_info.pm_nclass = op_cpu_info.pm_nclass;
1381 for (n = 0; n < op_cpu_info.pm_nclass; n++)
1382 memcpy(&cpu_info.pm_classes[n], &op_cpu_info.pm_classes[n],
1383 sizeof(cpu_info.pm_classes[n]));
1384
1385 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE *
1386 sizeof(struct pmc_class_descr *));
1387
1388 if (pmc_class_table == NULL)
1389 return (-1);
1390
1391 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++)
1392 pmc_class_table[n] = NULL;
1393
1394 /*
1395 * Get soft events list.
1396 */
1397 soft_event_info.pm_class = PMC_CLASS_SOFT;
1398 if (PMC_CALL(PMC_OP_GETDYNEVENTINFO, &soft_event_info) < 0)
1399 return (pmc_syscall = -1);
1400
1401 /* Map soft events to static list. */
1402 for (n = 0; n < soft_event_info.pm_nevent; n++) {
1403 soft_event_table[n].pm_ev_name =
1404 soft_event_info.pm_events[n].pm_ev_name;
1405 soft_event_table[n].pm_ev_code =
1406 soft_event_info.pm_events[n].pm_ev_code;
1407 }
1408 soft_class_table_descr.pm_evc_event_table_size = \
1409 soft_event_info.pm_nevent;
1410 soft_class_table_descr.pm_evc_event_table = \
1411 soft_event_table;
1412
1413 /*
1414 * Fill in the class table.
1415 */
1416 n = 0;
1417
1418 /* Fill soft events information. */
1419 pmc_class_table[n++] = &soft_class_table_descr;
1420 #if defined(__amd64__) || defined(__i386__)
1421 if (cpu_info.pm_cputype != PMC_CPU_GENERIC)
1422 pmc_class_table[n++] = &tsc_class_table_descr;
1423 #endif
1424
1425 #define PMC_MDEP_INIT(C) pmc_mdep_event_aliases = C##_aliases
1426
1427 /* Configure the event name parser. */
1428 switch (cpu_info.pm_cputype) {
1429 #if defined(__amd64__) || defined(__i386__)
1430 case PMC_CPU_AMD_K8:
1431 PMC_MDEP_INIT(k8);
1432 pmc_class_table[n] = &k8_class_table_descr;
1433 break;
1434 #endif
1435 case PMC_CPU_GENERIC:
1436 PMC_MDEP_INIT(generic);
1437 break;
1438 #if defined(__arm__)
1439 case PMC_CPU_ARMV7_CORTEX_A8:
1440 PMC_MDEP_INIT(cortex_a8);
1441 pmc_class_table[n] = &cortex_a8_class_table_descr;
1442 break;
1443 case PMC_CPU_ARMV7_CORTEX_A9:
1444 PMC_MDEP_INIT(cortex_a9);
1445 pmc_class_table[n] = &cortex_a9_class_table_descr;
1446 break;
1447 #endif
1448 #if defined(__aarch64__)
1449 case PMC_CPU_ARMV8_CORTEX_A53:
1450 PMC_MDEP_INIT(cortex_a53);
1451 pmc_class_table[n] = &cortex_a53_class_table_descr;
1452 break;
1453 case PMC_CPU_ARMV8_CORTEX_A57:
1454 PMC_MDEP_INIT(cortex_a57);
1455 pmc_class_table[n] = &cortex_a57_class_table_descr;
1456 break;
1457 case PMC_CPU_ARMV8_CORTEX_A76:
1458 PMC_MDEP_INIT(cortex_a76);
1459 pmc_class_table[n] = &cortex_a76_class_table_descr;
1460 break;
1461 #endif
1462 #if defined(__mips__)
1463 case PMC_CPU_MIPS_BERI:
1464 PMC_MDEP_INIT(beri);
1465 pmc_class_table[n] = &beri_class_table_descr;
1466 break;
1467 case PMC_CPU_MIPS_24K:
1468 PMC_MDEP_INIT(mips24k);
1469 pmc_class_table[n] = &mips24k_class_table_descr;
1470 break;
1471 case PMC_CPU_MIPS_74K:
1472 PMC_MDEP_INIT(mips74k);
1473 pmc_class_table[n] = &mips74k_class_table_descr;
1474 break;
1475 case PMC_CPU_MIPS_OCTEON:
1476 PMC_MDEP_INIT(octeon);
1477 pmc_class_table[n] = &octeon_class_table_descr;
1478 break;
1479 #endif /* __mips__ */
1480 #if defined(__powerpc__)
1481 case PMC_CPU_PPC_7450:
1482 PMC_MDEP_INIT(ppc7450);
1483 pmc_class_table[n] = &ppc7450_class_table_descr;
1484 break;
1485 case PMC_CPU_PPC_970:
1486 PMC_MDEP_INIT(ppc970);
1487 pmc_class_table[n] = &ppc970_class_table_descr;
1488 break;
1489 case PMC_CPU_PPC_POWER8:
1490 PMC_MDEP_INIT(power8);
1491 pmc_class_table[n] = &power8_class_table_descr;
1492 break;
1493 case PMC_CPU_PPC_E500:
1494 PMC_MDEP_INIT(e500);
1495 pmc_class_table[n] = &e500_class_table_descr;
1496 break;
1497 #endif
1498 default:
1499 /*
1500 * Some kind of CPU this version of the library knows nothing
1501 * about. This shouldn't happen since the abi version check
1502 * should have caught this.
1503 */
1504 #if defined(__amd64__) || defined(__i386__)
1505 break;
1506 #endif
1507 errno = ENXIO;
1508 return (pmc_syscall = -1);
1509 }
1510
1511 return (0);
1512 }
1513
1514 const char *
pmc_name_of_capability(enum pmc_caps cap)1515 pmc_name_of_capability(enum pmc_caps cap)
1516 {
1517 int i;
1518
1519 /*
1520 * 'cap' should have a single bit set and should be in
1521 * range.
1522 */
1523 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
1524 cap > PMC_CAP_LAST) {
1525 errno = EINVAL;
1526 return (NULL);
1527 }
1528
1529 i = ffs(cap);
1530 return (pmc_capability_names[i - 1]);
1531 }
1532
1533 const char *
pmc_name_of_class(enum pmc_class pc)1534 pmc_name_of_class(enum pmc_class pc)
1535 {
1536 size_t n;
1537
1538 for (n = 0; n < PMC_TABLE_SIZE(pmc_class_names); n++)
1539 if (pc == pmc_class_names[n].pm_class)
1540 return (pmc_class_names[n].pm_name);
1541
1542 errno = EINVAL;
1543 return (NULL);
1544 }
1545
1546 const char *
pmc_name_of_cputype(enum pmc_cputype cp)1547 pmc_name_of_cputype(enum pmc_cputype cp)
1548 {
1549 size_t n;
1550
1551 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++)
1552 if (cp == pmc_cputype_names[n].pm_cputype)
1553 return (pmc_cputype_names[n].pm_name);
1554
1555 errno = EINVAL;
1556 return (NULL);
1557 }
1558
1559 const char *
pmc_name_of_disposition(enum pmc_disp pd)1560 pmc_name_of_disposition(enum pmc_disp pd)
1561 {
1562 if ((int) pd >= PMC_DISP_FIRST &&
1563 pd <= PMC_DISP_LAST)
1564 return (pmc_disposition_names[pd]);
1565
1566 errno = EINVAL;
1567 return (NULL);
1568 }
1569
1570 const char *
_pmc_name_of_event(enum pmc_event pe,enum pmc_cputype cpu)1571 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
1572 {
1573 const struct pmc_event_descr *ev, *evfence;
1574
1575 ev = evfence = NULL;
1576 if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
1577 ev = k8_event_table;
1578 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
1579
1580 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) {
1581 switch (cpu) {
1582 case PMC_CPU_ARMV7_CORTEX_A8:
1583 ev = cortex_a8_event_table;
1584 evfence = cortex_a8_event_table + PMC_EVENT_TABLE_SIZE(cortex_a8);
1585 break;
1586 case PMC_CPU_ARMV7_CORTEX_A9:
1587 ev = cortex_a9_event_table;
1588 evfence = cortex_a9_event_table + PMC_EVENT_TABLE_SIZE(cortex_a9);
1589 break;
1590 default: /* Unknown CPU type. */
1591 break;
1592 }
1593 } else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) {
1594 switch (cpu) {
1595 case PMC_CPU_ARMV8_CORTEX_A53:
1596 ev = cortex_a53_event_table;
1597 evfence = cortex_a53_event_table + PMC_EVENT_TABLE_SIZE(cortex_a53);
1598 break;
1599 case PMC_CPU_ARMV8_CORTEX_A57:
1600 ev = cortex_a57_event_table;
1601 evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57);
1602 break;
1603 case PMC_CPU_ARMV8_CORTEX_A76:
1604 ev = cortex_a76_event_table;
1605 evfence = cortex_a76_event_table + PMC_EVENT_TABLE_SIZE(cortex_a76);
1606 break;
1607 default: /* Unknown CPU type. */
1608 break;
1609 }
1610 } else if (pe >= PMC_EV_BERI_FIRST && pe <= PMC_EV_BERI_LAST) {
1611 ev = beri_event_table;
1612 evfence = beri_event_table + PMC_EVENT_TABLE_SIZE(beri);
1613 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) {
1614 ev = mips24k_event_table;
1615 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k);
1616 } else if (pe >= PMC_EV_MIPS74K_FIRST && pe <= PMC_EV_MIPS74K_LAST) {
1617 ev = mips74k_event_table;
1618 evfence = mips74k_event_table + PMC_EVENT_TABLE_SIZE(mips74k);
1619 } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) {
1620 ev = octeon_event_table;
1621 evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon);
1622 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) {
1623 ev = ppc7450_event_table;
1624 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450);
1625 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) {
1626 ev = ppc970_event_table;
1627 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970);
1628 } else if (pe >= PMC_EV_POWER8_FIRST && pe <= PMC_EV_POWER8_LAST) {
1629 ev = power8_event_table;
1630 evfence = power8_event_table + PMC_EVENT_TABLE_SIZE(power8);
1631 } else if (pe >= PMC_EV_E500_FIRST && pe <= PMC_EV_E500_LAST) {
1632 ev = e500_event_table;
1633 evfence = e500_event_table + PMC_EVENT_TABLE_SIZE(e500);
1634 } else if (pe == PMC_EV_TSC_TSC) {
1635 ev = tsc_event_table;
1636 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
1637 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) {
1638 ev = soft_event_table;
1639 evfence = soft_event_table + soft_event_info.pm_nevent;
1640 }
1641
1642 for (; ev != evfence; ev++)
1643 if (pe == ev->pm_ev_code)
1644 return (ev->pm_ev_name);
1645
1646 return (NULL);
1647 }
1648
1649 const char *
pmc_name_of_event(enum pmc_event pe)1650 pmc_name_of_event(enum pmc_event pe)
1651 {
1652 const char *n;
1653
1654 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL)
1655 return (n);
1656
1657 errno = EINVAL;
1658 return (NULL);
1659 }
1660
1661 const char *
pmc_name_of_mode(enum pmc_mode pm)1662 pmc_name_of_mode(enum pmc_mode pm)
1663 {
1664 if ((int) pm >= PMC_MODE_FIRST &&
1665 pm <= PMC_MODE_LAST)
1666 return (pmc_mode_names[pm]);
1667
1668 errno = EINVAL;
1669 return (NULL);
1670 }
1671
1672 const char *
pmc_name_of_state(enum pmc_state ps)1673 pmc_name_of_state(enum pmc_state ps)
1674 {
1675 if ((int) ps >= PMC_STATE_FIRST &&
1676 ps <= PMC_STATE_LAST)
1677 return (pmc_state_names[ps]);
1678
1679 errno = EINVAL;
1680 return (NULL);
1681 }
1682
1683 int
pmc_ncpu(void)1684 pmc_ncpu(void)
1685 {
1686 if (pmc_syscall == -1) {
1687 errno = ENXIO;
1688 return (-1);
1689 }
1690
1691 return (cpu_info.pm_ncpu);
1692 }
1693
1694 int
pmc_npmc(int cpu)1695 pmc_npmc(int cpu)
1696 {
1697 if (pmc_syscall == -1) {
1698 errno = ENXIO;
1699 return (-1);
1700 }
1701
1702 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
1703 errno = EINVAL;
1704 return (-1);
1705 }
1706
1707 return (cpu_info.pm_npmc);
1708 }
1709
1710 int
pmc_pmcinfo(int cpu,struct pmc_pmcinfo ** ppmci)1711 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci)
1712 {
1713 int nbytes, npmc;
1714 struct pmc_op_getpmcinfo *pmci;
1715
1716 if ((npmc = pmc_npmc(cpu)) < 0)
1717 return (-1);
1718
1719 nbytes = sizeof(struct pmc_op_getpmcinfo) +
1720 npmc * sizeof(struct pmc_info);
1721
1722 if ((pmci = calloc(1, nbytes)) == NULL)
1723 return (-1);
1724
1725 pmci->pm_cpu = cpu;
1726
1727 if (PMC_CALL(PMC_OP_GETPMCINFO, pmci) < 0) {
1728 free(pmci);
1729 return (-1);
1730 }
1731
1732 /* kernel<->library, library<->userland interfaces are identical */
1733 *ppmci = (struct pmc_pmcinfo *) pmci;
1734 return (0);
1735 }
1736
1737 int
pmc_read(pmc_id_t pmc,pmc_value_t * value)1738 pmc_read(pmc_id_t pmc, pmc_value_t *value)
1739 {
1740 struct pmc_op_pmcrw pmc_read_op;
1741
1742 pmc_read_op.pm_pmcid = pmc;
1743 pmc_read_op.pm_flags = PMC_F_OLDVALUE;
1744 pmc_read_op.pm_value = -1;
1745
1746 if (PMC_CALL(PMC_OP_PMCRW, &pmc_read_op) < 0)
1747 return (-1);
1748
1749 *value = pmc_read_op.pm_value;
1750 return (0);
1751 }
1752
1753 int
pmc_release(pmc_id_t pmc)1754 pmc_release(pmc_id_t pmc)
1755 {
1756 struct pmc_op_simple pmc_release_args;
1757
1758 pmc_release_args.pm_pmcid = pmc;
1759 return (PMC_CALL(PMC_OP_PMCRELEASE, &pmc_release_args));
1760 }
1761
1762 int
pmc_rw(pmc_id_t pmc,pmc_value_t newvalue,pmc_value_t * oldvaluep)1763 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
1764 {
1765 struct pmc_op_pmcrw pmc_rw_op;
1766
1767 pmc_rw_op.pm_pmcid = pmc;
1768 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
1769 pmc_rw_op.pm_value = newvalue;
1770
1771 if (PMC_CALL(PMC_OP_PMCRW, &pmc_rw_op) < 0)
1772 return (-1);
1773
1774 *oldvaluep = pmc_rw_op.pm_value;
1775 return (0);
1776 }
1777
1778 int
pmc_set(pmc_id_t pmc,pmc_value_t value)1779 pmc_set(pmc_id_t pmc, pmc_value_t value)
1780 {
1781 struct pmc_op_pmcsetcount sc;
1782
1783 sc.pm_pmcid = pmc;
1784 sc.pm_count = value;
1785
1786 if (PMC_CALL(PMC_OP_PMCSETCOUNT, &sc) < 0)
1787 return (-1);
1788 return (0);
1789 }
1790
1791 int
pmc_start(pmc_id_t pmc)1792 pmc_start(pmc_id_t pmc)
1793 {
1794 struct pmc_op_simple pmc_start_args;
1795
1796 pmc_start_args.pm_pmcid = pmc;
1797 return (PMC_CALL(PMC_OP_PMCSTART, &pmc_start_args));
1798 }
1799
1800 int
pmc_stop(pmc_id_t pmc)1801 pmc_stop(pmc_id_t pmc)
1802 {
1803 struct pmc_op_simple pmc_stop_args;
1804
1805 pmc_stop_args.pm_pmcid = pmc;
1806 return (PMC_CALL(PMC_OP_PMCSTOP, &pmc_stop_args));
1807 }
1808
1809 int
pmc_width(pmc_id_t pmcid,uint32_t * width)1810 pmc_width(pmc_id_t pmcid, uint32_t *width)
1811 {
1812 unsigned int i;
1813 enum pmc_class cl;
1814
1815 cl = PMC_ID_TO_CLASS(pmcid);
1816 for (i = 0; i < cpu_info.pm_nclass; i++)
1817 if (cpu_info.pm_classes[i].pm_class == cl) {
1818 *width = cpu_info.pm_classes[i].pm_width;
1819 return (0);
1820 }
1821 errno = EINVAL;
1822 return (-1);
1823 }
1824
1825 int
pmc_write(pmc_id_t pmc,pmc_value_t value)1826 pmc_write(pmc_id_t pmc, pmc_value_t value)
1827 {
1828 struct pmc_op_pmcrw pmc_write_op;
1829
1830 pmc_write_op.pm_pmcid = pmc;
1831 pmc_write_op.pm_flags = PMC_F_NEWVALUE;
1832 pmc_write_op.pm_value = value;
1833 return (PMC_CALL(PMC_OP_PMCRW, &pmc_write_op));
1834 }
1835
1836 int
pmc_writelog(uint32_t userdata)1837 pmc_writelog(uint32_t userdata)
1838 {
1839 struct pmc_op_writelog wl;
1840
1841 wl.pm_userdata = userdata;
1842 return (PMC_CALL(PMC_OP_WRITELOG, &wl));
1843 }
1844