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Searched refs:WRITE4 (Results 1 – 25 of 65) sorted by relevance

123

/freebsd-13-stable/sys/arm/freescale/vybrid/
HDvf_dcu4.c230 WRITE4(sc, DCU_INT_STATUS, reg); in dcu_intr()
295 WRITE4(sc, DCU_DISP_SIZE, reg); in dcu_init()
300 WRITE4(sc, DCU_HSYN_PARA, reg); in dcu_init()
305 WRITE4(sc, DCU_VSYN_PARA, reg); in dcu_init()
307 WRITE4(sc, DCU_BGND, 0); in dcu_init()
308 WRITE4(sc, DCU_DIV_RATIO, panel->clk_div); in dcu_init()
311 WRITE4(sc, DCU_SYNPOL, reg); in dcu_init()
317 WRITE4(sc, DCU_THRESHOLD, reg); in dcu_init()
320 WRITE4(sc, DCU_INT_MASK, 0xffffffff); in dcu_init()
324 WRITE4(sc, DCU_CTRLDESCLn_1(i), 0x0); in dcu_init()
[all …]
HDvf_anadig.c141 WRITE4(sc, pll_ctrl, reg); in enable_pll()
149 WRITE4(sc, pll_ctrl, reg); in enable_pll()
169 WRITE4(sc, ANADIG_PLL4_CTRL, reg); in pll4_configure_output()
170 WRITE4(sc, ANADIG_PLL4_NUM, mfn); in pll4_configure_output()
171 WRITE4(sc, ANADIG_PLL4_DENOM, mfd); in pll4_configure_output()
209 WRITE4(sc, ANADIG_REG_3P0, reg); in anadig_attach()
214 WRITE4(sc, USB_MISC(0), reg); in anadig_attach()
218 WRITE4(sc, USB_MISC(1), reg); in anadig_attach()
HDvf_spi.c167 WRITE4(sc, SPI_MCR, reg); in spi_attach()
171 WRITE4(sc, SPI_RSER, reg); in spi_attach()
175 WRITE4(sc, SPI_MCR, reg); in spi_attach()
193 WRITE4(sc, SPI_CTAR0, reg); in spi_attach()
198 WRITE4(sc, SPI_CTAR0, reg); in spi_attach()
223 WRITE4(sc, SPI_PUSHR, wreg); in spi_txrx()
234 WRITE4(sc, SPI_SR, reg); in spi_txrx()
HDvf_adc.c175 WRITE4(sc, ADC_HC0, reg); in adc_enable()
212 WRITE4(sc, ADC_CFG, reg); in adc_attach()
217 WRITE4(sc, ADC_GC, reg); in adc_attach()
222 WRITE4(sc, ADC_HC0, reg); in adc_attach()
/freebsd-13-stable/sys/dev/flash/
HDcqspi.c83 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro
159 WRITE4(sc, CQSPI_IRQSTAT, pending); in cqspi_intr()
260 WRITE4(sc, CQSPI_FLASHCMDADDR, addr); in cqspi_cmd_write_addr()
264 WRITE4(sc, CQSPI_FLASHCMD, reg); in cqspi_cmd_write_addr()
267 WRITE4(sc, CQSPI_FLASHCMD, reg); in cqspi_cmd_write_addr()
282 WRITE4(sc, CQSPI_FLASHCMD, reg); in cqspi_cmd_write()
284 WRITE4(sc, CQSPI_FLASHCMD, reg); in cqspi_cmd_write()
313 WRITE4(sc, CQSPI_FLASHCMD, reg); in cqspi_cmd_read()
316 WRITE4(sc, CQSPI_FLASHCMD, reg); in cqspi_cmd_read()
431 WRITE4(sc, CQSPI_DMAPER, reg); in cqspi_write()
[all …]
/freebsd-13-stable/sys/arm/freescale/imx/
HDimx6_sdma.c65 #define WRITE4(_sc, _reg, _val) \ macro
98 WRITE4(sc, SDMAARM_INTR, pending); in sdma_intr()
116 WRITE4(sc, SDMAARM_HSTART, (1 << i)); in sdma_intr()
141 WRITE4(sc, SDMAARM_HSTART, (1 << chn)); in sdma_start()
153 WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn)); in sdma_stop()
220 WRITE4(sc, SDMAARM_EVTOVR, reg); in sdma_overrides()
228 WRITE4(sc, SDMAARM_HOSTOVR, reg); in sdma_overrides()
236 WRITE4(sc, SDMAARM_DSPOVR, reg); in sdma_overrides()
264 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1); in sdma_configure()
265 WRITE4(sc, SDMAARM_CHNENBL(conf->event), (1 << chn)); in sdma_configure()
[all …]
HDimx_gpt.c51 #define WRITE4(_sc, _r, _v) \ macro
56 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
58 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
192 WRITE4(sc, IMX_GPT_CR, 0); in imx_gpt_attach()
193 WRITE4(sc, IMX_GPT_IR, 0); in imx_gpt_attach()
203 WRITE4(sc, IMX_GPT_CR, ctlreg); in imx_gpt_attach()
213 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); in imx_gpt_attach()
226 WRITE4(sc, IMX_GPT_PR, prescale); in imx_gpt_attach()
229 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); in imx_gpt_attach()
232 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN); in imx_gpt_attach()
[all …]
HDimx_gpio.c71 #define WRITE4(_sc, _r, _v) \ macro
76 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
78 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
310 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << gi->gi_irq)); in gpio_pic_teardown_intr()
382 WRITE4(sc, reg, wrk); in gpio_pic_setup_intr()
384 WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq)); in gpio_pic_setup_intr()
436 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); in gpio_pic_post_filter()
450 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); in gpio_pic_post_ithread()
707 WRITE4(sc, IMX_GPIO_DR_REG, in imx51_gpio_pin_toggle()
730 WRITE4(sc, IMX_GPIO_DR_REG, in imx51_gpio_pin_access_32()
[all …]
HDimx6_audmux.c55 #define WRITE4(_sc, _reg, _val) \ macro
106 WRITE4(sc, AUDMUX_PTCR(audmux_port), reg); in audmux_configure()
110 WRITE4(sc, AUDMUX_PDCR(audmux_port), reg); in audmux_configure()
/freebsd-13-stable/sys/arm/altera/socfpga/
HDsocfpga_a10_manager.c118 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); in fpga_wait_dclk_pulses()
121 WRITE4(sc, FPGAMGR_DCLKCNT, npulses); in fpga_wait_dclk_pulses()
127 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); in fpga_wait_dclk_pulses()
176 WRITE4(sc, IMGCFG_CTRL_02, reg); in fpga_open()
180 WRITE4(sc, IMGCFG_CTRL_02, reg); in fpga_open()
185 WRITE4(sc, IMGCFG_CTRL_01, reg); in fpga_open()
189 WRITE4(sc, IMGCFG_CTRL_00, reg); in fpga_open()
194 WRITE4(sc, IMGCFG_CTRL_01, reg); in fpga_open()
199 WRITE4(sc, IMGCFG_CTRL_02, reg); in fpga_open()
209 WRITE4(sc, IMGCFG_CTRL_00, reg); in fpga_open()
[all …]
HDsocfpga_manager.c225 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open()
230 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open()
235 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open()
246 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open()
254 WRITE4(sc, GPIO_PORTA_EOI, PORTA_EOI_NS); in fpga_open()
259 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open()
271 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); in fpga_wait_dclk_pulses()
274 WRITE4(sc, FPGAMGR_DCLKCNT, npulses); in fpga_wait_dclk_pulses()
280 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); in fpga_wait_dclk_pulses()
311 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_close()
[all …]
/freebsd-13-stable/sys/dev/mmc/host/
HDdwmmc.c91 #define WRITE4(_sc, _reg, _val) \ macro
217 WRITE4(sc, SDMMC_CTRL, reg); in dwmmc_ctrl_reset()
427 WRITE4(sc, SDMMC_RINTSTS, reg); in dwmmc_intr()
442 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI | in dwmmc_intr()
444 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI); in dwmmc_intr()
726 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr); in dwmmc_attach()
729 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK); in dwmmc_attach()
730 WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI | in dwmmc_attach()
736 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); in dwmmc_attach()
737 WRITE4(sc, SDMMC_INTMASK, 0); in dwmmc_attach()
[all …]
HDdwmmc_samsung.c46 #define WRITE4(_sc, _reg, _val) \ macro
102 WRITE4(sc, EMMCP_MPSBEGIN0, 0); in samsung_dwmmc_attach()
103 WRITE4(sc, EMMCP_SEND0, 0); in samsung_dwmmc_attach()
104 WRITE4(sc, EMMCP_CTRL0, (MPSCTRL_SECURE_READ_BIT | in samsung_dwmmc_attach()
/freebsd-13-stable/sys/dev/xilinx/
HDaxi_quad_spi.c67 #define WRITE4(_sc, _reg, _val) \ macro
141 WRITE4(sc, SPI_SRR, SRR_RESET); in spi_attach()
146 WRITE4(sc, SPI_CR, reg); in spi_attach()
147 WRITE4(sc, SPI_DGIER, 0); /* Disable interrupts */ in spi_attach()
150 WRITE4(sc, SPI_CR, reg); in spi_attach()
164 WRITE4(sc, SPI_DTR, out_buf[i]); in spi_txrx()
199 WRITE4(sc, SPI_SSR, reg); in spi_transfer()
210 WRITE4(sc, SPI_SSR, reg); in spi_transfer()
HDif_xae.c71 #define WRITE4(_sc, _reg, _val) \ macro
353 WRITE4(sc, XAE_TC, reg); in xae_stop_locked()
358 WRITE4(sc, XAE_RCW1, reg); in xae_stop_locked()
454 WRITE4(sc, XAE_TC, TC_TX); in xae_init_locked()
457 WRITE4(sc, XAE_RCW1, RCW1_RX); in xae_init_locked()
531 WRITE4(sc, XAE_FFC, reg); in xae_write_maddr()
537 WRITE4(sc, XAE_FFV(0), reg); in xae_write_maddr()
541 WRITE4(sc, XAE_FFV(1), reg); in xae_write_maddr()
562 WRITE4(sc, XAE_FFC, reg); in xae_setup_rxfilter()
566 WRITE4(sc, XAE_FFC, reg); in xae_setup_rxfilter()
[all …]
/freebsd-13-stable/sys/arm64/rockchip/clk/
HDrk_clk_pll.c54 #define WRITE4(_clk, off, val) \ macro
90 WRITE4(clk, sc->gate_offset, val); in rk_clk_pll_set_gate()
151 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_mux()
232 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
235 WRITE4(clk, sc->base_offset + 12, RK3066_CLK_PLL_RESET | in rk3066_clk_pll_set_freq()
247 WRITE4(clk, sc->base_offset, reg); in rk3066_clk_pll_set_freq()
257 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3066_clk_pll_set_freq()
262 WRITE4(clk, sc->base_offset + 0x8, reg); in rk3066_clk_pll_set_freq()
265 WRITE4(clk, sc->base_offset + 12, in rk3066_clk_pll_set_freq()
291 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
[all …]
/freebsd-13-stable/sys/mips/mediatek/
HDmtk_intr_gic.c105 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->gic_res[0], (_reg), (_val)) macro
125 WRITE4(sc, MTK_INTENA, (1u << (irq))); in gic_irq_unmask()
132 WRITE4(sc, MTK_INTDIS, (1u << (irq))); in gic_irq_mask()
188 WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF); in mtk_gic_attach()
191 WRITE4(sc, MTK_INTTRIG, 0x00000000); in mtk_gic_attach()
194 WRITE4(sc, MTK_INTPOL, 0xFFFFFFFF); in mtk_gic_attach()
200 WRITE4(sc, MTK_MAPPIN(i), MTK_PIN_BITS(0)); in mtk_gic_attach()
201 WRITE4(sc, MTK_MAPVPE(i, 0), MTK_VPE_BITS(0)); in mtk_gic_attach()
HDmtk_intr_v1.c103 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) macro
123 WRITE4(sc, MTK_INTENA, (1u << (irq))); in pic_irq_unmask()
130 WRITE4(sc, MTK_INTDIS, (1u << (irq))); in pic_irq_mask()
184 WRITE4(sc, MTK_INTDIS, 0x7FFFFFFF); in mtk_pic_attach()
187 WRITE4(sc, MTK_INTENA, 0x80000000); in mtk_pic_attach()
190 WRITE4(sc, MTK_INTTYPE, 0x00000000); in mtk_pic_attach()
HDmtk_intr_v2.c98 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) macro
118 WRITE4(sc, MTK_INTENA, (1u << (irq))); in pic_irq_unmask()
125 WRITE4(sc, MTK_INTDIS, (1u << (irq))); in pic_irq_mask()
179 WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF); in mtk_pic_attach()
182 WRITE4(sc, MTK_INTENA, 0x00000000); in mtk_pic_attach()
185 WRITE4(sc, MTK_INTTYPE, 0xFFFFFFFF); in mtk_pic_attach()
/freebsd-13-stable/sys/mips/ingenic/
HDjz4780_intr.c90 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) macro
109 WRITE4(sc, JZ_ICMCR0, (1u << irq)); in pic_irq_unmask()
111 WRITE4(sc, JZ_ICMCR1, (1u << (irq - 32))); in pic_irq_unmask()
118 WRITE4(sc, JZ_ICMSR0, (1u << irq)); in pic_irq_mask()
120 WRITE4(sc, JZ_ICMSR1, (1u << (irq - 32))); in pic_irq_mask()
175 WRITE4(sc, JZ_ICMR0, 0xFFFFFFFF); in jz4780_pic_attach()
176 WRITE4(sc, JZ_ICMR1, 0xFFFFFFFF); in jz4780_pic_attach()
HDjz4780_pdma.c136 WRITE4(sc, PDMA_DIRQP, 0); in pdma_intr()
147 WRITE4(sc, PDMA_DCS(chan->index), 0); in pdma_intr()
212 WRITE4(sc, PDMA_DMAC, reg); in pdma_attach()
214 WRITE4(sc, PDMA_DMACP, 0); in pdma_attach()
239 WRITE4(sc, PDMA_DCS(chan->index), DCS_DES8); in chan_start()
240 WRITE4(sc, PDMA_DDA(chan->index), in chan_start()
243 WRITE4(sc, PDMA_DDS, (1 << chan->index)); in chan_start()
246 WRITE4(sc, PDMA_DCS(chan->index), (DCS_DES8 | DCS_CTE)); in chan_start()
256 WRITE4(sc, PDMA_DCS(chan->index), 0); in chan_stop()
/freebsd-13-stable/sys/dev/dwc/
HDif_dwc.c81 #define WRITE4(_sc, _reg, _val) \ macro
246 WRITE4(sc, GMII_ADDRESS, mii); in dwc_miibus_read_reg()
273 WRITE4(sc, GMII_DATA, val); in dwc_miibus_write_reg()
274 WRITE4(sc, GMII_ADDRESS, mii); in dwc_miibus_write_reg()
335 WRITE4(sc, MAC_CONFIGURATION, reg); in dwc_miibus_statchg()
344 WRITE4(sc, FLOW_CONTROL, reg); in dwc_miibus_statchg()
480 WRITE4(sc, MAC_ADDRESS_LOW(0), lo); in dwc_setup_rxfilter()
481 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); in dwc_setup_rxfilter()
482 WRITE4(sc, MAC_FRAME_FILTER, ffval); in dwc_setup_rxfilter()
484 WRITE4(sc, GMAC_MAC_HTLOW, ctx.hash[0]); in dwc_setup_rxfilter()
[all …]
/freebsd-13-stable/sys/dev/altera/pio/
HDpio.c61 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro
126 WRITE4(sc, PIO_OUTSET, bit); in pio_set()
128 WRITE4(sc, PIO_OUTCLR, bit); in pio_set()
140 WRITE4(sc, PIO_INT_MASK, mask); in pio_configure()
141 WRITE4(sc, PIO_DIR, dir); in pio_configure()
/freebsd-13-stable/sys/arm/allwinner/clkng/
HDaw_clk_nkmp.c63 #define WRITE4(_clk, off, val) \ macro
112 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_gate()
133 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_mux()
208 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
215 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
223 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
229 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
236 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale()
296 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq()
304 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq()
/freebsd-13-stable/sys/arm/ti/clk/
HDti_clk_clkctrl.c71 #define WRITE4(_clk, off, val) \ macro
115 WRITE4(clk, sc->register_offset, val); in ti_clkctrl_set_gdbclk_gate()
154 WRITE4(clk, sc->register_offset, MODULEMODE_ENABLE); in ti_clkctrl_set_gate()
156 WRITE4(clk, sc->register_offset, MODULEMODE_DISABLE); in ti_clkctrl_set_gate()

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