Searched refs:WR2 (Results 1 – 6 of 6) sorted by relevance
| /freebsd-13-stable/sys/arm/freescale/imx/ |
| HD | imx_wdog.c | 95 WR2(struct imx_wdog_softc *sc, bus_size_t offs, uint16_t val) in WR2() function
115 WR2(sc, WDOG_CR_REG, reg | WDOG_CR_WDE); in imx_wdog_enable()
118 WR2(sc, WDOG_SR_REG, WDOG_SR_STEP1); in imx_wdog_enable()
119 WR2(sc, WDOG_SR_REG, WDOG_SR_STEP2); in imx_wdog_enable()
124 WR2(sc, WDOG_MCR_REG, reg & ~WDOG_MCR_PDE); in imx_wdog_enable()
207 WR2(sc, WDOG_CR_REG, WDOG_CR_WDT | RD2(sc, WDOG_CR_REG)); in imx_wdog_attach()
211 WR2(sc, WDOG_ICR_REG, WDOG_ICR_WIE); /* Enable, count is 0. */ in imx_wdog_attach()
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| /freebsd-13-stable/sys/dev/sdhci/ |
| HD | sdhci.c | 88 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) macro
353 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); in sdhci_set_clock()
376 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); in sdhci_set_clock()
415 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
418 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
434 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
1236 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1303 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1318 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1476 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
[all …]
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| /freebsd-13-stable/sys/dev/ffec/ |
| HD | if_ffec.c | 218 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) in WR2() function
294 WR2(sc, FEC_MIIGSK_ENR, 0); in ffec_miigasket_setup()
298 WR2(sc, FEC_MIIGSK_CFGR, ifmode); in ffec_miigasket_setup()
300 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); in ffec_miigasket_setup()
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| /freebsd-13-stable/sys/arm/broadcom/bcm2835/ |
| HD | bcm2835_sdhost.c | 272 WR2(struct bcm_sdhost_softc *sc, bus_size_t off, uint16_t val) in WR2() function
1096 WR2(sc, HC_BLOCKSIZE, val); in bcm_sdhost_write_2()
1103 WR2(sc, HC_BLOCKCOUNT, val); in bcm_sdhost_write_2()
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| HD | HexagonDisassembler.cpp | 628 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4, in DecodeHvxWRRegisterClass()
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| HD | HexagonRegisterInfo.td | 254 def WR2 : Rd< 5, "v4:5", [V4, V5, VFR2]>, DwarfRegNum<[163]>;
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