Searched refs:VECREDUCE_FADD (Results 1 – 14 of 14) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 1393 VECREDUCE_FADD, enumerator
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAGDumper.cpp | 529 case ISD::VECREDUCE_FADD: return "vecreduce_fadd"; in getOperationName()
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| HD | LegalizeVectorOps.cpp | 489 case ISD::VECREDUCE_FADD: in LegalizeOp()
1101 case ISD::VECREDUCE_FADD: in Expand()
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| HD | LegalizeFloatTypes.cpp | 162 case ISD::VECREDUCE_FADD: in SoftenFloatResult()
2661 case ISD::VECREDUCE_FADD: in PromoteFloatResult()
3097 case ISD::VECREDUCE_FADD: in SoftPromoteHalfResult()
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| HD | LegalizeVectorTypes.cpp | 794 case ISD::VECREDUCE_FADD: in ScalarizeVectorOperand()
3223 case ISD::VECREDUCE_FADD: in SplitVectorOperand()
6434 case ISD::VECREDUCE_FADD: in WidenVectorOperand()
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| HD | LegalizeDAG.cpp | 1198 case ISD::VECREDUCE_FADD: in LegalizeOp()
4304 case ISD::VECREDUCE_FADD: in ExpandNode()
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| HD | SelectionDAGBuilder.cpp | 10719 DAG.getNode(ISD::VECREDUCE_FADD, dl, VT, Op2, SDFlags), in visitVectorReduce()
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| HD | SelectionDAG.cpp | 429 case ISD::VECREDUCE_FADD: in getVecReduceBaseOpcode()
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| HD | DAGCombiner.cpp | 1975 case ISD::VECREDUCE_FADD: in visit()
16712 if (SDValue SD = reassociateReduction(ISD::VECREDUCE_FADD, ISD::FADD, DL, in visitFADD()
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| HD | TargetLoweringBase.cpp | 785 {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD, in initActions()
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Target/ |
| HD | TargetSelectionDAG.td | 495 def vecreduce_fadd : SDNode<"ISD::VECREDUCE_FADD", SDTFPVecReduce>;
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 1300 setOperationAction(ISD::VECREDUCE_FADD, VT, Legal); in AArch64TargetLowering()
1613 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); in AArch64TargetLowering()
1745 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); in AArch64TargetLowering()
2108 setOperationAction(ISD::VECREDUCE_FADD, VT, Default); in addTypeForFixedLengthSVE()
6960 case ISD::VECREDUCE_FADD: in LowerOperation()
15278 Op.getOpcode() == ISD::VECREDUCE_FADD || in LowerVECREDUCE()
15305 case ISD::VECREDUCE_FADD: in LowerVECREDUCE()
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| HD | ARMISelLowering.cpp | 368 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); in addMVEVectorTypes()
393 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom); in addMVEVectorTypes()
397 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom); in addMVEVectorTypes()
10299 case ISD::VECREDUCE_FADD: BaseOpcode = ISD::FADD; break; in LowerVecReduce()
10665 case ISD::VECREDUCE_FADD: in LowerOperation()
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| HD | RISCVISelLowering.cpp | 727 ISD::VECREDUCE_FADD, ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_FMIN, in RISCVTargetLowering()
6787 case ISD::VECREDUCE_FADD: in LowerOperation()
9893 case ISD::VECREDUCE_FADD: { in getRVVFPReductionOpAndOperands()
12936 return ISD::VECREDUCE_FADD; in getVecReduceOpcode()
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