1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2009 Oleksandr Tymoshenko
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29
30 #ifndef _AR71XX_REG_H_
31 #define _AR71XX_REG_H_
32
33 /* PCI region */
34 #define AR71XX_PCI_MEM_BASE 0x10000000
35 /*
36 * PCI mem windows is 0x08000000 bytes long but we exclude control
37 * region from the resource manager
38 */
39 #define AR71XX_PCI_MEM_SIZE 0x07000000
40 #define AR71XX_PCI_IRQ_START 0
41 #define AR71XX_PCI_IRQ_END 2
42 #define AR71XX_PCI_NIRQS 3
43 /*
44 * PCI devices slots are starting from this number
45 */
46 #define AR71XX_PCI_BASE_SLOT 17
47
48 /* PCI config registers */
49 #define AR71XX_PCI_LCONF_CMD 0x17010000
50 #define PCI_LCONF_CMD_READ 0x00000000
51 #define PCI_LCONF_CMD_WRITE 0x00010000
52 #define AR71XX_PCI_LCONF_WRITE_DATA 0x17010004
53 #define AR71XX_PCI_LCONF_READ_DATA 0x17010008
54 #define AR71XX_PCI_CONF_ADDR 0x1701000C
55 #define AR71XX_PCI_CONF_CMD 0x17010010
56 #define PCI_CONF_CMD_READ 0x0000000A
57 #define PCI_CONF_CMD_WRITE 0x0000000B
58 #define AR71XX_PCI_CONF_WRITE_DATA 0x17010014
59 #define AR71XX_PCI_CONF_READ_DATA 0x17010018
60 #define AR71XX_PCI_ERROR 0x1701001C
61 #define AR71XX_PCI_ERROR_ADDR 0x17010020
62 #define AR71XX_PCI_AHB_ERROR 0x17010024
63 #define AR71XX_PCI_AHB_ERROR_ADDR 0x17010028
64
65 /* APB region */
66 /*
67 * Size is not really true actual APB window size is
68 * 0x01000000 but it should handle OHCI memory as well
69 * because this controller's interrupt is routed through
70 * APB.
71 */
72 #define AR71XX_APB_BASE 0x18000000
73 #define AR71XX_APB_SIZE 0x06000000
74
75 /* DDR registers */
76 #define AR71XX_DDR_CONFIG 0x18000000
77 #define AR71XX_DDR_CONFIG2 0x18000004
78 #define AR71XX_DDR_MODE_REGISTER 0x18000008
79 #define AR71XX_DDR_EXT_MODE_REGISTER 0x1800000C
80 #define AR71XX_DDR_CONTROL 0x18000010
81 #define AR71XX_DDR_REFRESH 0x18000014
82 #define AR71XX_DDR_RD_DATA_THIS_CYCLE 0x18000018
83 #define AR71XX_TAP_CONTROL0 0x1800001C
84 #define AR71XX_TAP_CONTROL1 0x18000020
85 #define AR71XX_TAP_CONTROL2 0x18000024
86 #define AR71XX_TAP_CONTROL3 0x18000028
87 #define AR71XX_PCI_WINDOW0 0x1800007C
88 #define AR71XX_PCI_WINDOW1 0x18000080
89 #define AR71XX_PCI_WINDOW2 0x18000084
90 #define AR71XX_PCI_WINDOW3 0x18000088
91 #define AR71XX_PCI_WINDOW4 0x1800008C
92 #define AR71XX_PCI_WINDOW5 0x18000090
93 #define AR71XX_PCI_WINDOW6 0x18000094
94 #define AR71XX_PCI_WINDOW7 0x18000098
95 #define AR71XX_WB_FLUSH_GE0 0x1800009C
96 #define AR71XX_WB_FLUSH_GE1 0x180000A0
97 #define AR71XX_WB_FLUSH_USB 0x180000A4
98 #define AR71XX_WB_FLUSH_PCI 0x180000A8
99
100 /*
101 * Values for PCI_WINDOW_X registers
102 */
103 #define PCI_WINDOW0_ADDR 0x10000000
104 #define PCI_WINDOW1_ADDR 0x11000000
105 #define PCI_WINDOW2_ADDR 0x12000000
106 #define PCI_WINDOW3_ADDR 0x13000000
107 #define PCI_WINDOW4_ADDR 0x14000000
108 #define PCI_WINDOW5_ADDR 0x15000000
109 #define PCI_WINDOW6_ADDR 0x16000000
110 #define PCI_WINDOW7_ADDR 0x17000000
111 /* This value enables acces to PCI config registers */
112 #define PCI_WINDOW7_CONF_ADDR 0x07000000
113
114 #define AR71XX_UART_ADDR 0x18020000
115 #define AR71XX_UART_THR 0x0
116 #define AR71XX_UART_LSR 0x14
117 #define AR71XX_UART_LSR_THRE (1 << 5)
118 #define AR71XX_UART_LSR_TEMT (1 << 6)
119
120 #define AR71XX_USB_CTRL_FLADJ 0x18030000
121 #define USB_CTRL_FLADJ_HOST_SHIFT 12
122 #define USB_CTRL_FLADJ_A5_SHIFT 10
123 #define USB_CTRL_FLADJ_A4_SHIFT 8
124 #define USB_CTRL_FLADJ_A3_SHIFT 6
125 #define USB_CTRL_FLADJ_A2_SHIFT 4
126 #define USB_CTRL_FLADJ_A1_SHIFT 2
127 #define USB_CTRL_FLADJ_A0_SHIFT 0
128 #define AR71XX_USB_CTRL_CONFIG 0x18030004
129 #define USB_CTRL_CONFIG_OHCI_DES_SWAP (1 << 19)
130 #define USB_CTRL_CONFIG_OHCI_BUF_SWAP (1 << 18)
131 #define USB_CTRL_CONFIG_EHCI_DES_SWAP (1 << 17)
132 #define USB_CTRL_CONFIG_EHCI_BUF_SWAP (1 << 16)
133 #define USB_CTRL_CONFIG_DISABLE_XTL (1 << 13)
134 #define USB_CTRL_CONFIG_OVERRIDE_XTL (1 << 12)
135 #define USB_CTRL_CONFIG_CLK_SEL_SHIFT 4
136 #define USB_CTRL_CONFIG_CLK_SEL_MASK 3
137 #define USB_CTRL_CONFIG_CLK_SEL_12 0
138 #define USB_CTRL_CONFIG_CLK_SEL_24 1
139 #define USB_CTRL_CONFIG_CLK_SEL_48 2
140 #define USB_CTRL_CONFIG_OVER_CURRENT_AS_GPIO (1 << 8)
141 #define USB_CTRL_CONFIG_SS_SIMULATION_MODE (1 << 2)
142 #define USB_CTRL_CONFIG_RESUME_UTMI_PLS_DIS (1 << 1)
143 #define USB_CTRL_CONFIG_UTMI_BACKWARD_ENB (1 << 0)
144
145 #define AR71XX_GPIO_BASE 0x18040000
146 #define AR71XX_GPIO_OE 0x00
147 #define AR71XX_GPIO_IN 0x04
148 #define AR71XX_GPIO_OUT 0x08
149 #define AR71XX_GPIO_SET 0x0c
150 #define AR71XX_GPIO_CLEAR 0x10
151 #define AR71XX_GPIO_INT 0x14
152 #define AR71XX_GPIO_INT_TYPE 0x18
153 #define AR71XX_GPIO_INT_POLARITY 0x1c
154 #define AR71XX_GPIO_INT_PENDING 0x20
155 #define AR71XX_GPIO_INT_MASK 0x24
156 #define AR71XX_GPIO_FUNCTION 0x28
157 #define GPIO_FUNC_STEREO_EN (1 << 17)
158 #define GPIO_FUNC_SLIC_EN (1 << 16)
159 #define GPIO_FUNC_SPI_CS2_EN (1 << 13)
160 /* CS2 is shared with GPIO_1 */
161 #define GPIO_FUNC_SPI_CS1_EN (1 << 12)
162 /* CS1 is shared with GPIO_0 */
163 #define GPIO_FUNC_UART_EN (1 << 8)
164 #define GPIO_FUNC_USB_OC_EN (1 << 4)
165 #define GPIO_FUNC_USB_CLK_EN (0)
166
167 #define AR71XX_BASE_FREQ 40000000
168 #define AR71XX_PLL_CPU_BASE 0x18050000
169 #define AR71XX_PLL_CPU_CONFIG 0x18050000
170 #define PLL_SW_UPDATE (1U << 31)
171 #define PLL_LOCKED (1 << 30)
172 #define PLL_AHB_DIV_SHIFT 20
173 #define PLL_AHB_DIV_MASK 7
174 #define PLL_DDR_DIV_SEL_SHIFT 18
175 #define PLL_DDR_DIV_SEL_MASK 3
176 #define PLL_CPU_DIV_SEL_SHIFT 16
177 #define PLL_CPU_DIV_SEL_MASK 3
178 #define PLL_LOOP_BW_SHIFT 12
179 #define PLL_LOOP_BW_MASK 0xf
180 #define PLL_DIV_IN_SHIFT 10
181 #define PLL_DIV_IN_MASK 3
182 #define PLL_DIV_OUT_SHIFT 8
183 #define PLL_DIV_OUT_MASK 3
184 #define PLL_FB_SHIFT 3
185 #define PLL_FB_MASK 0x1f
186 #define PLL_BYPASS (1 << 1)
187 #define PLL_POWER_DOWN (1 << 0)
188 #define AR71XX_PLL_SEC_CONFIG 0x18050004
189 #define AR71XX_PLL_ETH0_SHIFT 17
190 #define AR71XX_PLL_ETH1_SHIFT 19
191 #define AR71XX_PLL_CPU_CLK_CTRL 0x18050008
192 #define AR71XX_PLL_ETH_INT0_CLK 0x18050010
193 #define AR71XX_PLL_ETH_INT1_CLK 0x18050014
194 #define XPLL_ETH_INT_CLK_10 0x00991099
195 #define XPLL_ETH_INT_CLK_100 0x00441011
196 #define XPLL_ETH_INT_CLK_1000 0x13110000
197 #define XPLL_ETH_INT_CLK_1000_GMII 0x14110000
198 #define PLL_ETH_INT_CLK_10 0x00991099
199 #define PLL_ETH_INT_CLK_100 0x00001099
200 #define PLL_ETH_INT_CLK_1000 0x00110000
201 #define AR71XX_PLL_ETH_EXT_CLK 0x18050018
202 #define AR71XX_PLL_PCI_CLK 0x1805001C
203
204 /* Reset block */
205 #define AR71XX_RST_BLOCK_BASE 0x18060000
206
207 #define AR71XX_RST_WDOG_CONTROL 0x18060008
208 #define RST_WDOG_LAST (1U << 31)
209 #define RST_WDOG_ACTION_MASK 3
210 #define RST_WDOG_ACTION_RESET 3
211 #define RST_WDOG_ACTION_NMI 2
212 #define RST_WDOG_ACTION_GP_INTR 1
213 #define RST_WDOG_ACTION_NOACTION 0
214
215 #define AR71XX_RST_WDOG_TIMER 0x1806000C
216 /*
217 * APB interrupt status and mask register and interrupt bit numbers for
218 */
219 #define AR71XX_MISC_INTR_STATUS 0x18060010
220 #define AR71XX_MISC_INTR_MASK 0x18060014
221 #define MISC_INTR_TIMER 0
222 #define MISC_INTR_ERROR 1
223 #define MISC_INTR_GPIO 2
224 #define MISC_INTR_UART 3
225 #define MISC_INTR_WATCHDOG 4
226 #define MISC_INTR_PERF 5
227 #define MISC_INTR_OHCI 6
228 #define MISC_INTR_DMA 7
229
230 #define AR71XX_PCI_INTR_STATUS 0x18060018
231 #define AR71XX_PCI_INTR_MASK 0x1806001C
232 #define PCI_INTR_CORE (1 << 4)
233
234 #define AR71XX_RST_RESET 0x18060024
235 #define RST_RESET_FULL_CHIP (1 << 24) /* Same as pulling
236 the reset pin */
237 #define RST_RESET_CPU_COLD (1 << 20) /* Cold reset */
238 #define RST_RESET_GE1_MAC (1 << 13)
239 #define RST_RESET_GE1_PHY (1 << 12)
240 #define RST_RESET_GE0_MAC (1 << 9)
241 #define RST_RESET_GE0_PHY (1 << 8)
242 #define RST_RESET_USB_OHCI_DLL (1 << 6)
243 #define RST_RESET_USB_HOST (1 << 5)
244 #define RST_RESET_USB_PHY (1 << 4)
245 #define RST_RESET_PCI_BUS (1 << 1)
246 #define RST_RESET_PCI_CORE (1 << 0)
247
248 /* Chipset revision details */
249 #define AR71XX_RST_RESET_REG_REV_ID 0x18060090
250 #define REV_ID_MAJOR_MASK 0xfff0
251 #define REV_ID_MAJOR_AR71XX 0x00a0
252 #define REV_ID_MAJOR_AR913X 0x00b0
253 #define REV_ID_MAJOR_AR7240 0x00c0
254 #define REV_ID_MAJOR_AR7241 0x0100
255 #define REV_ID_MAJOR_AR7242 0x1100
256
257 /* AR71XX chipset revision details */
258 #define AR71XX_REV_ID_MINOR_MASK 0x3
259 #define AR71XX_REV_ID_MINOR_AR7130 0x0
260 #define AR71XX_REV_ID_MINOR_AR7141 0x1
261 #define AR71XX_REV_ID_MINOR_AR7161 0x2
262 #define AR71XX_REV_ID_REVISION_MASK 0x3
263 #define AR71XX_REV_ID_REVISION_SHIFT 2
264
265 /* AR724X chipset revision details */
266 #define AR724X_REV_ID_REVISION_MASK 0x3
267
268 /* AR91XX chipset revision details */
269 #define AR91XX_REV_ID_MINOR_MASK 0x3
270 #define AR91XX_REV_ID_MINOR_AR9130 0x0
271 #define AR91XX_REV_ID_MINOR_AR9132 0x1
272 #define AR91XX_REV_ID_REVISION_MASK 0x3
273 #define AR91XX_REV_ID_REVISION_SHIFT 2
274
275 typedef enum {
276 AR71XX_MII_MODE_NONE = 0,
277 AR71XX_MII_MODE_GMII,
278 AR71XX_MII_MODE_MII,
279 AR71XX_MII_MODE_RGMII,
280 AR71XX_MII_MODE_RMII,
281 AR71XX_MII_MODE_SGMII /* not hardware defined, though! */
282 } ar71xx_mii_mode;
283
284 /*
285 * AR71xx MII control region
286 */
287 #define AR71XX_MII0_CTRL 0x18070000
288 #define MII_CTRL_SPEED_SHIFT 4
289 #define MII_CTRL_SPEED_MASK 3
290 #define MII_CTRL_SPEED_10 0
291 #define MII_CTRL_SPEED_100 1
292 #define MII_CTRL_SPEED_1000 2
293 #define MII_CTRL_IF_MASK 3
294 #define MII_CTRL_IF_SHIFT 0
295 #define MII0_CTRL_IF_GMII 0
296 #define MII0_CTRL_IF_MII 1
297 #define MII0_CTRL_IF_RGMII 2
298 #define MII0_CTRL_IF_RMII 3
299
300 #define AR71XX_MII1_CTRL 0x18070004
301
302 #define MII1_CTRL_IF_RGMII 0
303 #define MII1_CTRL_IF_RMII 1
304
305 /*
306 * GigE adapters region
307 */
308 #define AR71XX_MAC0_BASE 0x19000000
309 #define AR71XX_MAC1_BASE 0x1A000000
310
311 #define AR71XX_MAC_CFG1 0x00
312 #define MAC_CFG1_SOFT_RESET (1U << 31)
313 #define MAC_CFG1_SIMUL_RESET (1 << 30)
314 #define MAC_CFG1_MAC_RX_BLOCK_RESET (1 << 19)
315 #define MAC_CFG1_MAC_TX_BLOCK_RESET (1 << 18)
316 #define MAC_CFG1_RX_FUNC_RESET (1 << 17)
317 #define MAC_CFG1_TX_FUNC_RESET (1 << 16)
318 #define MAC_CFG1_LOOPBACK (1 << 8)
319 #define MAC_CFG1_RXFLOW_CTRL (1 << 5)
320 #define MAC_CFG1_TXFLOW_CTRL (1 << 4)
321 #define MAC_CFG1_SYNC_RX (1 << 3)
322 #define MAC_CFG1_RX_ENABLE (1 << 2)
323 #define MAC_CFG1_SYNC_TX (1 << 1)
324 #define MAC_CFG1_TX_ENABLE (1 << 0)
325 #define AR71XX_MAC_CFG2 0x04
326 #define MAC_CFG2_PREAMBLE_LEN_MASK 0xf
327 #define MAC_CFG2_PREAMBLE_LEN_SHIFT 12
328 #define MAC_CFG2_IFACE_MODE_1000 (2 << 8)
329 #define MAC_CFG2_IFACE_MODE_10_100 (1 << 8)
330 #define MAC_CFG2_IFACE_MODE_SHIFT 8
331 #define MAC_CFG2_IFACE_MODE_MASK 3
332 #define MAC_CFG2_HUGE_FRAME (1 << 5)
333 #define MAC_CFG2_LENGTH_FIELD (1 << 4)
334 #define MAC_CFG2_ENABLE_PADCRC (1 << 2)
335 #define MAC_CFG2_ENABLE_CRC (1 << 1)
336 #define MAC_CFG2_FULL_DUPLEX (1 << 0)
337 #define AR71XX_MAC_IFG 0x08
338 #define AR71XX_MAC_HDUPLEX 0x0C
339 #define AR71XX_MAC_MAX_FRAME_LEN 0x10
340 #define AR71XX_MAC_MII_CFG 0x20
341 #define MAC_MII_CFG_RESET (1U << 31)
342 #define MAC_MII_CFG_SCAN_AUTO_INC (1 << 5)
343 #define MAC_MII_CFG_PREAMBLE_SUP (1 << 4)
344 #define MAC_MII_CFG_CLOCK_SELECT_MASK 0x7
345 #define MAC_MII_CFG_CLOCK_SELECT_MASK_AR933X 0xf
346 #define MAC_MII_CFG_CLOCK_DIV_4 0
347 #define MAC_MII_CFG_CLOCK_DIV_6 2
348 #define MAC_MII_CFG_CLOCK_DIV_8 3
349 #define MAC_MII_CFG_CLOCK_DIV_10 4
350 #define MAC_MII_CFG_CLOCK_DIV_14 5
351 #define MAC_MII_CFG_CLOCK_DIV_20 6
352 #define MAC_MII_CFG_CLOCK_DIV_28 7
353
354 /* .. and the AR933x/AR934x extensions */
355 #define MAC_MII_CFG_CLOCK_DIV_34 8
356 #define MAC_MII_CFG_CLOCK_DIV_42 9
357 #define MAC_MII_CFG_CLOCK_DIV_50 10
358 #define MAC_MII_CFG_CLOCK_DIV_58 11
359 #define MAC_MII_CFG_CLOCK_DIV_66 12
360 #define MAC_MII_CFG_CLOCK_DIV_74 13
361 #define MAC_MII_CFG_CLOCK_DIV_82 14
362 #define MAC_MII_CFG_CLOCK_DIV_98 15
363
364 #define AR71XX_MAC_MII_CMD 0x24
365 #define MAC_MII_CMD_SCAN_CYCLE (1 << 1)
366 #define MAC_MII_CMD_READ 1
367 #define MAC_MII_CMD_WRITE 0
368 #define AR71XX_MAC_MII_ADDR 0x28
369 #define MAC_MII_PHY_ADDR_SHIFT 8
370 #define MAC_MII_PHY_ADDR_MASK 0xff
371 #define MAC_MII_REG_MASK 0x1f
372 #define AR71XX_MAC_MII_CONTROL 0x2C
373 #define MAC_MII_CONTROL_MASK 0xffff
374 #define AR71XX_MAC_MII_STATUS 0x30
375 #define MAC_MII_STATUS_MASK 0xffff
376 #define AR71XX_MAC_MII_INDICATOR 0x34
377 #define MAC_MII_INDICATOR_NOT_VALID (1 << 2)
378 #define MAC_MII_INDICATOR_SCANNING (1 << 1)
379 #define MAC_MII_INDICATOR_BUSY (1 << 0)
380 #define AR71XX_MAC_IFCONTROL 0x38
381 #define MAC_IFCONTROL_SPEED (1 << 16)
382 #define AR71XX_MAC_STA_ADDR1 0x40
383 #define AR71XX_MAC_STA_ADDR2 0x44
384 #define AR71XX_MAC_FIFO_CFG0 0x48
385 #define FIFO_CFG0_TX_FABRIC (1 << 4)
386 #define FIFO_CFG0_TX_SYSTEM (1 << 3)
387 #define FIFO_CFG0_RX_FABRIC (1 << 2)
388 #define FIFO_CFG0_RX_SYSTEM (1 << 1)
389 #define FIFO_CFG0_WATERMARK (1 << 0)
390 #define FIFO_CFG0_ALL ((1 << 5) - 1)
391 #define FIFO_CFG0_ENABLE_SHIFT 8
392 #define AR71XX_MAC_FIFO_CFG1 0x4C
393 #define AR71XX_MAC_FIFO_CFG2 0x50
394 #define AR71XX_MAC_FIFO_TX_THRESHOLD 0x54
395 #define AR71XX_MAC_FIFO_RX_FILTMATCH 0x58
396 /*
397 * These flags applicable both to AR71XX_MAC_FIFO_RX_FILTMASK and
398 * to AR71XX_MAC_FIFO_RX_FILTMATCH
399 */
400 #define FIFO_RX_MATCH_UNICAST (1 << 17)
401 #define FIFO_RX_MATCH_TRUNC_FRAME (1 << 16)
402 #define FIFO_RX_MATCH_VLAN_TAG (1 << 15)
403 #define FIFO_RX_MATCH_UNSUP_OPCODE (1 << 14)
404 #define FIFO_RX_MATCH_PAUSE_FRAME (1 << 13)
405 #define FIFO_RX_MATCH_CTRL_FRAME (1 << 12)
406 #define FIFO_RX_MATCH_LONG_EVENT (1 << 11)
407 #define FIFO_RX_MATCH_DRIBBLE_NIBBLE (1 << 10)
408 #define FIFO_RX_MATCH_BCAST (1 << 9)
409 #define FIFO_RX_MATCH_MCAST (1 << 8)
410 #define FIFO_RX_MATCH_OK (1 << 7)
411 #define FIFO_RX_MATCH_OORANGE (1 << 6)
412 #define FIFO_RX_MATCH_LEN_MSMTCH (1 << 5)
413 #define FIFO_RX_MATCH_CRC_ERROR (1 << 4)
414 #define FIFO_RX_MATCH_CODE_ERROR (1 << 3)
415 #define FIFO_RX_MATCH_FALSE_CARRIER (1 << 2)
416 #define FIFO_RX_MATCH_RX_DV_EVENT (1 << 1)
417 #define FIFO_RX_MATCH_DROP_EVENT (1 << 0)
418 /*
419 * Exclude unicast and truncated frames from matching
420 */
421 #define FIFO_RX_FILTMATCH_DEFAULT \
422 (FIFO_RX_MATCH_VLAN_TAG | \
423 FIFO_RX_MATCH_UNSUP_OPCODE | \
424 FIFO_RX_MATCH_PAUSE_FRAME | \
425 FIFO_RX_MATCH_CTRL_FRAME | \
426 FIFO_RX_MATCH_LONG_EVENT | \
427 FIFO_RX_MATCH_DRIBBLE_NIBBLE | \
428 FIFO_RX_MATCH_BCAST | \
429 FIFO_RX_MATCH_MCAST | \
430 FIFO_RX_MATCH_OK | \
431 FIFO_RX_MATCH_OORANGE | \
432 FIFO_RX_MATCH_LEN_MSMTCH | \
433 FIFO_RX_MATCH_CRC_ERROR | \
434 FIFO_RX_MATCH_CODE_ERROR | \
435 FIFO_RX_MATCH_FALSE_CARRIER | \
436 FIFO_RX_MATCH_RX_DV_EVENT | \
437 FIFO_RX_MATCH_DROP_EVENT)
438 #define AR71XX_MAC_FIFO_RX_FILTMASK 0x5C
439 #define FIFO_RX_MASK_BYTE_MODE (1 << 19)
440 #define FIFO_RX_MASK_NO_SHORT_FRAME (1 << 18)
441 #define FIFO_RX_MASK_BIT17 (1 << 17)
442 #define FIFO_RX_MASK_BIT16 (1 << 16)
443 #define FIFO_RX_MASK_TRUNC_FRAME (1 << 15)
444 #define FIFO_RX_MASK_LONG_EVENT (1 << 14)
445 #define FIFO_RX_MASK_VLAN_TAG (1 << 13)
446 #define FIFO_RX_MASK_UNSUP_OPCODE (1 << 12)
447 #define FIFO_RX_MASK_PAUSE_FRAME (1 << 11)
448 #define FIFO_RX_MASK_CTRL_FRAME (1 << 10)
449 #define FIFO_RX_MASK_DRIBBLE_NIBBLE (1 << 9)
450 #define FIFO_RX_MASK_BCAST (1 << 8)
451 #define FIFO_RX_MASK_MCAST (1 << 7)
452 #define FIFO_RX_MASK_OK (1 << 6)
453 #define FIFO_RX_MASK_OORANGE (1 << 5)
454 #define FIFO_RX_MASK_LEN_MSMTCH (1 << 4)
455 #define FIFO_RX_MASK_CODE_ERROR (1 << 3)
456 #define FIFO_RX_MASK_FALSE_CARRIER (1 << 2)
457 #define FIFO_RX_MASK_RX_DV_EVENT (1 << 1)
458 #define FIFO_RX_MASK_DROP_EVENT (1 << 0)
459
460 /*
461 * Len. mismatch, unsup. opcode and short frmae bits excluded
462 */
463 #define FIFO_RX_FILTMASK_DEFAULT \
464 (FIFO_RX_MASK_NO_SHORT_FRAME | \
465 FIFO_RX_MASK_BIT17 | \
466 FIFO_RX_MASK_BIT16 | \
467 FIFO_RX_MASK_TRUNC_FRAME | \
468 FIFO_RX_MASK_LONG_EVENT | \
469 FIFO_RX_MASK_VLAN_TAG | \
470 FIFO_RX_MASK_PAUSE_FRAME | \
471 FIFO_RX_MASK_CTRL_FRAME | \
472 FIFO_RX_MASK_DRIBBLE_NIBBLE | \
473 FIFO_RX_MASK_BCAST | \
474 FIFO_RX_MASK_MCAST | \
475 FIFO_RX_MASK_OK | \
476 FIFO_RX_MASK_OORANGE | \
477 FIFO_RX_MASK_CODE_ERROR | \
478 FIFO_RX_MASK_FALSE_CARRIER | \
479 FIFO_RX_MASK_RX_DV_EVENT | \
480 FIFO_RX_MASK_DROP_EVENT)
481
482 #define AR71XX_MAC_FIFO_RAM0 0x60
483 #define AR71XX_MAC_FIFO_RAM1 0x64
484 #define AR71XX_MAC_FIFO_RAM2 0x68
485 #define AR71XX_MAC_FIFO_RAM3 0x6C
486 #define AR71XX_MAC_FIFO_RAM4 0x70
487 #define AR71XX_MAC_FIFO_RAM5 0x74
488 #define AR71XX_MAC_FIFO_RAM6 0x78
489 #define AR71XX_DMA_TX_CONTROL 0x180
490 #define DMA_TX_CONTROL_EN (1 << 0)
491 #define AR71XX_DMA_TX_DESC 0x184
492 #define AR71XX_DMA_TX_STATUS 0x188
493 #define DMA_TX_STATUS_PCOUNT_MASK 0xff
494 #define DMA_TX_STATUS_PCOUNT_SHIFT 16
495 #define DMA_TX_STATUS_BUS_ERROR (1 << 3)
496 #define DMA_TX_STATUS_UNDERRUN (1 << 1)
497 #define DMA_TX_STATUS_PKT_SENT (1 << 0)
498 #define AR71XX_DMA_RX_CONTROL 0x18C
499 #define DMA_RX_CONTROL_EN (1 << 0)
500 #define AR71XX_DMA_RX_DESC 0x190
501 #define AR71XX_DMA_RX_STATUS 0x194
502 #define DMA_RX_STATUS_PCOUNT_MASK 0xff
503 #define DMA_RX_STATUS_PCOUNT_SHIFT 16
504 #define DMA_RX_STATUS_BUS_ERROR (1 << 3)
505 #define DMA_RX_STATUS_OVERFLOW (1 << 2)
506 #define DMA_RX_STATUS_PKT_RECVD (1 << 0)
507 #define AR71XX_DMA_INTR 0x198
508 #define AR71XX_DMA_INTR_STATUS 0x19C
509 #define DMA_INTR_ALL ((1 << 8) - 1)
510 #define DMA_INTR_RX_BUS_ERROR (1 << 7)
511 #define DMA_INTR_RX_OVERFLOW (1 << 6)
512 #define DMA_INTR_RX_PKT_RCVD (1 << 4)
513 #define DMA_INTR_TX_BUS_ERROR (1 << 3)
514 #define DMA_INTR_TX_UNDERRUN (1 << 1)
515 #define DMA_INTR_TX_PKT_SENT (1 << 0)
516
517 #define AR71XX_SPI_BASE 0x1f000000
518 #define AR71XX_SPI_FS 0x00
519 #define AR71XX_SPI_CTRL 0x04
520 #define SPI_CTRL_REMAP_DISABLE (1 << 6)
521 #define SPI_CTRL_CLOCK_DIVIDER_MASK ((1 << 6) - 1)
522 #define AR71XX_SPI_IO_CTRL 0x08
523 #define SPI_IO_CTRL_CS2 (1 << 18)
524 #define SPI_IO_CTRL_CS1 (1 << 17)
525 #define SPI_IO_CTRL_CS0 (1 << 16)
526 #define SPI_IO_CTRL_CSMASK (7 << 16)
527 #define SPI_IO_CTRL_CLK (1 << 8)
528 #define SPI_IO_CTRL_DO 1
529 #define AR71XX_SPI_RDS 0x0C
530
531 #define ATH_READ_REG(reg) \
532 *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg)))
533 /*
534 * Note: Don't put a flush read here; some users (eg the AR724x PCI fixup code)
535 * requires write-only space to certain registers. Doing the read afterwards
536 * causes things to break.
537 */
538 #define ATH_WRITE_REG(reg, val) \
539 *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val)
540
541 static inline void
ar71xx_ddr_flush(uint32_t reg)542 ar71xx_ddr_flush(uint32_t reg)
543 {
544 ATH_WRITE_REG(reg, 1);
545 while ((ATH_READ_REG(reg) & 0x1))
546 ;
547 ATH_WRITE_REG(reg, 1);
548 while ((ATH_READ_REG(reg) & 0x1))
549 ;
550 }
551
552 static inline void
ar71xx_write_pll(uint32_t cfg_reg,uint32_t pll_reg,uint32_t pll,uint32_t pll_reg_shift)553 ar71xx_write_pll(uint32_t cfg_reg, uint32_t pll_reg, uint32_t pll, uint32_t pll_reg_shift)
554 {
555 uint32_t sec_cfg;
556
557 /* set PLL registers */
558 sec_cfg = ATH_READ_REG(cfg_reg);
559 sec_cfg &= ~(3 << pll_reg_shift);
560 sec_cfg |= (2 << pll_reg_shift);
561
562 ATH_WRITE_REG(cfg_reg, sec_cfg);
563 DELAY(100);
564
565 ATH_WRITE_REG(pll_reg, pll);
566 sec_cfg |= (3 << pll_reg_shift);
567 ATH_WRITE_REG(cfg_reg, sec_cfg);
568 DELAY(100);
569
570 sec_cfg &= ~(3 << pll_reg_shift);
571 ATH_WRITE_REG(cfg_reg, sec_cfg);
572 DELAY(100);
573 }
574
575 #endif /* _AR71XX_REG_H_ */
576