Searched refs:TEGRA210_CLK_PCLK (Results 1 – 3 of 3) sorted by relevance
327 #define TEGRA210_CLK_PCLK 293 macro
247 GATE_INV(TEGRA210_CLK_PCLK, "pclk", "pclk_div", CLK_SYSTEM_RATE, 3),
831 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;