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Searched refs:SRLI (Results 1 – 23 of 23) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVMacroFusion.td36 "Enable SLLI+SRLI to be fused to zero extension of halfword",
43 CheckOpcode<[SRLI]>,
53 "Enable SLLI+SRLI to be fused to zero extension of word",
60 CheckOpcode<[SRLI]>,
71 "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension",
78 CheckOpcode<[SRLI]>,
HDRISCVISelDAGToDAG.cpp1145 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
1146 Subtarget->is64Bit() ? RISCV::SRLIW : RISCV::SRLI, DL, VT, in Select()
1148 ReplaceNode(Node, SRLI); in Select()
1169 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
1170 RISCV::SRLI, DL, VT, SDValue(SLLI, 0), in Select()
1172 ReplaceNode(Node, SRLI); in Select()
1321 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
1322 RISCV::SRLI, DL, VT, SDValue(SLLI, 0), in Select()
1324 ReplaceNode(Node, SRLI); in Select()
1351 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
[all …]
HDRISCVInstrInfoZb.td685 // Match a shifted 0xffffffff mask. Use SRLI to clear the LSBs and SLLI_UW to
688 (SLLI_UW (XLenVT (SRLI GPR:$rs1, Shifted32OnesMask:$mask)),
723 // Use SRLI to clear the LSBs and SHXADD_UW to mask and shift.
725 (SH1ADD_UW (XLenVT (SRLI GPR:$rs1, 1)), GPR:$rs2)>;
727 (SH2ADD_UW (XLenVT (SRLI GPR:$rs1, 2)), GPR:$rs2)>;
729 (SH3ADD_UW (XLenVT (SRLI GPR:$rs1, 3)), GPR:$rs2)>;
HDRISCVVectorPeephole.cpp98 } else if (Def->getOpcode() == RISCV::SRLI) { in convertToVLMAX()
HDRISCVOptWInstrs.cpp204 case RISCV::SRLI: { in hasAllNBitUsers()
364 case RISCV::SRLI: in isSignExtendingOpW()
HDRISCVInstrInfo.td665 def SRLI : Shift_ri<0b00000, 0b101, "srli">;
1032 (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1267 def : PatGprUimmLog2XLen<srl, SRLI>;
1293 (SLLI (i64 (SRLI $rs, LeadingOnesMask:$mask)), LeadingOnesMask:$mask)>;
1295 (SRLI (XLenVT (SLLI $rs, TrailingOnesMask:$mask)), TrailingOnesMask:$mask)>;
1812 def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (i64 (SLLI GPR:$rs1, 32)), 32)>;
1817 (SRLI (i64 (SLLI GPR:$rs1, 32)), (ImmSubFrom32 uimm5:$shamt))>;
2020 (SRLI (i32 (SLLI $rs, (i64 (XLenSubTrailingOnes $mask)))),
2028 def : Pat<(zext GPR:$src), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;
2033 (SRLI (i64 (SLLI GPR:$rs, 32)), (ImmSubFrom32 uimm5:$shamt))>;
HDRISCVAsmPrinter.cpp660 OutStreamer->emitInstruction(MCInstBuilder(RISCV::SRLI) in EmitHwasanMemaccessSymbols()
676 MCInstBuilder(RISCV::SRLI).addReg(RISCV::X7).addReg(Reg).addImm(56), in EmitHwasanMemaccessSymbols()
HDRISCVExpandPseudoInsts.cpp219 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break; in expandCCOp()
HDRISCVRegisterInfo.cpp858 case RISCV::SRLI: in getRegAllocationHints()
HDRISCVFrameLowering.cpp735 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR) in emitPrologue()
HDRISCVInstrInfoC.td928 def : CompressPat<(SRLI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$imm),
HDRISCVInstrInfo.cpp1307 case RISCV::SRLI: return RISCV::PseudoCCSRLI; break; in getPredicatedOpcode()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
HDRISCVMatInt.cpp26 case RISCV::SRLI: in getInstSeqCost()
193 TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros); in generateInstSeqLeadingZeros()
205 TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros); in generateInstSeqLeadingZeros()
538 case RISCV::SRLI: in getOpndKind()
/freebsd-13-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
HDRISCVInstructions.h143 R_SHAMT_TYPE_INST(SRLI);
278 LWU, LD, SD, SLLI, SRLI, SRAI, ADDIW, SLLIW, SRLIW, SRAIW, ADDW, SUBW, SLLW,
HDRISCVCInstructions.h241 return SRLI{rd, rd, uint8_t(shamt)}; in DecodeC_SRLI()
HDEmulateInstructionRISCV.cpp444 {"SRLI", 0xF800707F, 0x5013, DecodeRShamtType<SRLI>},
884 bool operator()(SRLI inst) { in operator ()()
/freebsd-13-stable/contrib/llvm-project/lld/ELF/Arch/
HDRISCV.cpp68 SRLI = 0x5013, enumerator
240 write32le(buf + 20, itype(SRLI, X_T1, X_T1, config->is64 ? 1 : 2)); in writePltHeader()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
HDRISCVInstructionSelector.cpp281 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
293 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Xtensa/
HDXtensaInstrInfo.td159 def SRLI : RRR_Inst<0x00, 0x01, 0x04, (outs AR:$r), (ins AR:$t, uimm4:$sa),
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsScheduleP5600.td438 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>;
HDMipsScheduleGeneric.td1559 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
HDRISCVAsmParser.cpp3320 unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; in emitPseudoExtend()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDDAGCombiner.cpp6386 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { in visitANDLike() local
6392 APInt SRLC = SRLI->getAPIntValue(); in visitANDLike()