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Searched refs:RMII (Results 1 – 21 of 21) sorted by relevance

/freebsd-13-stable/sys/contrib/device-tree/Bindings/net/
HDmediatek-dwmac.txt26 It should be defined for RMII interface when the reference clock is from MT2712 SoC.
29 It should be defined for RMII interface.
32 Both delay properties need to be a multiple of 550 for MII/RMII interface,
35 - mediatek,rmii-rxc: boolean property, if present indicates that the RMII
40 MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only.
44 which is from external PHYs in RMII case, and it rarely happen.
45 3. the reference clock, which outputs to TXC pin will be inversed in RMII case
49 2. reference clock will be inversed when arrived at MAC in RMII case, when
51 3. the inside clock, which be sent to MAC, will be inversed in RMII case when
HDmicrel.txt22 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
25 Setting the RMII Reference Clock Select bit enables 25 MHz rather
36 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
HDrockchip-dwmac.txt24 <&cru SCLK_MACREF>: clock gate for RMII referce clock
25 <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
33 is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
HDftgmac100.txt28 IP clock, and optionally an RMII RCLK gate for the AST2500/AST2600. The
33 - "RCLK": Clock gate for the RMII RCLK
HDcpsw-phy-sel.txt13 -rmii-clock-ext : If present, the driver will configure the RMII
HDdavinci_emac.txt23 - ti,davinci-rmii-en: 1 byte, 1 means use RMII
HDsti-dwmac.txt21 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
HDimx-dwmac.txt30 - snps,rmii_refclk_ext: to select RMII reference clock from external.
/freebsd-13-stable/sys/contrib/device-tree/src/powerpc/
HDkmeter1.dts346 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
362 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
378 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
394 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
410 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
432 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
437 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
442 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
447 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
452 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
/freebsd-13-stable/sys/contrib/device-tree/Bindings/phy/
HDti-phy-gmii-sel.txt5 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
21 | | | RMII <------->
47 cell 2 - RMII refclk mode
/freebsd-13-stable/sys/contrib/device-tree/src/arm/
HDimx53-kp-hsc.dts18 fixed-link { /* RMII fixed link to LAN9303 */
35 port@0 { /* RMII fixed link to master */
HDam335x-icev2.dts204 /* Slave 1, RMII mode */
213 /* Slave 2, RMII mode */
471 /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
HDimx6qdl-sr-som.dtsi107 * As the RMII pins are also connected to RGMII
/freebsd-13-stable/sys/contrib/device-tree/Bindings/net/dsa/
HDlan9303.txt31 fixed-link { /* RMII fixed link to LAN9303 */
47 port@0 { /* RMII fixed link to master */
HDsja1105.txt32 - In the case of MII or RMII it specifies whether the SJA1105 port is a
50 ports are at both ends of a MII/RMII PHY-less setup. One end would need
/freebsd-13-stable/sys/mips/conf/
HDPICOSTATION_M2HP.hints11 # arge0: dedicated switch port; RMII; dedicated PHY 4 on switch, connected
18 # arge1: nail to 1000/full, RMII - connected to the switch
HDROCKET_M2HP.hints11 # arge0: dedicated switch port; RMII; dedicated PHY 4 on switch, connected
18 # arge1: nail to 1000/full, RMII - connected to the switch
HDWZR-300HP.hints18 # arge1: nail to 1000/full, RMII - connected to the switch
/freebsd-13-stable/sys/contrib/device-tree/Bindings/clock/
Drockchip,rk3188-cru.txt37 - "ext_rmii" - external RMII clock - optional,
/freebsd-13-stable/sys/contrib/device-tree/Bindings/c6x/
HDdscr.txt41 offset and bitmask of RMII reset field. May have multiple tuples if more
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDMachineFunction.cpp1129 auto RMII = CurInst->getReverseIterator(); in salvageCopySSAImpl() local
1130 auto PrevInstrs = make_range(RMII, CurInst->getParent()->instr_rend()); in salvageCopySSAImpl()