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Searched refs:Q0 (Results 1 – 25 of 49) sorted by relevance

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/freebsd-13-stable/sys/arm/include/
HDcpu-v6.h309 _R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0)) in _WF0()
310 _R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0)) in _WF0()
311 _R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0)) in _WF0()
312 _W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0)) in _WF0()
313 _R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0)) in _WF0()
314 _W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0)) in _WF0()
315 _R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0)) in _WF0()
316 _W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0)) in _WF0()
317 _R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0)) in _WF0()
318 _W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0)) in _WF0()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonVectorPrint.cpp77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
88 if (R >= Hexagon::Q0 && R <= Hexagon::Q3) { in getStringReg()
90 return S[R-Hexagon::Q0]; in getStringReg()
192 } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { in runOnMachineFunction()
193 LLVM_DEBUG(dbgs() << "adding dump for Q" << Reg - Hexagon::Q0 << '\n'); in runOnMachineFunction()
HDHexagonRegisterInfo.cpp89 Q0, Q1, Q2, Q3, 0 in getCallerSavedRegs()
HDHexagonRegisterInfo.td283 def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>;
520 (add Q0, Q1, Q2, Q3)> {
HDHexagonISelLoweringHVX.cpp2590 SDValue Q0 = DAG.getSetCC(dl, PredTy, A, Zero, ISD::SETLT); in emitHvxMulLoHiV60() local
2592 SDValue X0 = DAG.getNode(ISD::VSELECT, dl, VecTy, {Q0, B, Zero}); in emitHvxMulLoHiV60()
2642 SDValue Q0 = DAG.getSetCC(dl, PredTy, A, Zero, ISD::SETLT); in emitHvxMulLoHiV62() local
2644 SDValue T0 = getInstr(Hexagon::V6_vandvqv, dl, VecTy, {Q0, B}, DAG); in emitHvxMulLoHiV62()
2656 SDValue Q0 = DAG.getSetCC(dl, PredTy, A, Zero, ISD::SETLT); in emitHvxMulLoHiV62() local
2657 Hi = getInstr(Hexagon::V6_vaddwq, dl, VecTy, {Q0, Hi, B}, DAG); in emitHvxMulLoHiV62()
/freebsd-13-stable/sys/contrib/libsodium/src/libsodium/include/sodium/private/
HDsse2_64_32.h18 # define _mm_set_epi64x(Q0, Q1) sodium__mm_set_epi64x((Q0), (Q1)) argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMCallingConv.td77 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
84 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
85 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
86 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
97 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
142 CCIfType<[f16, bf16, f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
143 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
145 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
146 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
225 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
[all …]
HDARMLowOverheadLoops.cpp1749 ARM::D0 + (Dst - ARM::Q0) * 2) in Expand()
1750 .addReg(ARM::D0 + (Src - ARM::Q0) * 2) in Expand()
1755 ARM::D0 + (Dst - ARM::Q0) * 2 + 1) in Expand()
1756 .addReg(ARM::D0 + (Src - ARM::Q0) * 2 + 1) in Expand()
HDARMCallingConv.cpp161 static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
HDARMRegisterInfo.td159 def Q0 : ARMReg< 0, "q0", [D0, D1]>;
582 // Same as QQPR but for MVE, containing the 7 register pairs made up from Q0-Q7.
608 // Same as QQPR but for MVE, containing the 5 register quads made up from Q0-Q7.
/freebsd-13-stable/lib/msun/bsdsrc/
HDb_tgamma.c171 Q0 = 1.4501953125000000e+0, variable
187 q = Q0 + z * (Q1 + z * (Q2 + z * (Q3 + z * (Q4 + z * (Q5 + in ratfun_gam()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/
HDVECallingConv.td51 CCAssignToRegWithShadow<[Q0, Q1, Q2, Q3],
96 CCAssignToRegWithShadow<[Q0, Q1, Q2, Q3],
HDVERegisterInfo.td133 // def Q0 : VEReg<0, "q0", [SX0, SX1], ["s0"]>;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64CallingConvention.td108 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
154 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
275 [Q0, Q1, Q2, Q3]>>,
282 [Q0, Q1, Q2, Q3]>>,
307 CCIfType<[f128], CCAssignToReg<[Q0, Q1]>>,
329 CCAssignToReg<[Q0, Q1, Q2, Q3]>>
397 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
582 // preserves X0-X8 and Q0-Q7.
HDAArch64CallingConvention.cpp35 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
HDAArch64PBQPRegAlloc.cpp121 case AArch64::Q0: in isOdd()
/freebsd-13-stable/sys/contrib/device-tree/src/arm/
HDaspeed-bmc-opp-romulus.dts252 /*Q0-Q7*/ "","","","","","","","id-button",
HDaspeed-bmc-opp-nicole.dts236 /*Q0-Q7*/ "","","","","","","","id-button",
HDaspeed-bmc-facebook-tiogapass.dts161 /*Q0-Q7*/ "","","","","UARTSW_LSB","UARTSW_MSB",
HDaspeed-bmc-opp-witherspoon.dts219 /*Q0-Q7*/ "","","","","","","","",
HDaspeed-bmc-opp-zaius.dts500 /*Q0-Q7*/ "","","","","","","","",
HDaspeed-bmc-opp-tacoma.dts120 /*Q0-Q7*/ "cfam-reset","","","","","","","fsi-routing",
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/
HDSparcDisassembler.cpp91 SP::Q0, SP::Q8, ~0U, ~0U,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
HDAArch64InstPrinter.cpp1512 case AArch64::Q0: Reg = AArch64::Q1; break; in getNextVectorRegister()
1545 Reg = AArch64::Q0; in getNextVectorRegister()
2089 case 128: Base = AArch64::Q0; break; in printZPRasFPR()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
HDAArch64AsmParser.cpp1786 case 128: Base = AArch64::Q0; break; in addFPRasZPRRegOperands()
1812 Inst.addOperand(MCOperand::createReg(AArch64::D0 + getReg() - AArch64::Q0)); in addVectorReg64Operands()
1843 /* DReg */ { AArch64::Q0, in addVectorListOperands()
1846 /* QReg */ { AArch64::Q0, in addVectorListOperands()
1847 AArch64::Q0, AArch64::Q0_Q1, in addVectorListOperands()
2638 .Case("v0", AArch64::Q0) in MatchNeonVectorRegName()
5243 (ZReg == ((Reg - AArch64::Q0) + AArch64::Z0)) || in isMatchingOrAlias()
7614 } else if (Reg >= AArch64::Q0 && Reg <= AArch64::Q31) { in parseDirectiveSEHSaveAnyReg()
7615 unsigned EncodedReg = Reg - AArch64::Q0; in parseDirectiveSEHSaveAnyReg()

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