1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003-2008, Joseph Koshy 5 * Copyright (c) 2007 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by A. Joseph Koshy under 9 * sponsorship from the FreeBSD Foundation and Google, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef _SYS_PMC_H_ 34 #define _SYS_PMC_H_ 35 36 #include <dev/hwpmc/pmc_events.h> 37 #include <sys/proc.h> 38 #include <sys/counter.h> 39 #include <machine/pmc_mdep.h> 40 #include <machine/profile.h> 41 #ifdef _KERNEL 42 #include <sys/epoch.h> 43 #include <ck_queue.h> 44 #endif 45 46 #define PMC_MODULE_NAME "hwpmc" 47 #define PMC_NAME_MAX 64 /* HW counter name size */ 48 #define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */ 49 50 /* 51 * Kernel<->userland API version number [MMmmpppp] 52 * 53 * Major numbers are to be incremented when an incompatible change to 54 * the ABI occurs that older clients will not be able to handle. 55 * 56 * Minor numbers are incremented when a backwards compatible change 57 * occurs that allows older correct programs to run unchanged. For 58 * example, when support for a new PMC type is added. 59 * 60 * The patch version is incremented for every bug fix. 61 */ 62 #define PMC_VERSION_MAJOR 0x09 63 #define PMC_VERSION_MINOR 0x04 64 #define PMC_VERSION_PATCH 0x0000 65 66 #define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \ 67 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH) 68 69 #define PMC_CPUID_LEN 64 70 /* cpu model name for pmu lookup */ 71 extern char pmc_cpuid[PMC_CPUID_LEN]; 72 73 /* 74 * Kinds of CPUs known. 75 * 76 * We keep track of CPU variants that need to be distinguished in 77 * some way for PMC operations. CPU names are grouped by manufacturer 78 * and numbered sparsely in order to minimize changes to the ABI involved 79 * when new CPUs are added. 80 */ 81 #define __PMC_CPUS() \ 82 __PMC_CPU(AMD_K7, 0x00, "AMD K7") \ 83 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ 84 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ 85 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ 86 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ 87 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ 88 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ 89 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ 90 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ 91 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ 92 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ 93 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ 94 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ 95 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ 96 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ 97 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ 98 __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ 99 __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ 100 __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \ 101 __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \ 102 __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \ 103 __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \ 104 __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \ 105 __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \ 106 __PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \ 107 __PMC_CPU(INTEL_ATOM_GOLDMONT_P, 0x9E, "Intel Atom Goldmont Plus") \ 108 __PMC_CPU(INTEL_ATOM_TREMONT, 0x9F, "Intel Atom Tremont") \ 109 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ 110 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ 111 __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ 112 __PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \ 113 __PMC_CPU(MIPS_BERI, 0x203, "BERI") \ 114 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ 115 __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ 116 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ 117 __PMC_CPU(PPC_POWER8, 0x390, "IBM POWER8") \ 118 __PMC_CPU(GENERIC, 0x400, "Generic") \ 119 __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ 120 __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ 121 __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ 122 __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ 123 __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ 124 __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ 125 __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ 126 __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") \ 127 __PMC_CPU(ARMV8_CORTEX_A76, 0x602, "ARMv8 Cortex A76") 128 129 enum pmc_cputype { 130 #undef __PMC_CPU 131 #define __PMC_CPU(S,V,D) PMC_CPU_##S = V, 132 __PMC_CPUS() 133 }; 134 135 #define PMC_CPU_FIRST PMC_CPU_AMD_K7 136 #define PMC_CPU_LAST PMC_CPU_ARMV8_CORTEX_A76 137 138 /* 139 * Classes of PMCs 140 */ 141 #define __PMC_CLASSES() \ 142 __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \ 143 __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \ 144 __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \ 145 __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \ 146 __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \ 147 __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \ 148 __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \ 149 __PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \ 150 __PMC_CLASS(MIPS24K, 0x0B, "MIPS 24K") \ 151 __PMC_CLASS(OCTEON, 0x0C, "Cavium Octeon") \ 152 __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \ 153 __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \ 154 __PMC_CLASS(SOFT, 0x0F, "Software events") \ 155 __PMC_CLASS(ARMV7, 0x10, "ARMv7") \ 156 __PMC_CLASS(ARMV8, 0x11, "ARMv8") \ 157 __PMC_CLASS(MIPS74K, 0x12, "MIPS 74K") \ 158 __PMC_CLASS(E500, 0x13, "Freescale e500 class") \ 159 __PMC_CLASS(BERI, 0x14, "MIPS BERI") \ 160 __PMC_CLASS(POWER8, 0x15, "IBM POWER8 class") \ 161 162 enum pmc_class { 163 #undef __PMC_CLASS 164 #define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V, 165 __PMC_CLASSES() 166 }; 167 168 #define PMC_CLASS_FIRST PMC_CLASS_TSC 169 #define PMC_CLASS_LAST PMC_CLASS_POWER8 170 171 /* 172 * A PMC can be in the following states: 173 * 174 * Hardware states: 175 * DISABLED -- administratively prohibited from being used. 176 * FREE -- HW available for use 177 * Software states: 178 * ALLOCATED -- allocated 179 * STOPPED -- allocated, but not counting events 180 * RUNNING -- allocated, and in operation; 'pm_runcount' 181 * holds the number of CPUs using this PMC at 182 * a given instant 183 * DELETED -- being destroyed 184 */ 185 186 #define __PMC_HWSTATES() \ 187 __PMC_STATE(DISABLED) \ 188 __PMC_STATE(FREE) 189 190 #define __PMC_SWSTATES() \ 191 __PMC_STATE(ALLOCATED) \ 192 __PMC_STATE(STOPPED) \ 193 __PMC_STATE(RUNNING) \ 194 __PMC_STATE(DELETED) 195 196 #define __PMC_STATES() \ 197 __PMC_HWSTATES() \ 198 __PMC_SWSTATES() 199 200 enum pmc_state { 201 #undef __PMC_STATE 202 #define __PMC_STATE(S) PMC_STATE_##S, 203 __PMC_STATES() 204 __PMC_STATE(MAX) 205 }; 206 207 #define PMC_STATE_FIRST PMC_STATE_DISABLED 208 #define PMC_STATE_LAST PMC_STATE_DELETED 209 210 /* 211 * An allocated PMC may used as a 'global' counter or as a 212 * 'thread-private' one. Each such mode of use can be in either 213 * statistical sampling mode or in counting mode. Thus a PMC in use 214 * 215 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling 216 * SC i.e., SYSTEM COUNTER -- system-wide counting mode 217 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling 218 * TC i.e., THREAD COUNTER -- thread virtual, counting mode 219 * 220 * Statistical profiling modes rely on the PMC periodically delivering 221 * a interrupt to the CPU (when the configured number of events have 222 * been measured), so the PMC must have the ability to generate 223 * interrupts. 224 * 225 * In counting modes, the PMC counts its configured events, with the 226 * value of the PMC being read whenever needed by its owner process. 227 * 228 * The thread specific modes "virtualize" the PMCs -- the PMCs appear 229 * to be thread private and count events only when the profiled thread 230 * actually executes on the CPU. 231 * 232 * The system-wide "global" modes keep the PMCs running all the time 233 * and are used to measure the behaviour of the whole system. 234 */ 235 236 #define __PMC_MODES() \ 237 __PMC_MODE(SS, 0) \ 238 __PMC_MODE(SC, 1) \ 239 __PMC_MODE(TS, 2) \ 240 __PMC_MODE(TC, 3) 241 242 enum pmc_mode { 243 #undef __PMC_MODE 244 #define __PMC_MODE(M,N) PMC_MODE_##M = N, 245 __PMC_MODES() 246 }; 247 248 #define PMC_MODE_FIRST PMC_MODE_SS 249 #define PMC_MODE_LAST PMC_MODE_TC 250 251 #define PMC_IS_COUNTING_MODE(mode) \ 252 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC) 253 #define PMC_IS_SYSTEM_MODE(mode) \ 254 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC) 255 #define PMC_IS_SAMPLING_MODE(mode) \ 256 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS) 257 #define PMC_IS_VIRTUAL_MODE(mode) \ 258 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC) 259 260 /* 261 * PMC row disposition 262 */ 263 264 #define __PMC_DISPOSITIONS(N) \ 265 __PMC_DISP(STANDALONE) /* global/disabled counters */ \ 266 __PMC_DISP(FREE) /* free/available */ \ 267 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \ 268 __PMC_DISP(UNKNOWN) /* sentinel */ 269 270 enum pmc_disp { 271 #undef __PMC_DISP 272 #define __PMC_DISP(D) PMC_DISP_##D , 273 __PMC_DISPOSITIONS() 274 }; 275 276 #define PMC_DISP_FIRST PMC_DISP_STANDALONE 277 #define PMC_DISP_LAST PMC_DISP_THREAD 278 279 /* 280 * Counter capabilities 281 * 282 * __PMC_CAPS(NAME, VALUE, DESCRIPTION) 283 */ 284 285 #define __PMC_CAPS() \ 286 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \ 287 __PMC_CAP(USER, 1, "count user-mode events") \ 288 __PMC_CAP(SYSTEM, 2, "count system-mode events") \ 289 __PMC_CAP(EDGE, 3, "do edge detection of events") \ 290 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \ 291 __PMC_CAP(READ, 5, "read PMC counter") \ 292 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \ 293 __PMC_CAP(INVERT, 7, "invert comparison sense") \ 294 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \ 295 __PMC_CAP(PRECISE, 9, "perform precise sampling") \ 296 __PMC_CAP(TAGGING, 10, "tag upstream events") \ 297 __PMC_CAP(CASCADE, 11, "cascade counters") 298 299 enum pmc_caps 300 { 301 #undef __PMC_CAP 302 #define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) , 303 __PMC_CAPS() 304 }; 305 306 #define PMC_CAP_FIRST PMC_CAP_INTERRUPT 307 #define PMC_CAP_LAST PMC_CAP_CASCADE 308 309 /* 310 * PMC Event Numbers 311 * 312 * These are generated from the definitions in "dev/hwpmc/pmc_events.h". 313 */ 314 315 enum pmc_event { 316 #undef __PMC_EV 317 #undef __PMC_EV_BLOCK 318 #define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 , 319 #define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N , 320 __PMC_EVENTS() 321 }; 322 323 /* 324 * PMC SYSCALL INTERFACE 325 */ 326 327 /* 328 * "PMC_OPS" -- these are the commands recognized by the kernel 329 * module, and are used when performing a system call from userland. 330 */ 331 #define __PMC_OPS() \ 332 __PMC_OP(CONFIGURELOG, "Set log file") \ 333 __PMC_OP(FLUSHLOG, "Flush log file") \ 334 __PMC_OP(GETCPUINFO, "Get system CPU information") \ 335 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \ 336 __PMC_OP(GETMODULEVERSION, "Get module version") \ 337 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \ 338 __PMC_OP(PMCADMIN, "Set PMC state") \ 339 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \ 340 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \ 341 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \ 342 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \ 343 __PMC_OP(PMCRELEASE, "Release a PMC") \ 344 __PMC_OP(PMCRW, "Read/Set a PMC") \ 345 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \ 346 __PMC_OP(PMCSTART, "Start a PMC") \ 347 __PMC_OP(PMCSTOP, "Stop a PMC") \ 348 __PMC_OP(WRITELOG, "Write a cookie to the log file") \ 349 __PMC_OP(CLOSELOG, "Close log file") \ 350 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list") 351 352 enum pmc_ops { 353 #undef __PMC_OP 354 #define __PMC_OP(N, D) PMC_OP_##N, 355 __PMC_OPS() 356 }; 357 358 /* 359 * Flags used in operations on PMCs. 360 */ 361 362 #define PMC_F_UNUSED1 0x00000001 /* unused */ 363 #define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */ 364 #define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */ 365 #define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */ 366 #define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */ 367 #define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */ 368 369 /* V2 API */ 370 #define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */ 371 #define PMC_F_USERCALLCHAIN 0x00000100 /*OP ALLOCATE use userspace stack */ 372 373 /* internal flags */ 374 #define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/ 375 #define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */ 376 #define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */ 377 378 #define PMC_CALLCHAIN_DEPTH_MAX 512 379 380 #define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/ 381 382 /* 383 * Cookies used to denote allocated PMCs, and the values of PMCs. 384 */ 385 386 typedef uint32_t pmc_id_t; 387 typedef uint64_t pmc_value_t; 388 389 #define PMC_ID_INVALID (~ (pmc_id_t) 0) 390 391 /* 392 * PMC IDs have the following format: 393 * 394 * +-----------------------+-------+-----------+ 395 * | CPU | PMC MODE | CLASS | ROW INDEX | 396 * +-----------------------+-------+-----------+ 397 * 398 * where CPU is 12 bits, MODE 8, CLASS 4, and ROW INDEX 8 Field 'CPU' 399 * is set to the requested CPU for system-wide PMCs or PMC_CPU_ANY for 400 * process-mode PMCs. Field 'PMC MODE' is the allocated PMC mode. 401 * Field 'PMC CLASS' is the class of the PMC. Field 'ROW INDEX' is the 402 * row index for the PMC. 403 * 404 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total 405 * number of hardware PMCs on this cpu. 406 */ 407 408 #define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF) 409 #define PMC_ID_TO_CLASS(ID) (((ID) & 0xF00) >> 8) 410 #define PMC_ID_TO_MODE(ID) (((ID) & 0xFF000) >> 12) 411 #define PMC_ID_TO_CPU(ID) (((ID) & 0xFFF00000) >> 20) 412 #define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \ 413 ((((CPU) & 0xFFF) << 20) | (((MODE) & 0xFF) << 12) | \ 414 (((CLASS) & 0xF) << 8) | ((ROWINDEX) & 0xFF)) 415 416 /* 417 * Data structures for system calls supported by the pmc driver. 418 */ 419 420 /* 421 * OP PMCALLOCATE 422 * 423 * Allocate a PMC on the named CPU. 424 */ 425 426 #define PMC_CPU_ANY ~0 427 428 struct pmc_op_pmcallocate { 429 uint32_t pm_caps; /* PMC_CAP_* */ 430 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */ 431 enum pmc_class pm_class; /* class of PMC desired */ 432 enum pmc_event pm_ev; /* [enum pmc_event] desired */ 433 uint32_t pm_flags; /* additional modifiers PMC_F_* */ 434 enum pmc_mode pm_mode; /* desired mode */ 435 pmc_id_t pm_pmcid; /* [return] process pmc id */ 436 pmc_value_t pm_count; /* initial/sample count */ 437 438 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */ 439 }; 440 441 /* 442 * OP PMCADMIN 443 * 444 * Set the administrative state (i.e., whether enabled or disabled) of 445 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an 446 * absolute PMC number and need not have been first allocated by the 447 * calling process. 448 */ 449 450 struct pmc_op_pmcadmin { 451 int pm_cpu; /* CPU# */ 452 uint32_t pm_flags; /* flags */ 453 int pm_pmc; /* PMC# */ 454 enum pmc_state pm_state; /* desired state */ 455 }; 456 457 /* 458 * OP PMCATTACH / OP PMCDETACH 459 * 460 * Attach/detach a PMC and a process. 461 */ 462 463 struct pmc_op_pmcattach { 464 pmc_id_t pm_pmc; /* PMC to attach to */ 465 pid_t pm_pid; /* target process */ 466 }; 467 468 /* 469 * OP PMCSETCOUNT 470 * 471 * Set the sampling rate (i.e., the reload count) for statistical counters. 472 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE. 473 */ 474 475 struct pmc_op_pmcsetcount { 476 pmc_value_t pm_count; /* initial/sample count */ 477 pmc_id_t pm_pmcid; /* PMC id to set */ 478 }; 479 480 /* 481 * OP PMCRW 482 * 483 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs 484 * to have been previously allocated using PMCALLOCATE. 485 */ 486 487 struct pmc_op_pmcrw { 488 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/ 489 pmc_id_t pm_pmcid; /* pmc id */ 490 pmc_value_t pm_value; /* new&returned value */ 491 }; 492 493 /* 494 * OP GETPMCINFO 495 * 496 * retrieve PMC state for a named CPU. The caller is expected to 497 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return 498 * values. 499 */ 500 501 struct pmc_info { 502 char pm_name[PMC_NAME_MAX]; /* pmc name */ 503 enum pmc_class pm_class; /* enum pmc_class */ 504 int pm_enabled; /* whether enabled */ 505 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */ 506 pid_t pm_ownerpid; /* owner, or -1 */ 507 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */ 508 enum pmc_event pm_event; /* current event */ 509 uint32_t pm_flags; /* current flags */ 510 pmc_value_t pm_reloadcount; /* sampling counters only */ 511 }; 512 513 struct pmc_op_getpmcinfo { 514 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */ 515 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */ 516 }; 517 518 /* 519 * OP GETCPUINFO 520 * 521 * Retrieve system CPU information. 522 */ 523 524 struct pmc_classinfo { 525 enum pmc_class pm_class; /* class id */ 526 uint32_t pm_caps; /* counter capabilities */ 527 uint32_t pm_width; /* width of the PMC */ 528 uint32_t pm_num; /* number of PMCs in class */ 529 }; 530 531 struct pmc_op_getcpuinfo { 532 enum pmc_cputype pm_cputype; /* what kind of CPU */ 533 uint32_t pm_ncpu; /* max CPU number */ 534 uint32_t pm_npmc; /* #PMCs per CPU */ 535 uint32_t pm_nclass; /* #classes of PMCs */ 536 struct pmc_classinfo pm_classes[PMC_CLASS_MAX]; 537 }; 538 539 /* 540 * OP CONFIGURELOG 541 * 542 * Configure a log file for writing system-wide statistics to. 543 */ 544 545 struct pmc_op_configurelog { 546 int pm_flags; 547 int pm_logfd; /* logfile fd (or -1) */ 548 }; 549 550 /* 551 * OP GETDRIVERSTATS 552 * 553 * Retrieve pmc(4) driver-wide statistics. 554 */ 555 #ifdef _KERNEL 556 struct pmc_driverstats { 557 counter_u64_t pm_intr_ignored; /* #interrupts ignored */ 558 counter_u64_t pm_intr_processed; /* #interrupts processed */ 559 counter_u64_t pm_intr_bufferfull; /* #interrupts with ENOSPC */ 560 counter_u64_t pm_syscalls; /* #syscalls */ 561 counter_u64_t pm_syscall_errors; /* #syscalls with errors */ 562 counter_u64_t pm_buffer_requests; /* #buffer requests */ 563 counter_u64_t pm_buffer_requests_failed; /* #failed buffer requests */ 564 counter_u64_t pm_log_sweeps; /* #sample buffer processing 565 passes */ 566 counter_u64_t pm_merges; /* merged k+u */ 567 counter_u64_t pm_overwrites; /* UR overwrites */ 568 }; 569 #endif 570 571 struct pmc_op_getdriverstats { 572 unsigned int pm_intr_ignored; /* #interrupts ignored */ 573 unsigned int pm_intr_processed; /* #interrupts processed */ 574 unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */ 575 unsigned int pm_syscalls; /* #syscalls */ 576 unsigned int pm_syscall_errors; /* #syscalls with errors */ 577 unsigned int pm_buffer_requests; /* #buffer requests */ 578 unsigned int pm_buffer_requests_failed; /* #failed buffer requests */ 579 unsigned int pm_log_sweeps; /* #sample buffer processing 580 passes */ 581 }; 582 583 /* 584 * OP RELEASE / OP START / OP STOP 585 * 586 * Simple operations on a PMC id. 587 */ 588 589 struct pmc_op_simple { 590 pmc_id_t pm_pmcid; 591 }; 592 593 /* 594 * OP WRITELOG 595 * 596 * Flush the current log buffer and write 4 bytes of user data to it. 597 */ 598 599 struct pmc_op_writelog { 600 uint32_t pm_userdata; 601 }; 602 603 /* 604 * OP GETMSR 605 * 606 * Retrieve the machine specific address associated with the allocated 607 * PMC. This number can be used subsequently with a read-performance-counter 608 * instruction. 609 */ 610 611 struct pmc_op_getmsr { 612 uint32_t pm_msr; /* machine specific address */ 613 pmc_id_t pm_pmcid; /* allocated pmc id */ 614 }; 615 616 /* 617 * OP GETDYNEVENTINFO 618 * 619 * Retrieve a PMC dynamic class events list. 620 */ 621 622 struct pmc_dyn_event_descr { 623 char pm_ev_name[PMC_NAME_MAX]; 624 enum pmc_event pm_ev_code; 625 }; 626 627 struct pmc_op_getdyneventinfo { 628 enum pmc_class pm_class; 629 unsigned int pm_nevent; 630 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT]; 631 }; 632 633 #ifdef _KERNEL 634 635 #include <sys/malloc.h> 636 #include <sys/sysctl.h> 637 #include <sys/_cpuset.h> 638 639 #include <machine/frame.h> 640 641 #define PMC_HASH_SIZE 1024 642 #define PMC_MTXPOOL_SIZE 2048 643 #define PMC_LOG_BUFFER_SIZE 256 644 #define PMC_NLOGBUFFERS_PCPU 32 645 #define PMC_NSAMPLES 256 646 #define PMC_CALLCHAIN_DEPTH 128 647 #define PMC_THREADLIST_MAX 128 648 649 #define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "." 650 651 /* 652 * Locking keys 653 * 654 * (b) - pmc_bufferlist_mtx (spin lock) 655 * (k) - pmc_kthread_mtx (sleep lock) 656 * (o) - po->po_mtx (spin lock) 657 * (g) - global_epoch_preempt (epoch) 658 * (p) - pmc_sx (sx) 659 */ 660 661 /* 662 * PMC commands 663 */ 664 665 struct pmc_syscall_args { 666 register_t pmop_code; /* one of PMC_OP_* */ 667 void *pmop_data; /* syscall parameter */ 668 }; 669 670 /* 671 * Interface to processor specific s1tuff 672 */ 673 674 /* 675 * struct pmc_descr 676 * 677 * Machine independent (i.e., the common parts) of a human readable 678 * PMC description. 679 */ 680 681 struct pmc_descr { 682 char pd_name[PMC_NAME_MAX]; /* name */ 683 uint32_t pd_caps; /* capabilities */ 684 enum pmc_class pd_class; /* class of the PMC */ 685 uint32_t pd_width; /* width in bits */ 686 }; 687 688 /* 689 * struct pmc_target 690 * 691 * This structure records all the target processes associated with a 692 * PMC. 693 */ 694 695 struct pmc_target { 696 LIST_ENTRY(pmc_target) pt_next; 697 struct pmc_process *pt_process; /* target descriptor */ 698 }; 699 700 /* 701 * struct pmc 702 * 703 * Describes each allocated PMC. 704 * 705 * Each PMC has precisely one owner, namely the process that allocated 706 * the PMC. 707 * 708 * A PMC may be attached to multiple target processes. The 709 * 'pm_targets' field links all the target processes being monitored 710 * by this PMC. 711 * 712 * The 'pm_savedvalue' field is protected by a mutex. 713 * 714 * On a multi-cpu machine, multiple target threads associated with a 715 * process-virtual PMC could be concurrently executing on different 716 * CPUs. The 'pm_runcount' field is atomically incremented every time 717 * the PMC gets scheduled on a CPU and atomically decremented when it 718 * get descheduled. Deletion of a PMC is only permitted when this 719 * field is '0'. 720 * 721 */ 722 struct pmc_pcpu_state { 723 uint32_t pps_overflowcnt; /* count overflow interrupts */ 724 uint8_t pps_stalled; 725 uint8_t pps_cpustate; 726 } __aligned(CACHE_LINE_SIZE); 727 struct pmc { 728 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */ 729 LIST_ENTRY(pmc) pm_next; /* owner's list */ 730 731 /* 732 * System-wide PMCs are allocated on a CPU and are not moved 733 * around. For system-wide PMCs we record the CPU the PMC was 734 * allocated on in the 'CPU' field of the pmc ID. 735 * 736 * Virtual PMCs run on whichever CPU is currently executing 737 * their targets' threads. For these PMCs we need to save 738 * their current PMC counter values when they are taken off 739 * CPU. 740 */ 741 742 union { 743 pmc_value_t pm_savedvalue; /* Virtual PMCS */ 744 } pm_gv; 745 746 /* 747 * For sampling mode PMCs, we keep track of the PMC's "reload 748 * count", which is the counter value to be loaded in when 749 * arming the PMC for the next counting session. For counting 750 * modes on PMCs that are read-only (e.g., the x86 TSC), we 751 * keep track of the initial value at the start of 752 * counting-mode operation. 753 */ 754 755 union { 756 pmc_value_t pm_reloadcount; /* sampling PMC modes */ 757 pmc_value_t pm_initial; /* counting PMC modes */ 758 } pm_sc; 759 760 struct pmc_pcpu_state *pm_pcpu_state; 761 volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */ 762 uint32_t pm_caps; /* PMC capabilities */ 763 enum pmc_event pm_event; /* event being measured */ 764 uint32_t pm_flags; /* additional flags PMC_F_... */ 765 struct pmc_owner *pm_owner; /* owner thread state */ 766 counter_u64_t pm_runcount; /* #cpus currently on */ 767 enum pmc_state pm_state; /* current PMC state */ 768 769 /* 770 * The PMC ID field encodes the row-index for the PMC, its 771 * mode, class and the CPU# associated with the PMC. 772 */ 773 774 pmc_id_t pm_id; /* allocated PMC id */ 775 enum pmc_class pm_class; 776 777 /* md extensions */ 778 union pmc_md_pmc pm_md; 779 }; 780 781 /* 782 * Accessor macros for 'struct pmc' 783 */ 784 785 #define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id) 786 #define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id) 787 #define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id) 788 #define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id) 789 790 /* 791 * struct pmc_threadpmcstate 792 * 793 * Record per-PMC, per-thread state. 794 */ 795 struct pmc_threadpmcstate { 796 pmc_value_t pt_pmcval; /* per-thread reload count */ 797 }; 798 799 /* 800 * struct pmc_thread 801 * 802 * Record a 'target' thread being profiled. 803 */ 804 struct pmc_thread { 805 LIST_ENTRY(pmc_thread) pt_next; /* linked list */ 806 struct thread *pt_td; /* target thread */ 807 struct pmc_threadpmcstate pt_pmcs[]; /* per-PMC state */ 808 }; 809 810 /* 811 * struct pmc_process 812 * 813 * Record a 'target' process being profiled. 814 * 815 * The target process being profiled could be different from the owner 816 * process which allocated the PMCs. Each target process descriptor 817 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a 818 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]' 819 * array. The size of this structure is thus PMC architecture 820 * dependent. 821 * 822 */ 823 824 struct pmc_targetstate { 825 struct pmc *pp_pmc; /* target PMC */ 826 pmc_value_t pp_pmcval; /* per-process value */ 827 }; 828 829 struct pmc_process { 830 LIST_ENTRY(pmc_process) pp_next; /* hash chain */ 831 LIST_HEAD(,pmc_thread) pp_tds; /* list of threads */ 832 struct mtx *pp_tdslock; /* lock on pp_tds thread list */ 833 int pp_refcnt; /* reference count */ 834 uint32_t pp_flags; /* flags PMC_PP_* */ 835 struct proc *pp_proc; /* target process */ 836 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */ 837 }; 838 839 #define PMC_PP_ENABLE_MSR_ACCESS 0x00000001 840 841 /* 842 * struct pmc_owner 843 * 844 * We associate a PMC with an 'owner' process. 845 * 846 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its 847 * lifetime, where NCPUS is the numbers of CPUS in the system and 848 * NHWPMC is the number of hardware PMCs per CPU. These are 849 * maintained in the list headed by the 'po_pmcs' to save on space. 850 * 851 */ 852 853 struct pmc_owner { 854 LIST_ENTRY(pmc_owner) po_next; /* hash chain */ 855 CK_LIST_ENTRY(pmc_owner) po_ssnext; /* (g/p) list of SS PMC owners */ 856 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */ 857 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */ 858 struct mtx po_mtx; /* spin lock for (o) */ 859 struct proc *po_owner; /* owner proc */ 860 uint32_t po_flags; /* (k) flags PMC_PO_* */ 861 struct proc *po_kthread; /* (k) helper kthread */ 862 struct file *po_file; /* file reference */ 863 int po_error; /* recorded error */ 864 short po_sscount; /* # SS PMCs owned */ 865 short po_logprocmaps; /* global mappings done */ 866 struct pmclog_buffer *po_curbuf[MAXCPU]; /* current log buffer */ 867 }; 868 869 #define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */ 870 #define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */ 871 #define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020 872 873 /* 874 * struct pmc_hw -- describe the state of the PMC hardware 875 * 876 * When in use, a HW PMC is associated with one allocated 'struct pmc' 877 * pointed to by field 'phw_pmc'. When inactive, this field is NULL. 878 * 879 * On an SMP box, one or more HW PMC's in process virtual mode with 880 * the same 'phw_pmc' could be executing on different CPUs. In order 881 * to handle this case correctly, we need to ensure that only 882 * incremental counts get added to the saved value in the associated 883 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC 884 * value at the time the hardware is started during this context 885 * switch (i.e., the difference between the new (hardware) count and 886 * the saved count is atomically added to the count field in 'struct 887 * pmc' at context switch time). 888 * 889 */ 890 891 struct pmc_hw { 892 uint32_t phw_state; /* see PHW_* macros below */ 893 struct pmc *phw_pmc; /* current thread PMC */ 894 }; 895 896 #define PMC_PHW_RI_MASK 0x000000FF 897 #define PMC_PHW_CPU_SHIFT 8 898 #define PMC_PHW_CPU_MASK 0x0000FF00 899 #define PMC_PHW_FLAGS_SHIFT 16 900 #define PMC_PHW_FLAGS_MASK 0xFFFF0000 901 902 #define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK) 903 #define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK) 904 #define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \ 905 PMC_PHW_CPU_MASK) 906 #define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \ 907 PMC_PHW_CPU_SHIFT) 908 #define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \ 909 PMC_PHW_FLAGS_MASK) 910 #define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \ 911 PMC_PHW_FLAGS_SHIFT) 912 #define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01)) 913 #define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02)) 914 915 /* 916 * struct pmc_sample 917 * 918 * Space for N (tunable) PC samples and associated control data. 919 */ 920 921 struct pmc_sample { 922 uint16_t ps_nsamples; /* callchain depth */ 923 uint16_t ps_nsamples_actual; 924 uint16_t ps_cpu; /* cpu number */ 925 uint16_t ps_flags; /* other flags */ 926 lwpid_t ps_tid; /* thread id */ 927 pid_t ps_pid; /* process PID or -1 */ 928 int ps_ticks; /* ticks at sample time */ 929 /* pad */ 930 struct thread *ps_td; /* which thread */ 931 struct pmc *ps_pmc; /* interrupting PMC */ 932 uintptr_t *ps_pc; /* (const) callchain start */ 933 uint64_t ps_tsc; /* tsc value */ 934 }; 935 936 #define PMC_SAMPLE_FREE ((uint16_t) 0) 937 #define PMC_USER_CALLCHAIN_PENDING ((uint16_t) 0xFFFF) 938 939 struct pmc_samplebuffer { 940 volatile uint64_t ps_prodidx; /* producer index */ 941 volatile uint64_t ps_considx; /* consumer index */ 942 uintptr_t *ps_callchains; /* all saved call chains */ 943 struct pmc_sample ps_samples[]; /* array of sample entries */ 944 }; 945 946 #define PMC_CONS_SAMPLE(psb) \ 947 (&(psb)->ps_samples[(psb)->ps_considx & pmc_sample_mask]) 948 949 #define PMC_CONS_SAMPLE_OFF(psb, off) \ 950 (&(psb)->ps_samples[(off) & pmc_sample_mask]) 951 952 #define PMC_PROD_SAMPLE(psb) \ 953 (&(psb)->ps_samples[(psb)->ps_prodidx & pmc_sample_mask]) 954 955 /* 956 * struct pmc_cpustate 957 * 958 * A CPU is modelled as a collection of HW PMCs with space for additional 959 * flags. 960 */ 961 962 struct pmc_cpu { 963 uint32_t pc_state; /* physical cpu number + flags */ 964 struct pmc_samplebuffer *pc_sb[3]; /* space for samples */ 965 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */ 966 }; 967 968 #define PMC_PCPU_CPU_MASK 0x000000FF 969 #define PMC_PCPU_FLAGS_MASK 0xFFFFFF00 970 #define PMC_PCPU_FLAGS_SHIFT 8 971 #define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK) 972 #define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT) 973 #define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK) 974 #define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK) 975 #define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1)) 976 977 /* 978 * struct pmc_binding 979 * 980 * CPU binding information. 981 */ 982 983 struct pmc_binding { 984 int pb_bound; /* is bound? */ 985 int pb_cpu; /* if so, to which CPU */ 986 u_char pb_priority; /* Thread active priority. */ 987 }; 988 989 struct pmc_mdep; 990 991 /* 992 * struct pmc_classdep 993 * 994 * PMC class-dependent operations. 995 */ 996 struct pmc_classdep { 997 uint32_t pcd_caps; /* class capabilities */ 998 enum pmc_class pcd_class; /* class id */ 999 int pcd_num; /* number of PMCs */ 1000 int pcd_ri; /* row index of the first PMC in class */ 1001 int pcd_width; /* width of the PMC */ 1002 1003 /* configuring/reading/writing the hardware PMCs */ 1004 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm); 1005 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm); 1006 int (*pcd_read_pmc)(int _cpu, int _ri, struct pmc *_pm, 1007 pmc_value_t *_value); 1008 int (*pcd_write_pmc)(int _cpu, int _ri, struct pmc *_pm, 1009 pmc_value_t _value); 1010 1011 /* pmc allocation/release */ 1012 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t, 1013 const struct pmc_op_pmcallocate *_a); 1014 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm); 1015 1016 /* starting and stopping PMCs */ 1017 int (*pcd_start_pmc)(int _cpu, int _ri, struct pmc *_pm); 1018 int (*pcd_stop_pmc)(int _cpu, int _ri, struct pmc *_pm); 1019 1020 /* description */ 1021 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi, 1022 struct pmc **_ppmc); 1023 1024 /* class-dependent initialization & finalization */ 1025 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 1026 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 1027 1028 /* machine-specific interface */ 1029 int (*pcd_get_msr)(int _ri, uint32_t *_msr); 1030 }; 1031 1032 /* 1033 * struct pmc_mdep 1034 * 1035 * Machine dependent bits needed per CPU type. 1036 */ 1037 1038 struct pmc_mdep { 1039 uint32_t pmd_cputype; /* from enum pmc_cputype */ 1040 uint32_t pmd_npmc; /* number of PMCs per CPU */ 1041 uint32_t pmd_nclass; /* number of PMC classes present */ 1042 1043 /* 1044 * Machine dependent methods. 1045 */ 1046 1047 /* thread context switch in/out */ 1048 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp); 1049 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp); 1050 1051 /* handle a PMC interrupt */ 1052 int (*pmd_intr)(struct trapframe *_tf); 1053 1054 /* 1055 * PMC class dependent information. 1056 */ 1057 struct pmc_classdep pmd_classdep[]; 1058 }; 1059 1060 /* 1061 * Per-CPU state. This is an array of 'mp_ncpu' pointers 1062 * to struct pmc_cpu descriptors. 1063 */ 1064 1065 extern struct pmc_cpu **pmc_pcpu; 1066 1067 /* driver statistics */ 1068 extern struct pmc_driverstats pmc_stats; 1069 1070 #if defined(HWPMC_DEBUG) 1071 1072 /* HWPMC_DEBUG without KTR will compile but is a no-op. */ 1073 #if !defined(KTR) || !defined(KTR_COMPILE) || ((KTR_COMPILE & KTR_SUBSYS) == 0) 1074 #error "HWPMC_DEBUG requires KTR and KTR_COMPILE=KTR_SUBSYS -- see ktr(4)" 1075 #endif 1076 1077 #include <sys/ktr.h> 1078 1079 #define __pmcdbg_used /* unused variable annotation */ 1080 1081 /* 1082 * Debug flags, major flag groups. 1083 * 1084 * Please keep the DEBUGGING section of the hwpmc(4) man page in sync. 1085 */ 1086 struct pmc_debugflags { 1087 int pdb_CPU; 1088 int pdb_CSW; 1089 int pdb_LOG; 1090 int pdb_MDP; 1091 int pdb_MOD; 1092 int pdb_OWN; 1093 int pdb_PMC; 1094 int pdb_PRC; 1095 int pdb_SAM; 1096 }; 1097 1098 extern struct pmc_debugflags pmc_debugflags; 1099 1100 #define KTR_PMC KTR_SUBSYS 1101 1102 #define PMC_DEBUG_STRSIZE 128 1103 #define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1104 1105 #define PMCDBG0(M, N, L, F) do { \ 1106 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1107 CTR0(KTR_PMC, #M ":" #N ":" #L ": " F); \ 1108 } while (0) 1109 #define PMCDBG1(M, N, L, F, p1) do { \ 1110 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1111 CTR1(KTR_PMC, #M ":" #N ":" #L ": " F, p1); \ 1112 } while (0) 1113 #define PMCDBG2(M, N, L, F, p1, p2) do { \ 1114 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1115 CTR2(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2); \ 1116 } while (0) 1117 #define PMCDBG3(M, N, L, F, p1, p2, p3) do { \ 1118 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1119 CTR3(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3); \ 1120 } while (0) 1121 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) do { \ 1122 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1123 CTR4(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4);\ 1124 } while (0) 1125 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) do { \ 1126 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1127 CTR5(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1128 p5); \ 1129 } while (0) 1130 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) do { \ 1131 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1132 CTR6(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1133 p5, p6); \ 1134 } while (0) 1135 1136 /* Major numbers */ 1137 #define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */ 1138 #define PMC_DEBUG_MAJ_CSW 1 /* context switches */ 1139 #define PMC_DEBUG_MAJ_LOG 2 /* logging */ 1140 #define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */ 1141 #define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */ 1142 #define PMC_DEBUG_MAJ_OWN 5 /* owner */ 1143 #define PMC_DEBUG_MAJ_PMC 6 /* pmc management */ 1144 #define PMC_DEBUG_MAJ_PRC 7 /* processes */ 1145 #define PMC_DEBUG_MAJ_SAM 8 /* sampling */ 1146 1147 /* Minor numbers */ 1148 1149 /* Common (8 bits) */ 1150 #define PMC_DEBUG_MIN_ALL 0 /* allocation */ 1151 #define PMC_DEBUG_MIN_REL 1 /* release */ 1152 #define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */ 1153 #define PMC_DEBUG_MIN_INI 3 /* init */ 1154 #define PMC_DEBUG_MIN_FND 4 /* find */ 1155 1156 /* MODULE */ 1157 #define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */ 1158 #define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */ 1159 1160 /* OWN */ 1161 #define PMC_DEBUG_MIN_ORM 8 /* owner remove */ 1162 #define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */ 1163 1164 /* PROCESSES */ 1165 #define PMC_DEBUG_MIN_TLK 8 /* link target */ 1166 #define PMC_DEBUG_MIN_TUL 9 /* unlink target */ 1167 #define PMC_DEBUG_MIN_EXT 10 /* process exit */ 1168 #define PMC_DEBUG_MIN_EXC 11 /* process exec */ 1169 #define PMC_DEBUG_MIN_FRK 12 /* process fork */ 1170 #define PMC_DEBUG_MIN_ATT 13 /* attach/detach */ 1171 #define PMC_DEBUG_MIN_SIG 14 /* signalling */ 1172 1173 /* CONTEXT SWITCHES */ 1174 #define PMC_DEBUG_MIN_SWI 8 /* switch in */ 1175 #define PMC_DEBUG_MIN_SWO 9 /* switch out */ 1176 1177 /* PMC */ 1178 #define PMC_DEBUG_MIN_REG 8 /* pmc register */ 1179 #define PMC_DEBUG_MIN_ALR 9 /* allocate row */ 1180 1181 /* MACHINE DEPENDENT LAYER */ 1182 #define PMC_DEBUG_MIN_REA 8 /* read */ 1183 #define PMC_DEBUG_MIN_WRI 9 /* write */ 1184 #define PMC_DEBUG_MIN_CFG 10 /* config */ 1185 #define PMC_DEBUG_MIN_STA 11 /* start */ 1186 #define PMC_DEBUG_MIN_STO 12 /* stop */ 1187 #define PMC_DEBUG_MIN_INT 13 /* interrupts */ 1188 1189 /* CPU */ 1190 #define PMC_DEBUG_MIN_BND 8 /* bind */ 1191 #define PMC_DEBUG_MIN_SEL 9 /* select */ 1192 1193 /* LOG */ 1194 #define PMC_DEBUG_MIN_GTB 8 /* get buf */ 1195 #define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */ 1196 #define PMC_DEBUG_MIN_FLS 10 /* flush */ 1197 #define PMC_DEBUG_MIN_SAM 11 /* sample */ 1198 #define PMC_DEBUG_MIN_CLO 12 /* close */ 1199 1200 #else 1201 #define __pmcdbg_used __unused 1202 #define PMCDBG0(M, N, L, F) /* nothing */ 1203 #define PMCDBG1(M, N, L, F, p1) 1204 #define PMCDBG2(M, N, L, F, p1, p2) 1205 #define PMCDBG3(M, N, L, F, p1, p2, p3) 1206 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) 1207 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) 1208 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) 1209 #endif 1210 1211 /* declare a dedicated memory pool */ 1212 MALLOC_DECLARE(M_PMC); 1213 1214 /* 1215 * Functions 1216 */ 1217 1218 struct pmc_mdep *pmc_md_initialize(void); /* MD init function */ 1219 void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */ 1220 int pmc_getrowdisp(int _ri); 1221 int pmc_process_interrupt(int _ring, struct pmc *_pm, struct trapframe *_tf); 1222 int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples, 1223 struct trapframe *_tf); 1224 int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples, 1225 struct trapframe *_tf); 1226 void pmc_restore_cpu_binding(struct pmc_binding *pb); 1227 void pmc_save_cpu_binding(struct pmc_binding *pb); 1228 void pmc_select_cpu(int cpu); 1229 struct pmc_mdep *pmc_mdep_alloc(int nclasses); 1230 void pmc_mdep_free(struct pmc_mdep *md); 1231 uint64_t pmc_rdtsc(void); 1232 #endif /* _KERNEL */ 1233 #endif /* _SYS_PMC_H_ */ 1234