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123

/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDDAGCombiner.cpp424 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference);
430 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
436 SDValue visitUADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
438 SDValue visitSADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
447 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
449 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
460 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
462 SDValue visitORLike(SDValue N0, SDValue N1, const SDLoc &DL);
573 SDValue N0,
575 SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0,
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HDTargetLowering.cpp752 SDValue N0 = Op.getOperand(0); in SimplifyMultipleUseDemandedBits() local
753 if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, DemandedElts, in SimplifyMultipleUseDemandedBits()
755 return N0; in SimplifyMultipleUseDemandedBits()
3229 SDValue N0 = Op.getOperand(0); in SimplifyDemandedVectorElts() local
3230 if (TLO.DAG.isGuaranteedNotToBeUndefOrPoison(N0, DemandedElts, in SimplifyDemandedVectorElts()
3232 return TLO.CombineTo(Op, N0); in SimplifyDemandedVectorElts()
3236 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && DemandedElts == 1) in SimplifyDemandedVectorElts()
3239 TLO.DAG.getFreeze(N0.getOperand(0)))); in SimplifyDemandedVectorElts()
3818 TargetLowering::buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, in buildLegalVectorShuffle() argument
3823 std::swap(N0, N1); in buildLegalVectorShuffle()
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/freebsd-13-stable/crypto/openssl/crypto/bn/asm/
HDarmv4-mont.pl293 my ($N0,$N1,$N2,$N3)=map("d$_",(4..7));
342 vld1.32 {$N0-$N3}, [$nptr]!
348 vmlal.u32 @ACC[0],$Ni,${N0}[0]
350 vmlal.u32 @ACC[1],$Ni,${N0}[1]
397 vmlal.u32 @ACC[0],$Ni,${N0}[0]
398 vmlal.u32 @ACC[1],$Ni,${N0}[1]
470 vld1.32 {$N0-$N3},[$nptr]!
490 vmlal.u32 @ACC[0],$Ni,${N0}[0]
492 vmlal.u32 @ACC[1],$Ni,${N0}[1]
527 vmlal.u32 @ACC[0],$Ni,${N0}[0]
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HDppc64-mont.pl172 $N0="f20"; $N1="f21"; $N2="f22"; $N3="f23";
394 lfd $N0,`$FRAME+96`($sp)
402 fcfid $N0,$N0
419 stfd $N0,40($nap_d) ; save n[j] in double format
441 fmadd $T0a,$N0,$na,$T0a
442 fmadd $T0b,$N0,$nb,$T0b
444 fmadd $T1a,$N0,$nc,$T1a
445 fmadd $T1b,$N0,$nd,$T1b
532 lfd $N0,`$FRAME+96`($sp)
540 fcfid $N0,$N0
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVISelDAGToDAG.cpp613 SDValue N0 = Node->getOperand(0); in tryShrinkShlLogicImm() local
626 SDValue Shift = N0; in tryShrinkShlLogicImm()
632 if (isInt<32>(Val) && N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in tryShrinkShlLogicImm()
633 N0.hasOneUse() && cast<VTSDNode>(N0.getOperand(1))->getVT() == MVT::i32) { in tryShrinkShlLogicImm()
635 Shift = N0.getOperand(0); in tryShrinkShlLogicImm()
691 SDValue N0 = Node->getOperand(0); in trySignedBitfieldExtract() local
692 if (!N0.hasOneUse()) in trySignedBitfieldExtract()
695 auto BitfieldExtract = [&](SDValue N0, unsigned Msb, unsigned Lsb, SDLoc DL, in trySignedBitfieldExtract()
697 return CurDAG->getMachineNode(RISCV::TH_EXT, DL, VT, N0.getOperand(0), in trySignedBitfieldExtract()
708 if (N0.getOpcode() == ISD::SHL) { in trySignedBitfieldExtract()
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HDRISCVISelLowering.cpp13161 SDValue N0 = N->getOperand(0); in transformAddShlImm() local
13163 if (N0->getOpcode() != ISD::SHL || N1->getOpcode() != ISD::SHL || in transformAddShlImm()
13164 !N0->hasOneUse() || !N1->hasOneUse()) in transformAddShlImm()
13168 auto *N0C = dyn_cast<ConstantSDNode>(N0->getOperand(1)); in transformAddShlImm()
13185 SDValue NS = (C0 < C1) ? N0->getOperand(0) : N1->getOperand(0); in transformAddShlImm()
13186 SDValue NL = (C0 > C1) ? N0->getOperand(0) : N1->getOperand(0); in transformAddShlImm()
13272 SDValue N0 = N->getOperand(0); in combineSelectAndUseCommutative() local
13274 if (SDValue Result = combineSelectAndUse(N, N0, N1, DAG, AllOnes, Subtarget)) in combineSelectAndUseCommutative()
13276 if (SDValue Result = combineSelectAndUse(N, N1, N0, DAG, AllOnes, Subtarget)) in combineSelectAndUseCommutative()
13306 SDValue N0 = N->getOperand(0); in transformAddImmMulImm() local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86ISelDAGToDAG.cpp1512 SDValue N0 = N->getOperand(0); in tryOptimizeRem8Extend() local
1515 if (!N0.isMachineOpcode() || in tryOptimizeRem8Extend()
1516 N0.getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG || in tryOptimizeRem8Extend()
1517 N0.getConstantOperandVal(1) != X86::sub_8bit) in tryOptimizeRem8Extend()
1523 SDValue N00 = N0.getOperand(0); in tryOptimizeRem8Extend()
1896 SDValue N0 = N.getOperand(0); in matchWrapper() local
1897 if (auto *G = dyn_cast<GlobalAddressSDNode>(N0)) { in matchWrapper()
1901 } else if (auto *CP = dyn_cast<ConstantPoolSDNode>(N0)) { in matchWrapper()
1906 } else if (auto *S = dyn_cast<ExternalSymbolSDNode>(N0)) { in matchWrapper()
1909 } else if (auto *S = dyn_cast<MCSymbolSDNode>(N0)) { in matchWrapper()
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HDX86ISelLowering.cpp5841 SDValue N0 = N.getOperand(0); in getFauxShuffleMask() local
5845 if (!getTargetConstantBitsFromNode(IsAndN ? N0 : N1, 8, UndefElts, EltBits, in getFauxShuffleMask()
5858 Ops.push_back(IsAndN ? N1 : N0); in getFauxShuffleMask()
5864 SDValue N0 = peekThroughBitcasts(N.getOperand(0)); in getFauxShuffleMask() local
5866 if (!N0.getValueType().isVector() || !N1.getValueType().isVector()) in getFauxShuffleMask()
5871 APInt Demand0 = APInt::getAllOnes(N0.getValueType().getVectorNumElements()); in getFauxShuffleMask()
5873 if (!getTargetShuffleInputs(N0, Demand0, SrcInputs0, SrcMask0, DAG, in getFauxShuffleMask()
5897 Ops.push_back(N0); in getFauxShuffleMask()
6085 SDValue N0 = N.getOperand(0); in getFauxShuffleMask() local
6087 assert(N0.getValueType().getVectorNumElements() == (NumElts / 2) && in getFauxShuffleMask()
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/M68k/
HDM68kISelDAGToDAG.cpp579 SDValue N0 = N.getOperand(0); in matchWrapper() local
590 if (auto *G = dyn_cast<GlobalAddressSDNode>(N0)) { in matchWrapper()
597 } else if (auto *CP = dyn_cast<ConstantPoolSDNode>(N0)) { in matchWrapper()
605 } else if (auto *S = dyn_cast<ExternalSymbolSDNode>(N0)) { in matchWrapper()
608 } else if (auto *S = dyn_cast<MCSymbolSDNode>(N0)) { in matchWrapper()
610 } else if (auto *J = dyn_cast<JumpTableSDNode>(N0)) { in matchWrapper()
613 } else if (auto *BA = dyn_cast<BlockAddressSDNode>(N0)) { in matchWrapper()
633 if (auto *G = dyn_cast<GlobalAddressSDNode>(N0)) { in matchWrapper()
637 } else if (auto *CP = dyn_cast<ConstantPoolSDNode>(N0)) { in matchWrapper()
642 } else if (auto *S = dyn_cast<ExternalSymbolSDNode>(N0)) { in matchWrapper()
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/freebsd-13-stable/contrib/ngatm/libngatm/
HDnet_in.fig57 4 1 0 50 0 14 12 0.0000 4 120 210 5400 720 N0\001
74 4 1 0 50 0 14 12 0.0000 4 120 210 5400 7470 N0\001
HDnet_out.fig58 4 1 0 50 0 14 12 0.0000 4 120 210 5400 720 N0\001
76 4 1 0 50 0 14 12 0.0000 4 120 210 5400 8595 N0\001
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp3523 SDValue N0 = Op.getOperand(0); in LowerFP_TO_FP16() local
3526 if (N0.getValueType() == MVT::f32) in LowerFP_TO_FP16()
3527 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0); in LowerFP_TO_FP16()
3534 assert(N0.getSimpleValueType() == MVT::f64); in LowerFP_TO_FP16()
3542 SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0); in LowerFP_TO_FP16()
3910 SDValue N0 = N->getOperand(0); in performAssertSZExtCombine() local
3914 if (N0.getOpcode() == ISD::TRUNCATE) { in performAssertSZExtCombine()
3919 SDValue Src = N0.getOperand(0); in performAssertSZExtCombine()
4235 SDValue N0, SDValue N1, unsigned Size, bool Signed) { in getMul24() argument
4238 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
[all …]
HDAMDGPUISelDAGToDAG.cpp732 SDValue &N0, SDValue &N1) { in getBaseWithOffsetUsingSplitOR() argument
753 N0 = BaseLo.getOperand(0).getOperand(0); in getBaseWithOffsetUsingSplitOR()
1085 SDValue N0 = Addr.getOperand(0); in SelectDS1Addr1Offset() local
1088 if (isDSOffsetLegal(N0, C1->getSExtValue())) { in SelectDS1Addr1Offset()
1090 Base = N0; in SelectDS1Addr1Offset()
1264 SDValue N0 = Addr.getOperand(0); in SelectDSReadWrite2() local
1271 if (isDSOffset2Legal(N0, OffsetValue0, OffsetValue1, Size)) { in SelectDSReadWrite2()
1272 Base = N0; in SelectDSReadWrite2()
1357 SDValue N0 = Addr; in SelectMUBUF() local
1361 N0 = Addr.getOperand(0); in SelectMUBUF()
[all …]
HDSIISelLowering.h212 const SDNode *N0, const SDNode *N1) const;
521 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0,
524 bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
HDMSP430ISelDAGToDAG.cpp151 SDValue N0 = N.getOperand(0); in MatchWrapper() local
153 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { in MatchWrapper()
157 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) { in MatchWrapper()
162 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) { in MatchWrapper()
165 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) { in MatchWrapper()
169 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress(); in MatchWrapper()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMISelLowering.cpp9607 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubSExt() local
9609 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubSExt()
9610 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
9618 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubZExt() local
9620 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubZExt()
9621 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
9632 SDNode *N0 = Op.getOperand(0).getNode(); in LowerMUL() local
9636 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
9641 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
9648 if (isN1SExt && isAddSubSExt(N0, DAG)) { in LowerMUL()
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDSelectionDAG.h1968 OverflowKind computeOverflowForSignedAdd(SDValue N0, SDValue N1) const;
1971 OverflowKind computeOverflowForUnsignedAdd(SDValue N0, SDValue N1) const;
1974 OverflowKind computeOverflowForAdd(bool IsSigned, SDValue N0,
1976 return IsSigned ? computeOverflowForSignedAdd(N0, N1)
1977 : computeOverflowForUnsignedAdd(N0, N1);
1981 bool willNotOverflowAdd(bool IsSigned, SDValue N0, SDValue N1) const {
1982 return computeOverflowForAdd(IsSigned, N0, N1) == OFK_Never;
1986 OverflowKind computeOverflowForSignedSub(SDValue N0, SDValue N1) const;
1989 OverflowKind computeOverflowForUnsignedSub(SDValue N0, SDValue N1) const;
1992 OverflowKind computeOverflowForSub(bool IsSigned, SDValue N0,
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HDTargetLowering.h3792 virtual bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, in isReassocProfitable() argument
3794 return N0.hasOneUse(); in isReassocProfitable()
3803 virtual bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0, in isReassocProfitable() argument
3805 return MRI.hasOneNonDBGUse(N0); in isReassocProfitable()
4182 SDValue buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0,
4252 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
5593 SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
5595 SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
5598 SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
5605 EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp575 SDValue N0 = Op.getOperand(0); in isADDADDMUL() local
579 if (N0.getOpcode() == ISD::ADD) { in isADDADDMUL()
580 AddOp = N0; in isADDADDMUL()
584 OtherOp = N0; in isADDADDMUL()
1537 SDValue N0 = N->getOperand(0); in PerformDAGCombine() local
1540 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); in PerformDAGCombine()
1542 EVT VT = N0.getValueType(); in PerformDAGCombine()
1546 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2); in PerformDAGCombine()
1565 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2); in PerformDAGCombine()
1573 SDValue N0 = N->getOperand(0); in PerformDAGCombine() local
[all …]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp5070 SDValue N0 = N.getOperand(0); in isAddSubSExt() local
5072 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubSExt()
5073 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
5081 SDValue N0 = N.getOperand(0); in isAddSubZExt() local
5083 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubZExt()
5084 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
5215 static unsigned selectUmullSmull(SDValue &N0, SDValue &N1, SelectionDAG &DAG, in selectUmullSmull() argument
5217 bool IsN0SExt = isSignExtended(N0, DAG); in selectUmullSmull()
5222 bool IsN0ZExt = isZeroExtended(N0, DAG); in selectUmullSmull()
5230 !isExtendedBUILD_VECTOR(N0, DAG, false) && in selectUmullSmull()
[all …]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp5298 PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, in PerformADDCombineWithOperands() argument
5300 EVT VT = N0.getValueType(); in PerformADDCombineWithOperands()
5306 if (!N0.getNode()->hasOneUse()) in PerformADDCombineWithOperands()
5311 if (N0.getOpcode() == ISD::MUL) in PerformADDCombineWithOperands()
5312 return DCI.DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT, N0.getOperand(0), in PerformADDCombineWithOperands()
5313 N0.getOperand(1), N1); in PerformADDCombineWithOperands()
5318 if (N0.getOpcode() == ISD::SELECT) { in PerformADDCombineWithOperands()
5320 if (isConstZero(N0->getOperand(1))) in PerformADDCombineWithOperands()
5322 else if (isConstZero(N0->getOperand(2))) in PerformADDCombineWithOperands()
5327 SDValue M = N0->getOperand((ZeroOpNum == 1) ? 2 : 1); in PerformADDCombineWithOperands()
[all …]
/freebsd-13-stable/contrib/pam_modules/pam_passwdqc/
HDREADME21 min=N0,N1,N2,N3,N4 [min=disabled,24,12,8,7]
28 N0 is used for passwords consisting of characters from one character
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
HDSystemZISelLowering.cpp6672 SDValue N0 = N->getOperand(0); in combineZERO_EXTEND() local
6674 if (N0.getOpcode() == SystemZISD::SELECT_CCMASK) { in combineZERO_EXTEND()
6675 auto *TrueOp = dyn_cast<ConstantSDNode>(N0.getOperand(0)); in combineZERO_EXTEND()
6676 auto *FalseOp = dyn_cast<ConstantSDNode>(N0.getOperand(1)); in combineZERO_EXTEND()
6678 SDLoc DL(N0); in combineZERO_EXTEND()
6681 N0.getOperand(2), N0.getOperand(3), N0.getOperand(4) }; in combineZERO_EXTEND()
6684 if (!N0.hasOneUse()) { in combineZERO_EXTEND()
6686 DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), NewSelect); in combineZERO_EXTEND()
6687 DCI.CombineTo(N0.getNode(), TruncSelect); in combineZERO_EXTEND()
6695 if (N0.getOpcode() == ISD::XOR && in combineZERO_EXTEND()
[all …]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
HDLanaiISelLowering.cpp1445 SDValue N0 = N->getOperand(0); in combineSelectAndUseCommutative() local
1447 if (N0.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
1448 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes)) in combineSelectAndUseCommutative()
1451 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes)) in combineSelectAndUseCommutative()
1459 SDValue N0 = N->getOperand(0); in PerformSUBCombine() local
1464 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false)) in PerformSUBCombine()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/LoongArch/
HDLoongArchISelLowering.cpp3235 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); in performORCombine() local
3255 if (N0.getOpcode() == ISD::AND && in performORCombine()
3256 (CN0 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) && in performORCombine()
3266 return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0), in performORCombine()
3277 if (N0.getOpcode() == ISD::AND && in performORCombine()
3278 (CN0 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) && in performORCombine()
3288 return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0), in performORCombine()
3300 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND && in performORCombine()
3301 (CN0 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) && in performORCombine()
3307 return DAG.getNode(LoongArchISD::BSTRINS, DL, ValTy, N0.getOperand(0), in performORCombine()
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