1 /*
2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Authors: Marian Choy
3 * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy
4 * Support: freebsdraid@avagotech.com
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer. 2. Redistributions
12 * in binary form must reproduce the above copyright notice, this list of
13 * conditions and the following disclaimer in the documentation and/or other
14 * materials provided with the distribution. 3. Neither the name of the
15 * <ORGANIZATION> nor the names of its contributors may be used to endorse or
16 * promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * The views and conclusions contained in the software and documentation are
32 * those of the authors and should not be interpreted as representing
33 * official policies,either expressed or implied, of the FreeBSD Project.
34 *
35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621
36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
37 *
38 */
39
40 #include <sys/cdefs.h>
41 #ifndef MRSAS_H
42 #define MRSAS_H
43
44 #include <sys/param.h> /* defines used in kernel.h */
45 #include <sys/module.h>
46 #include <sys/systm.h>
47 #include <sys/proc.h>
48 #include <sys/errno.h>
49 #include <sys/kernel.h> /* types used in module initialization */
50 #include <sys/conf.h> /* cdevsw struct */
51 #include <sys/uio.h> /* uio struct */
52 #include <sys/malloc.h>
53 #include <sys/bus.h> /* structs, prototypes for pci bus
54 * stuff */
55 #include <sys/rman.h>
56 #include <sys/types.h>
57 #include <sys/lock.h>
58 #include <sys/mutex.h>
59 #include <sys/sema.h>
60 #include <sys/sysctl.h>
61 #include <sys/stat.h>
62 #include <sys/taskqueue.h>
63 #include <sys/poll.h>
64 #include <sys/selinfo.h>
65
66 #include <machine/bus.h>
67 #include <machine/resource.h>
68 #include <machine/atomic.h>
69
70 #include <dev/pci/pcivar.h> /* For pci_get macros! */
71 #include <dev/pci/pcireg.h>
72
73 #define IOCTL_SEMA_DESCRIPTION "mrsas semaphore for MFI pool"
74
75 /*
76 * Device IDs and PCI
77 */
78 #define MRSAS_TBOLT 0x005b
79 #define MRSAS_INVADER 0x005d
80 #define MRSAS_FURY 0x005f
81 #define MRSAS_INTRUDER 0x00ce
82 #define MRSAS_INTRUDER_24 0x00cf
83 #define MRSAS_CUTLASS_52 0x0052
84 #define MRSAS_CUTLASS_53 0x0053
85 /* Gen3.5 Conroller */
86 #define MRSAS_VENTURA 0x0014
87 #define MRSAS_CRUSADER 0x0015
88 #define MRSAS_HARPOON 0x0016
89 #define MRSAS_TOMCAT 0x0017
90 #define MRSAS_VENTURA_4PORT 0x001B
91 #define MRSAS_CRUSADER_4PORT 0x001C
92 #define MRSAS_AERO_10E0 0x10E0
93 #define MRSAS_AERO_10E1 0x10E1
94 #define MRSAS_AERO_10E2 0x10E2
95 #define MRSAS_AERO_10E3 0x10E3
96 #define MRSAS_AERO_10E4 0x10E4
97 #define MRSAS_AERO_10E5 0x10E5
98 #define MRSAS_AERO_10E6 0x10E6
99 #define MRSAS_AERO_10E7 0x10E7
100
101 /*
102 * Firmware State Defines
103 */
104 #define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF
105 #define MRSAS_FWSTATE_SGE_MASK 0x00FF0000
106 #define MRSAS_FW_STATE_CHNG_INTERRUPT 1
107
108 /*
109 * Message Frame Defines
110 */
111 #define MRSAS_SENSE_LEN 96
112 #define MRSAS_FUSION_MAX_RESET_TRIES 3
113
114 /*
115 * Miscellaneous Defines
116 */
117 #define BYTE_ALIGNMENT 1
118 #define MRSAS_MAX_NAME_LENGTH 32
119 #define MRSAS_VERSION "07.709.04.00-fbsd"
120 #define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF
121 #define MRSAS_DEFAULT_TIMEOUT 0x14 /* Temporarily set */
122 #define DONE 0
123 #define MRSAS_PAGE_SIZE 4096
124 #define MRSAS_RESET_NOTICE_INTERVAL 5
125 #define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */
126 #define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */
127 #define THRESHOLD_REPLY_COUNT 50
128 #define MAX_MSIX_COUNT 128
129
130 #define MAX_STREAMS_TRACKED 8
131 #define MR_STREAM_BITMAP 0x76543210
132 #define BITS_PER_INDEX_STREAM 4 /* number of bits per index in U32 TrackStream */
133 #define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1)
134 #define ZERO_LAST_STREAM 0x0fffffff
135
136 /*
137 * Boolean types
138 */
139 #if (__FreeBSD_version < 901000)
140 typedef enum _boolean {
141 false, true
142 } boolean;
143
144 #endif
145 enum err {
146 SUCCESS, FAIL
147 };
148
149 MALLOC_DECLARE(M_MRSAS);
150 SYSCTL_DECL(_hw_mrsas);
151
152 #define MRSAS_INFO (1 << 0)
153 #define MRSAS_TRACE (1 << 1)
154 #define MRSAS_FAULT (1 << 2)
155 #define MRSAS_OCR (1 << 3)
156 #define MRSAS_TOUT MRSAS_OCR
157 #define MRSAS_AEN (1 << 4)
158 #define MRSAS_PRL11 (1 << 5)
159
160 #define mrsas_dprint(sc, level, msg, args...) \
161 do { \
162 if (sc->mrsas_debug & level) \
163 device_printf(sc->mrsas_dev, msg, ##args); \
164 } while (0)
165
166 #define le32_to_cpus(x) do { *((u_int32_t *)(x)) = le32toh((*(u_int32_t *)x)); } while (0)
167 #define le16_to_cpus(x) do { *((u_int16_t *)(x)) = le16toh((*(u_int16_t *)x)); } while (0)
168
169 /****************************************************************************
170 * Raid Context structure which describes MegaRAID specific IO Paramenters
171 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
172 ****************************************************************************/
173
174 typedef struct _RAID_CONTEXT {
175 #if _BYTE_ORDER == _LITTLE_ENDIAN
176 u_int8_t Type:4;
177 u_int8_t nseg:4;
178 #else
179 u_int8_t nseg:4;
180 u_int8_t Type:4;
181 #endif
182 u_int8_t resvd0;
183 u_int16_t timeoutValue;
184 u_int8_t regLockFlags;
185 u_int8_t resvd1;
186 u_int16_t VirtualDiskTgtId;
187 u_int64_t regLockRowLBA;
188 u_int32_t regLockLength;
189 u_int16_t nextLMId;
190 u_int8_t exStatus;
191 u_int8_t status;
192 u_int8_t RAIDFlags;
193 u_int8_t numSGE;
194 u_int16_t configSeqNum;
195 u_int8_t spanArm;
196 u_int8_t priority; /* 0x1D MR_PRIORITY_RANGE */
197 u_int8_t numSGEExt; /* 0x1E 1M IO support */
198 u_int8_t resvd2; /* 0x1F */
199 } RAID_CONTEXT;
200
201 /*
202 * Raid Context structure which describes ventura MegaRAID specific IO Paramenters
203 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
204 */
205 typedef struct _RAID_CONTEXT_G35 {
206 #if _BYTE_ORDER == _LITTLE_ENDIAN
207 u_int16_t Type:4;
208 u_int16_t nseg:4;
209 u_int16_t resvd0:8;
210 #else
211 u_int16_t resvd0:8;
212 u_int16_t nseg:4;
213 u_int16_t Type:4;
214 #endif
215 u_int16_t timeoutValue;
216 union {
217 struct {
218 #if _BYTE_ORDER == _LITTLE_ENDIAN
219 u_int16_t reserved:1;
220 u_int16_t sld:1;
221 u_int16_t c2f:1;
222 u_int16_t fwn:1;
223 u_int16_t sqn:1;
224 u_int16_t sbs:1;
225 u_int16_t rw:1;
226 u_int16_t log:1;
227 u_int16_t cpuSel:4;
228 u_int16_t setDivert:4;
229 #else
230 u_int16_t setDivert:4;
231 u_int16_t cpuSel:4;
232 u_int16_t log:1;
233 u_int16_t rw:1;
234 u_int16_t sbs:1;
235 u_int16_t sqn:1;
236 u_int16_t fwn:1;
237 u_int16_t c2f:1;
238 u_int16_t sld:1;
239 u_int16_t reserved:1;
240 #endif
241 } bits;
242 u_int16_t s;
243 } routingFlags;
244 u_int16_t VirtualDiskTgtId;
245 u_int64_t regLockRowLBA;
246 u_int32_t regLockLength;
247 union {
248 u_int16_t nextLMId;
249 u_int16_t peerSMID;
250 } smid;
251 u_int8_t exStatus;
252 u_int8_t status;
253 u_int8_t RAIDFlags;
254 u_int8_t spanArm;
255 u_int16_t configSeqNum;
256 #if _BYTE_ORDER == _LITTLE_ENDIAN
257 u_int16_t numSGE:12;
258 u_int16_t reserved:3;
259 u_int16_t streamDetected:1;
260 #else
261 u_int16_t streamDetected:1;
262 u_int16_t reserved:3;
263 u_int16_t numSGE:12;
264 #endif
265 u_int8_t resvd2[2];
266 } RAID_CONTEXT_G35;
267
268 typedef union _RAID_CONTEXT_UNION {
269 RAID_CONTEXT raid_context;
270 RAID_CONTEXT_G35 raid_context_g35;
271 } RAID_CONTEXT_UNION, *PRAID_CONTEXT_UNION;
272
273 /*************************************************************************
274 * MPI2 Defines
275 ************************************************************************/
276
277 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
278 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
279 #define MPI2_VERSION_MAJOR (0x02)
280 #define MPI2_VERSION_MINOR (0x00)
281 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
282 #define MPI2_VERSION_MAJOR_SHIFT (8)
283 #define MPI2_VERSION_MINOR_MASK (0x00FF)
284 #define MPI2_VERSION_MINOR_SHIFT (0)
285 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
286 MPI2_VERSION_MINOR)
287 #define MPI2_HEADER_VERSION_UNIT (0x10)
288 #define MPI2_HEADER_VERSION_DEV (0x00)
289 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
290 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
291 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
292 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
293 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
294 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
295 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
296 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
297 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
298 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
299 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
300 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
301 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
302 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
303 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03)
304 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06)
305 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
306 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
307 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
308 #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
309 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
310 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
311 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
312 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
313 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
314 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
315 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
316 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
317 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
318 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
319 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
320 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
321
322 #ifndef MPI2_POINTER
323 #define MPI2_POINTER *
324 #endif
325
326 /***************************************
327 * MPI2 Structures
328 ***************************************/
329
330 typedef struct _MPI25_IEEE_SGE_CHAIN64 {
331 u_int64_t Address;
332 u_int32_t Length;
333 u_int16_t Reserved1;
334 u_int8_t NextChainOffset;
335 u_int8_t Flags;
336 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
337 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
338
339 typedef struct _MPI2_SGE_SIMPLE_UNION {
340 u_int32_t FlagsLength;
341 union {
342 u_int32_t Address32;
343 u_int64_t Address64;
344 } u;
345 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
346 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
347
348 typedef struct {
349 u_int8_t CDB[20]; /* 0x00 */
350 u_int32_t PrimaryReferenceTag; /* 0x14 */
351 u_int16_t PrimaryApplicationTag;/* 0x18 */
352 u_int16_t PrimaryApplicationTagMask; /* 0x1A */
353 u_int32_t TransferLength; /* 0x1C */
354 } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32,
355 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t;
356
357 typedef struct _MPI2_SGE_CHAIN_UNION {
358 u_int16_t Length;
359 u_int8_t NextChainOffset;
360 u_int8_t Flags;
361 union {
362 u_int32_t Address32;
363 u_int64_t Address64;
364 } u;
365 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
366 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
367
368 typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
369 u_int32_t Address;
370 u_int32_t FlagsLength;
371 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
372 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
373 typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
374 u_int64_t Address;
375 u_int32_t Length;
376 u_int16_t Reserved1;
377 u_int8_t Reserved2;
378 u_int8_t Flags;
379 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
380 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
381
382 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
383 MPI2_IEEE_SGE_SIMPLE32 Simple32;
384 MPI2_IEEE_SGE_SIMPLE64 Simple64;
385 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
386 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
387
388 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
389 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
390
391 typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
392 MPI2_IEEE_SGE_CHAIN32 Chain32;
393 MPI2_IEEE_SGE_CHAIN64 Chain64;
394 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
395 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
396
397 typedef union _MPI2_SGE_IO_UNION {
398 MPI2_SGE_SIMPLE_UNION MpiSimple;
399 MPI2_SGE_CHAIN_UNION MpiChain;
400 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
401 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
402 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
403 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
404
405 typedef union {
406 u_int8_t CDB32[32];
407 MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
408 MPI2_SGE_SIMPLE_UNION SGE;
409 } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION,
410 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t;
411
412 /****************************************************************************
413 * * SCSI Task Management messages
414 * ****************************************************************************/
415
416 /*SCSI Task Management Request Message */
417 typedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST {
418 u_int16_t DevHandle; /*0x00 */
419 u_int8_t ChainOffset; /*0x02 */
420 u_int8_t Function; /*0x03 */
421 u_int8_t Reserved1; /*0x04 */
422 u_int8_t TaskType; /*0x05 */
423 u_int8_t Reserved2; /*0x06 */
424 u_int8_t MsgFlags; /*0x07 */
425 u_int8_t VP_ID; /*0x08 */
426 u_int8_t VF_ID; /*0x09 */
427 u_int16_t Reserved3; /*0x0A */
428 u_int8_t LUN[8]; /*0x0C */
429 u_int32_t Reserved4[7]; /*0x14 */
430 u_int16_t TaskMID; /*0x30 */
431 u_int16_t Reserved5; /*0x32 */
432 } MPI2_SCSI_TASK_MANAGE_REQUEST;
433
434 /*SCSI Task Management Reply Message */
435 typedef struct _MPI2_SCSI_TASK_MANAGE_REPLY {
436 u_int16_t DevHandle; /*0x00 */
437 u_int8_t MsgLength; /*0x02 */
438 u_int8_t Function; /*0x03 */
439 u_int8_t ResponseCode; /*0x04 */
440 u_int8_t TaskType; /*0x05 */
441 u_int8_t Reserved1; /*0x06 */
442 u_int8_t MsgFlags; /*0x07 */
443 u_int8_t VP_ID; /*0x08 */
444 u_int8_t VF_ID; /*0x09 */
445 u_int16_t Reserved2; /*0x0A */
446 u_int16_t Reserved3; /*0x0C */
447 u_int16_t IOCStatus; /*0x0E */
448 u_int32_t IOCLogInfo; /*0x10 */
449 u_int32_t TerminationCount; /*0x14 */
450 u_int32_t ResponseInfo; /*0x18 */
451 } MPI2_SCSI_TASK_MANAGE_REPLY;
452
453 typedef struct _MR_TM_REQUEST {
454 char request[128];
455 } MR_TM_REQUEST;
456
457 typedef struct _MR_TM_REPLY {
458 char reply[128];
459 } MR_TM_REPLY;
460
461 /* SCSI Task Management Request Message */
462 typedef struct _MR_TASK_MANAGE_REQUEST {
463 /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */
464 MR_TM_REQUEST TmRequest;
465 union {
466 struct {
467 #if _BYTE_ORDER == _LITTLE_ENDIAN
468 u_int32_t isTMForLD:1;
469 u_int32_t isTMForPD:1;
470 u_int32_t reserved1:30;
471 #else
472 u_int32_t reserved1:30;
473 u_int32_t isTMForPD:1;
474 u_int32_t isTMForLD:1;
475 #endif
476 u_int32_t reserved2;
477 } tmReqFlags;
478 MR_TM_REPLY TMReply;
479 } uTmReqReply;
480 } MR_TASK_MANAGE_REQUEST;
481
482 /* TaskType values */
483 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
484 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
485 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
486 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
487 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
488 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
489 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
490 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
491 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
492
493 /* ResponseCode values */
494 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
495 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
496 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
497 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
498 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
499 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
500 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
501 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
502
503 /*
504 * RAID SCSI IO Request Message Total SGE count will be one less than
505 * _MPI2_SCSI_IO_REQUEST
506 */
507 typedef struct _MPI2_RAID_SCSI_IO_REQUEST {
508 u_int16_t DevHandle; /* 0x00 */
509 u_int8_t ChainOffset; /* 0x02 */
510 u_int8_t Function; /* 0x03 */
511 u_int16_t Reserved1; /* 0x04 */
512 u_int8_t Reserved2; /* 0x06 */
513 u_int8_t MsgFlags; /* 0x07 */
514 u_int8_t VP_ID; /* 0x08 */
515 u_int8_t VF_ID; /* 0x09 */
516 u_int16_t Reserved3; /* 0x0A */
517 u_int32_t SenseBufferLowAddress;/* 0x0C */
518 u_int16_t SGLFlags; /* 0x10 */
519 u_int8_t SenseBufferLength; /* 0x12 */
520 u_int8_t Reserved4; /* 0x13 */
521 u_int8_t SGLOffset0; /* 0x14 */
522 u_int8_t SGLOffset1; /* 0x15 */
523 u_int8_t SGLOffset2; /* 0x16 */
524 u_int8_t SGLOffset3; /* 0x17 */
525 u_int32_t SkipCount; /* 0x18 */
526 u_int32_t DataLength; /* 0x1C */
527 u_int32_t BidirectionalDataLength; /* 0x20 */
528 u_int16_t IoFlags; /* 0x24 */
529 u_int16_t EEDPFlags; /* 0x26 */
530 u_int32_t EEDPBlockSize; /* 0x28 */
531 u_int32_t SecondaryReferenceTag;/* 0x2C */
532 u_int16_t SecondaryApplicationTag; /* 0x30 */
533 u_int16_t ApplicationTagTranslationMask; /* 0x32 */
534 u_int8_t LUN[8]; /* 0x34 */
535 u_int32_t Control; /* 0x3C */
536 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
537 RAID_CONTEXT_UNION RaidContext; /* 0x60 */
538 MPI2_SGE_IO_UNION SGL; /* 0x80 */
539 } MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST,
540 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t;
541
542 /*
543 * MPT RAID MFA IO Descriptor.
544 */
545 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR {
546 u_int32_t RequestFlags:8;
547 u_int32_t MessageAddress1:24; /* bits 31:8 */
548 u_int32_t MessageAddress2; /* bits 61:32 */
549 } MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR, *PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR;
550
551 /* Default Request Descriptor */
552 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
553 u_int8_t RequestFlags; /* 0x00 */
554 u_int8_t MSIxIndex; /* 0x01 */
555 u_int16_t SMID; /* 0x02 */
556 u_int16_t LMID; /* 0x04 */
557 u_int16_t DescriptorTypeDependent; /* 0x06 */
558 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
559
560 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
561 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
562
563 /* High Priority Request Descriptor */
564 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
565 u_int8_t RequestFlags; /* 0x00 */
566 u_int8_t MSIxIndex; /* 0x01 */
567 u_int16_t SMID; /* 0x02 */
568 u_int16_t LMID; /* 0x04 */
569 u_int16_t Reserved1; /* 0x06 */
570 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
571
572 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
573 Mpi2HighPriorityRequestDescriptor_t, MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
574
575 /* SCSI IO Request Descriptor */
576 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
577 u_int8_t RequestFlags; /* 0x00 */
578 u_int8_t MSIxIndex; /* 0x01 */
579 u_int16_t SMID; /* 0x02 */
580 u_int16_t LMID; /* 0x04 */
581 u_int16_t DevHandle; /* 0x06 */
582 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
583
584 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
585 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
586
587 /* SCSI Target Request Descriptor */
588 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
589 u_int8_t RequestFlags; /* 0x00 */
590 u_int8_t MSIxIndex; /* 0x01 */
591 u_int16_t SMID; /* 0x02 */
592 u_int16_t LMID; /* 0x04 */
593 u_int16_t IoIndex; /* 0x06 */
594 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
595
596 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
597 Mpi2SCSITargetRequestDescriptor_t, MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
598
599 /* RAID Accelerator Request Descriptor */
600 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
601 u_int8_t RequestFlags; /* 0x00 */
602 u_int8_t MSIxIndex; /* 0x01 */
603 u_int16_t SMID; /* 0x02 */
604 u_int16_t LMID; /* 0x04 */
605 u_int16_t Reserved; /* 0x06 */
606 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
607
608 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
609 Mpi2RAIDAcceleratorRequestDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
610
611 /* union of Request Descriptors */
612 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION {
613 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
614 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
615 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
616 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
617 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
618 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
619 union {
620 struct {
621 u_int32_t low;
622 u_int32_t high;
623 } u;
624 u_int64_t Words;
625 } addr;
626 } MRSAS_REQUEST_DESCRIPTOR_UNION;
627
628 /* Default Reply Descriptor */
629 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
630 u_int8_t ReplyFlags; /* 0x00 */
631 u_int8_t MSIxIndex; /* 0x01 */
632 u_int16_t DescriptorTypeDependent1; /* 0x02 */
633 u_int32_t DescriptorTypeDependent2; /* 0x04 */
634 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
635 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
636
637 /* Address Reply Descriptor */
638 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
639 u_int8_t ReplyFlags; /* 0x00 */
640 u_int8_t MSIxIndex; /* 0x01 */
641 u_int16_t SMID; /* 0x02 */
642 u_int32_t ReplyFrameAddress; /* 0x04 */
643 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
644 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
645
646 /* SCSI IO Success Reply Descriptor */
647 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
648 u_int8_t ReplyFlags; /* 0x00 */
649 u_int8_t MSIxIndex; /* 0x01 */
650 u_int16_t SMID; /* 0x02 */
651 u_int16_t TaskTag; /* 0x04 */
652 u_int16_t Reserved1; /* 0x06 */
653 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
654
655 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
656 Mpi2SCSIIOSuccessReplyDescriptor_t, MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
657
658 /* TargetAssist Success Reply Descriptor */
659 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
660 u_int8_t ReplyFlags; /* 0x00 */
661 u_int8_t MSIxIndex; /* 0x01 */
662 u_int16_t SMID; /* 0x02 */
663 u_int8_t SequenceNumber; /* 0x04 */
664 u_int8_t Reserved1; /* 0x05 */
665 u_int16_t IoIndex; /* 0x06 */
666 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
667
668 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
669 Mpi2TargetAssistSuccessReplyDescriptor_t, MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
670
671 /* Target Command Buffer Reply Descriptor */
672 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
673 u_int8_t ReplyFlags; /* 0x00 */
674 u_int8_t MSIxIndex; /* 0x01 */
675 u_int8_t VP_ID; /* 0x02 */
676 u_int8_t Flags; /* 0x03 */
677 u_int16_t InitiatorDevHandle; /* 0x04 */
678 u_int16_t IoIndex; /* 0x06 */
679 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
680
681 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
682 Mpi2TargetCommandBufferReplyDescriptor_t, MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
683
684 /* RAID Accelerator Success Reply Descriptor */
685 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
686 u_int8_t ReplyFlags; /* 0x00 */
687 u_int8_t MSIxIndex; /* 0x01 */
688 u_int16_t SMID; /* 0x02 */
689 u_int32_t Reserved; /* 0x04 */
690 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
691
692 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
693 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
694
695 /* union of Reply Descriptors */
696 typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
697 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
698 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
699 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
700 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
701 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
702 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
703 u_int64_t Words;
704 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
705 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
706
707 typedef union {
708 volatile unsigned int val;
709 unsigned int val_rdonly;
710 } mrsas_atomic_t;
711
712 #define mrsas_atomic_read(v) atomic_load_acq_int(&(v)->val)
713 #define mrsas_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i)
714 #define mrsas_atomic_dec(v) atomic_subtract_int(&(v)->val, 1)
715 #define mrsas_atomic_inc(v) atomic_add_int(&(v)->val, 1)
716
717 static inline int
mrsas_atomic_inc_return(mrsas_atomic_t * v)718 mrsas_atomic_inc_return(mrsas_atomic_t *v)
719 {
720 return 1 + atomic_fetchadd_int(&(v)->val, 1);
721 }
722
723 /* IOCInit Request message */
724 typedef struct _MPI2_IOC_INIT_REQUEST {
725 u_int8_t WhoInit; /* 0x00 */
726 u_int8_t Reserved1; /* 0x01 */
727 u_int8_t ChainOffset; /* 0x02 */
728 u_int8_t Function; /* 0x03 */
729 u_int16_t Reserved2; /* 0x04 */
730 u_int8_t Reserved3; /* 0x06 */
731 u_int8_t MsgFlags; /* 0x07 */
732 u_int8_t VP_ID; /* 0x08 */
733 u_int8_t VF_ID; /* 0x09 */
734 u_int16_t Reserved4; /* 0x0A */
735 u_int16_t MsgVersion; /* 0x0C */
736 u_int16_t HeaderVersion; /* 0x0E */
737 u_int32_t Reserved5; /* 0x10 */
738 u_int16_t Reserved6; /* 0x14 */
739 u_int8_t HostPageSize; /* 0x16 */
740 u_int8_t HostMSIxVectors; /* 0x17 */
741 u_int16_t Reserved8; /* 0x18 */
742 u_int16_t SystemRequestFrameSize; /* 0x1A */
743 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */
744 u_int16_t ReplyFreeQueueDepth; /* 0x1E */
745 u_int32_t SenseBufferAddressHigh; /* 0x20 */
746 u_int32_t SystemReplyAddressHigh; /* 0x24 */
747 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */
748 u_int64_t ReplyDescriptorPostQueueAddress; /* 0x30 */
749 u_int64_t ReplyFreeQueueAddress;/* 0x38 */
750 u_int64_t TimeStamp; /* 0x40 */
751 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
752 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
753
754 /*
755 * MR private defines
756 */
757 #define MR_PD_INVALID 0xFFFF
758 #define MR_DEVHANDLE_INVALID 0xFFFF
759 #define MAX_SPAN_DEPTH 8
760 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
761 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
762 #define MAX_ROW_SIZE 32
763 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
764 #define MAX_LOGICAL_DRIVES 64
765 #define MAX_LOGICAL_DRIVES_EXT 256
766 #define MAX_LOGICAL_DRIVES_DYN 512
767
768 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
769 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
770
771 #define MAX_ARRAYS 128
772 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
773
774 #define MAX_ARRAYS_EXT 256
775 #define MAX_API_ARRAYS_EXT MAX_ARRAYS_EXT
776 #define MAX_API_ARRAYS_DYN 512
777
778 #define MAX_PHYSICAL_DEVICES 256
779 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
780 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512
781 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
782 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102
783 #define MR_DCMD_PD_MFI_TASK_MGMT 0x0200e100
784
785 #define MR_DCMD_PD_GET_INFO 0x02020000
786 #define MRSAS_MAX_PD_CHANNELS 1
787 #define MRSAS_MAX_LD_CHANNELS 1
788 #define MRSAS_MAX_DEV_PER_CHANNEL 256
789 #define MRSAS_DEFAULT_INIT_ID -1
790 #define MRSAS_MAX_LUN 8
791 #define MRSAS_DEFAULT_CMD_PER_LUN 256
792 #define MRSAS_MAX_PD (MRSAS_MAX_PD_CHANNELS * \
793 MRSAS_MAX_DEV_PER_CHANNEL)
794 #define MRSAS_MAX_LD_IDS (MRSAS_MAX_LD_CHANNELS * \
795 MRSAS_MAX_DEV_PER_CHANNEL)
796
797 #define VD_EXT_DEBUG 0
798 #define TM_DEBUG 1
799
800 /*******************************************************************
801 * RAID map related structures
802 ********************************************************************/
803 #pragma pack(1)
804 typedef struct _MR_DEV_HANDLE_INFO {
805 u_int16_t curDevHdl;
806 u_int8_t validHandles;
807 u_int8_t interfaceType;
808 u_int16_t devHandle[2];
809 } MR_DEV_HANDLE_INFO;
810
811 #pragma pack()
812
813 typedef struct _MR_ARRAY_INFO {
814 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE];
815 } MR_ARRAY_INFO;
816
817 typedef struct _MR_QUAD_ELEMENT {
818 u_int64_t logStart;
819 u_int64_t logEnd;
820 u_int64_t offsetInSpan;
821 u_int32_t diff;
822 u_int32_t reserved1;
823 } MR_QUAD_ELEMENT;
824
825 typedef struct _MR_SPAN_INFO {
826 u_int32_t noElements;
827 u_int32_t reserved1;
828 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
829 } MR_SPAN_INFO;
830
831 typedef struct _MR_LD_SPAN_ {
832 u_int64_t startBlk;
833 u_int64_t numBlks;
834 u_int16_t arrayRef;
835 u_int8_t spanRowSize;
836 u_int8_t spanRowDataSize;
837 u_int8_t reserved[4];
838 } MR_LD_SPAN;
839
840 typedef struct _MR_SPAN_BLOCK_INFO {
841 u_int64_t num_rows;
842 MR_LD_SPAN span;
843 MR_SPAN_INFO block_span_info;
844 } MR_SPAN_BLOCK_INFO;
845
846 typedef struct _MR_LD_RAID {
847 struct {
848 #if _BYTE_ORDER == _LITTLE_ENDIAN
849 u_int32_t fpCapable:1;
850 u_int32_t raCapable:1;
851 u_int32_t reserved5:2;
852 u_int32_t ldPiMode:4;
853 u_int32_t pdPiMode:4;
854 u_int32_t encryptionType:8;
855 u_int32_t fpWriteCapable:1;
856 u_int32_t fpReadCapable:1;
857 u_int32_t fpWriteAcrossStripe:1;
858 u_int32_t fpReadAcrossStripe:1;
859 u_int32_t fpNonRWCapable:1;
860 u_int32_t tmCapable:1;
861 u_int32_t fpCacheBypassCapable:1;
862 u_int32_t reserved4:5;
863 #else
864 u_int32_t reserved4:5;
865 u_int32_t fpCacheBypassCapable:1;
866 u_int32_t tmCapable:1;
867 u_int32_t fpNonRWCapable:1;
868 u_int32_t fpReadAcrossStripe:1;
869 u_int32_t fpWriteAcrossStripe:1;
870 u_int32_t fpReadCapable:1;
871 u_int32_t fpWriteCapable:1;
872 u_int32_t encryptionType:8;
873 u_int32_t pdPiMode:4;
874 u_int32_t ldPiMode:4;
875 u_int32_t reserved5:2;
876 u_int32_t raCapable:1;
877 u_int32_t fpCapable:1;
878 #endif
879 } capability;
880 u_int32_t reserved6;
881 u_int64_t size;
882
883 u_int8_t spanDepth;
884 u_int8_t level;
885 u_int8_t stripeShift;
886 u_int8_t rowSize;
887
888 u_int8_t rowDataSize;
889 u_int8_t writeMode;
890 u_int8_t PRL;
891 u_int8_t SRL;
892
893 u_int16_t targetId;
894 u_int8_t ldState;
895 u_int8_t regTypeReqOnWrite;
896 u_int8_t modFactor;
897 u_int8_t regTypeReqOnRead;
898 u_int16_t seqNum;
899
900 struct {
901 #if _BYTE_ORDER == _LITTLE_ENDIAN
902 u_int32_t reserved:30;
903 u_int32_t regTypeReqOnReadLsValid:1;
904 u_int32_t ldSyncRequired:1;
905 #else
906 u_int32_t ldSyncRequired:1;
907 u_int32_t regTypeReqOnReadLsValid:1;
908 u_int32_t reserved:30;
909 #endif
910 } flags;
911
912 u_int8_t LUN[8];
913 u_int8_t fpIoTimeoutForLd;
914 u_int8_t reserved2[3];
915 u_int32_t logicalBlockLength;
916 struct {
917 #if _BYTE_ORDER == _LITTLE_ENDIAN
918 u_int32_t reserved1:24;
919 u_int32_t LdLogicalBlockExp:4;
920 u_int32_t LdPiExp:4;
921 #else
922 u_int32_t LdPiExp:4;
923 u_int32_t LdLogicalBlockExp:4;
924 u_int32_t reserved1:24;
925 #endif
926 } exponent;
927 u_int8_t reserved3[0x80 - 0x38];
928 } MR_LD_RAID;
929
930 typedef struct _MR_LD_SPAN_MAP {
931 MR_LD_RAID ldRaid;
932 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE];
933 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
934 } MR_LD_SPAN_MAP;
935
936 typedef struct _MR_FW_RAID_MAP {
937 u_int32_t totalSize;
938 union {
939 struct {
940 u_int32_t maxLd;
941 u_int32_t maxSpanDepth;
942 u_int32_t maxRowSize;
943 u_int32_t maxPdCount;
944 u_int32_t maxArrays;
945 } validationInfo;
946 u_int32_t version[5];
947 u_int32_t reserved1[5];
948 } raid_desc;
949 u_int32_t ldCount;
950 u_int32_t Reserved1;
951
952 /*
953 * This doesn't correspond to FW Ld Tgt Id to LD, but will purge. For
954 * example: if tgt Id is 4 and FW LD is 2, and there is only one LD,
955 * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF,
956 * 0x0,.....]. This is to help reduce the entire strcture size if
957 * there are few LDs or driver is looking info for 1 LD only.
958 */
959 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS];
960 u_int8_t fpPdIoTimeoutSec;
961 u_int8_t reserved2[7];
962 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
963 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
964 MR_LD_SPAN_MAP ldSpanMap[1];
965 } MR_FW_RAID_MAP;
966
967 typedef struct _MR_FW_RAID_MAP_EXT {
968 /* Not used in new map */
969 u_int32_t reserved;
970
971 union {
972 struct {
973 u_int32_t maxLd;
974 u_int32_t maxSpanDepth;
975 u_int32_t maxRowSize;
976 u_int32_t maxPdCount;
977 u_int32_t maxArrays;
978 } validationInfo;
979 u_int32_t version[5];
980 u_int32_t reserved1[5];
981 } fw_raid_desc;
982
983 u_int8_t fpPdIoTimeoutSec;
984 u_int8_t reserved2[7];
985
986 u_int16_t ldCount;
987 u_int16_t arCount;
988 u_int16_t spanCount;
989 u_int16_t reserve3;
990
991 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
992 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
993 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
994 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
995 } MR_FW_RAID_MAP_EXT;
996
997 typedef struct _MR_DRV_RAID_MAP {
998 /*
999 * Total size of this structure, including this field. This field
1000 * will be manupulated by driver for ext raid map, else pick the
1001 * value from firmware raid map.
1002 */
1003 u_int32_t totalSize;
1004
1005 union {
1006 struct {
1007 u_int32_t maxLd;
1008 u_int32_t maxSpanDepth;
1009 u_int32_t maxRowSize;
1010 u_int32_t maxPdCount;
1011 u_int32_t maxArrays;
1012 } validationInfo;
1013 u_int32_t version[5];
1014 u_int32_t reserved1[5];
1015 } drv_raid_desc;
1016
1017 /* timeout value used by driver in FP IOs */
1018 u_int8_t fpPdIoTimeoutSec;
1019 u_int8_t reserved2[7];
1020
1021 u_int16_t ldCount;
1022 u_int16_t arCount;
1023 u_int16_t spanCount;
1024 u_int16_t reserve3;
1025
1026 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN];
1027 u_int16_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN];
1028 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN];
1029 MR_LD_SPAN_MAP ldSpanMap[1];
1030
1031 } MR_DRV_RAID_MAP;
1032
1033 /*
1034 * Driver raid map size is same as raid map ext MR_DRV_RAID_MAP_ALL is
1035 * created to sync with old raid. And it is mainly for code re-use purpose.
1036 */
1037
1038 #pragma pack(1)
1039 typedef struct _MR_DRV_RAID_MAP_ALL {
1040 MR_DRV_RAID_MAP raidMap;
1041 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1];
1042 } MR_DRV_RAID_MAP_ALL;
1043
1044 #pragma pack()
1045
1046 typedef struct _LD_LOAD_BALANCE_INFO {
1047 u_int8_t loadBalanceFlag;
1048 u_int8_t reserved1;
1049 mrsas_atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
1050 u_int64_t last_accessed_block[MAX_PHYSICAL_DEVICES];
1051 } LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO;
1052
1053 /* SPAN_SET is info caclulated from span info from Raid map per ld */
1054 typedef struct _LD_SPAN_SET {
1055 u_int64_t log_start_lba;
1056 u_int64_t log_end_lba;
1057 u_int64_t span_row_start;
1058 u_int64_t span_row_end;
1059 u_int64_t data_strip_start;
1060 u_int64_t data_strip_end;
1061 u_int64_t data_row_start;
1062 u_int64_t data_row_end;
1063 u_int8_t strip_offset[MAX_SPAN_DEPTH];
1064 u_int32_t span_row_data_width;
1065 u_int32_t diff;
1066 u_int32_t reserved[2];
1067 } LD_SPAN_SET, *PLD_SPAN_SET;
1068
1069 typedef struct LOG_BLOCK_SPAN_INFO {
1070 LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
1071 } LD_SPAN_INFO, *PLD_SPAN_INFO;
1072
1073 #pragma pack(1)
1074 typedef struct _MR_FW_RAID_MAP_ALL {
1075 MR_FW_RAID_MAP raidMap;
1076 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
1077 } MR_FW_RAID_MAP_ALL;
1078
1079 #pragma pack()
1080
1081 struct IO_REQUEST_INFO {
1082 u_int64_t ldStartBlock;
1083 u_int32_t numBlocks;
1084 u_int16_t ldTgtId;
1085 u_int8_t isRead;
1086 u_int16_t devHandle;
1087 u_int8_t pdInterface;
1088 u_int64_t pdBlock;
1089 u_int8_t fpOkForIo;
1090 u_int8_t IoforUnevenSpan;
1091 u_int8_t start_span;
1092 u_int8_t reserved;
1093 u_int64_t start_row;
1094 /* span[7:5], arm[4:0] */
1095 u_int8_t span_arm;
1096 u_int8_t pd_after_lb;
1097 boolean_t raCapable;
1098 u_int16_t r1_alt_dev_handle;
1099 };
1100
1101 /*
1102 * define MR_PD_CFG_SEQ structure for system PDs
1103 */
1104 struct MR_PD_CFG_SEQ {
1105 u_int16_t seqNum;
1106 u_int16_t devHandle;
1107 struct {
1108 #if _BYTE_ORDER == _LITTLE_ENDIAN
1109 u_int8_t tmCapable:1;
1110 u_int8_t reserved:7;
1111 #else
1112 u_int8_t reserved:7;
1113 u_int8_t tmCapable:1;
1114 #endif
1115 } capability;
1116 u_int8_t reserved;
1117 u_int16_t pdTargetId;
1118 } __packed;
1119
1120 struct MR_PD_CFG_SEQ_NUM_SYNC {
1121 u_int32_t size;
1122 u_int32_t count;
1123 struct MR_PD_CFG_SEQ seq[1];
1124 } __packed;
1125
1126 typedef struct _STREAM_DETECT {
1127 u_int64_t nextSeqLBA;
1128 struct megasas_cmd_fusion *first_cmd_fusion;
1129 struct megasas_cmd_fusion *last_cmd_fusion;
1130 u_int32_t countCmdsInStream;
1131 u_int16_t numSGEsInGroup;
1132 u_int8_t isRead;
1133 u_int8_t groupDepth;
1134 boolean_t groupFlush;
1135 u_int8_t reserved[7];
1136 } STREAM_DETECT, *PTR_STREAM_DETECT;
1137
1138 typedef struct _LD_STREAM_DETECT {
1139 boolean_t writeBack;
1140 boolean_t FPWriteEnabled;
1141 boolean_t membersSSDs;
1142 boolean_t fpCacheBypassCapable;
1143 u_int32_t mruBitMap;
1144 volatile long iosToFware;
1145 volatile long writeBytesOutstanding;
1146 STREAM_DETECT streamTrack[MAX_STREAMS_TRACKED];
1147 } LD_STREAM_DETECT, *PTR_LD_STREAM_DETECT;
1148
1149 typedef struct _MR_LD_TARGET_SYNC {
1150 u_int8_t targetId;
1151 u_int8_t reserved;
1152 u_int16_t seqNum;
1153 } MR_LD_TARGET_SYNC;
1154
1155 /*
1156 * RAID Map descriptor Types.
1157 * Each element should uniquely idetify one data structure in the RAID map
1158 */
1159 typedef enum _MR_RAID_MAP_DESC_TYPE {
1160 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0, /* MR_DEV_HANDLE_INFO data */
1161 RAID_MAP_DESC_TYPE_TGTID_INFO = 1, /* target to Ld num Index map */
1162 RAID_MAP_DESC_TYPE_ARRAY_INFO = 2, /* MR_ARRAY_INFO data */
1163 RAID_MAP_DESC_TYPE_SPAN_INFO = 3, /* MR_LD_SPAN_MAP data */
1164 RAID_MAP_DESC_TYPE_COUNT,
1165 } MR_RAID_MAP_DESC_TYPE;
1166
1167 /*
1168 * This table defines the offset, size and num elements of each descriptor
1169 * type in the RAID Map buffer
1170 */
1171 typedef struct _MR_RAID_MAP_DESC_TABLE {
1172 /* Raid map descriptor type */
1173 u_int32_t raidMapDescType;
1174 /* Offset into the RAID map buffer where descriptor data is saved */
1175 u_int32_t raidMapDescOffset;
1176 /* total size of the descriptor buffer */
1177 u_int32_t raidMapDescBufferSize;
1178 /* Number of elements contained in the descriptor buffer */
1179 u_int32_t raidMapDescElements;
1180 } MR_RAID_MAP_DESC_TABLE;
1181
1182 /*
1183 * Dynamic Raid Map Structure.
1184 */
1185 typedef struct _MR_FW_RAID_MAP_DYNAMIC {
1186 u_int32_t raidMapSize;
1187 u_int32_t descTableOffset;
1188 u_int32_t descTableSize;
1189 u_int32_t descTableNumElements;
1190 u_int64_t PCIThresholdBandwidth;
1191 u_int32_t reserved2[3];
1192
1193 u_int8_t fpPdIoTimeoutSec;
1194 u_int8_t reserved3[3];
1195 u_int32_t rmwFPSeqNum;
1196 u_int16_t ldCount;
1197 u_int16_t arCount;
1198 u_int16_t spanCount;
1199 u_int16_t reserved4[3];
1200
1201 /*
1202 * The below structure of pointers is only to be used by the driver.
1203 * This is added in the API to reduce the amount of code changes needed in
1204 * the driver to support dynamic RAID map.
1205 * Firmware should not update these pointers while preparing the raid map
1206 */
1207 union {
1208 struct {
1209 MR_DEV_HANDLE_INFO *devHndlInfo;
1210 u_int16_t *ldTgtIdToLd;
1211 MR_ARRAY_INFO *arMapInfo;
1212 MR_LD_SPAN_MAP *ldSpanMap;
1213 } ptrStruct;
1214 u_int64_t ptrStructureSize[RAID_MAP_DESC_TYPE_COUNT];
1215 } RaidMapDescPtrs;
1216
1217 /*
1218 * RAID Map descriptor table defines the layout of data in the RAID Map.
1219 * The size of the descriptor table itself could change.
1220 */
1221
1222 /* Variable Size descriptor Table. */
1223 MR_RAID_MAP_DESC_TABLE raidMapDescTable[RAID_MAP_DESC_TYPE_COUNT];
1224 /* Variable Size buffer containing all data */
1225 u_int32_t raidMapDescData[1];
1226
1227 } MR_FW_RAID_MAP_DYNAMIC;
1228
1229 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1230 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1231 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1232 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1233 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1234 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1235 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1236
1237 /* Few NVME flags defines*/
1238 #define MPI2_SGE_FLAGS_SHIFT (0x02)
1239 #define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0)
1240 #define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00)
1241 #define IEEE_SGE_FLAGS_FORMAT_PQI (0x01)
1242 #define IEEE_SGE_FLAGS_FORMAT_NVME (0x02)
1243 #define IEEE_SGE_FLAGS_FORMAT_AHCI (0x03)
1244
1245 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1246 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1247 #define MPI26_IEEE_SGE_FLAGS_NSF_PQI (0x04)
1248 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1249 #define MPI26_IEEE_SGE_FLAGS_NSF_AHCI_PRDT (0x0C)
1250 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1251
1252 union desc_value {
1253 u_int64_t word;
1254 struct {
1255 u_int32_t low;
1256 u_int32_t high;
1257 } u;
1258 };
1259
1260 /*******************************************************************
1261 * Temporary command
1262 ********************************************************************/
1263 struct mrsas_tmp_dcmd {
1264 bus_dma_tag_t tmp_dcmd_tag;
1265 bus_dmamap_t tmp_dcmd_dmamap;
1266 void *tmp_dcmd_mem;
1267 bus_addr_t tmp_dcmd_phys_addr;
1268 };
1269
1270 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16
1271 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF
1272 #define MR_MIN_MAP_SIZE 0x10000
1273
1274 /*******************************************************************
1275 * Register set, included legacy controllers 1068 and 1078,
1276 * structure extended for 1078 registers
1277 *******************************************************************/
1278 #pragma pack(1)
1279 typedef struct _mrsas_register_set {
1280 u_int32_t doorbell; /* 0000h */
1281 u_int32_t fusion_seq_offset; /* 0004h */
1282 u_int32_t fusion_host_diag; /* 0008h */
1283 u_int32_t reserved_01; /* 000Ch */
1284
1285 u_int32_t inbound_msg_0; /* 0010h */
1286 u_int32_t inbound_msg_1; /* 0014h */
1287 u_int32_t outbound_msg_0; /* 0018h */
1288 u_int32_t outbound_msg_1; /* 001Ch */
1289
1290 u_int32_t inbound_doorbell; /* 0020h */
1291 u_int32_t inbound_intr_status; /* 0024h */
1292 u_int32_t inbound_intr_mask; /* 0028h */
1293
1294 u_int32_t outbound_doorbell; /* 002Ch */
1295 u_int32_t outbound_intr_status; /* 0030h */
1296 u_int32_t outbound_intr_mask; /* 0034h */
1297
1298 u_int32_t reserved_1[2]; /* 0038h */
1299
1300 u_int32_t inbound_queue_port; /* 0040h */
1301 u_int32_t outbound_queue_port; /* 0044h */
1302
1303 u_int32_t reserved_2[9]; /* 0048h */
1304 u_int32_t reply_post_host_index;/* 006Ch */
1305 u_int32_t reserved_2_2[12]; /* 0070h */
1306
1307 u_int32_t outbound_doorbell_clear; /* 00A0h */
1308
1309 u_int32_t reserved_3[3]; /* 00A4h */
1310
1311 u_int32_t outbound_scratch_pad; /* 00B0h */
1312 u_int32_t outbound_scratch_pad_2; /* 00B4h */
1313 u_int32_t outbound_scratch_pad_3; /* 00B8h */
1314 u_int32_t outbound_scratch_pad_4; /* 00BCh */
1315
1316 u_int32_t inbound_low_queue_port; /* 00C0h */
1317
1318 u_int32_t inbound_high_queue_port; /* 00C4h */
1319
1320 u_int32_t inbound_single_queue_port; /* 00C8h */
1321 u_int32_t res_6[11]; /* CCh */
1322 u_int32_t host_diag;
1323 u_int32_t seq_offset;
1324 u_int32_t index_registers[807]; /* 00CCh */
1325 } mrsas_reg_set;
1326
1327 #pragma pack()
1328
1329 /*******************************************************************
1330 * Firmware Interface Defines
1331 *******************************************************************
1332 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker
1333 * for protocol between the software and firmware. Commands are
1334 * issued using "message frames".
1335 ******************************************************************/
1336 /*
1337 * FW posts its state in upper 4 bits of outbound_msg_0 register
1338 */
1339 #define MFI_STATE_MASK 0xF0000000
1340 #define MFI_STATE_UNDEFINED 0x00000000
1341 #define MFI_STATE_BB_INIT 0x10000000
1342 #define MFI_STATE_FW_INIT 0x40000000
1343 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
1344 #define MFI_STATE_FW_INIT_2 0x70000000
1345 #define MFI_STATE_DEVICE_SCAN 0x80000000
1346 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
1347 #define MFI_STATE_FLUSH_CACHE 0xA0000000
1348 #define MFI_STATE_READY 0xB0000000
1349 #define MFI_STATE_OPERATIONAL 0xC0000000
1350 #define MFI_STATE_FAULT 0xF0000000
1351 #define MFI_RESET_REQUIRED 0x00000001
1352 #define MFI_RESET_ADAPTER 0x00000002
1353 #define MEGAMFI_FRAME_SIZE 64
1354 #define MRSAS_MFI_FRAME_SIZE 1024
1355 #define MRSAS_MFI_SENSE_SIZE 128
1356
1357 /*
1358 * During FW init, clear pending cmds & reset state using inbound_msg_0
1359 *
1360 * ABORT : Abort all pending cmds READY : Move from OPERATIONAL to
1361 * READY state; discard queue info MFIMODE : Discard (possible) low MFA
1362 * posted in 64-bit mode (??) CLR_HANDSHAKE: FW is waiting for HANDSHAKE from
1363 * BIOS or Driver HOTPLUG : Resume from Hotplug MFI_STOP_ADP : Send
1364 * signal to FW to stop processing
1365 */
1366
1367 #define WRITE_SEQUENCE_OFFSET (0x0000000FC)
1368 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8)
1369 #define DIAG_WRITE_ENABLE (0x00000080)
1370 #define DIAG_RESET_ADAPTER (0x00000004)
1371
1372 #define MFI_ADP_RESET 0x00000040
1373 #define MFI_INIT_ABORT 0x00000001
1374 #define MFI_INIT_READY 0x00000002
1375 #define MFI_INIT_MFIMODE 0x00000004
1376 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
1377 #define MFI_INIT_HOTPLUG 0x00000010
1378 #define MFI_STOP_ADP 0x00000020
1379 #define MFI_RESET_FLAGS MFI_INIT_READY| \
1380 MFI_INIT_MFIMODE| \
1381 MFI_INIT_ABORT
1382
1383 /*
1384 * MFI frame flags
1385 */
1386 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
1387 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
1388 #define MFI_FRAME_SGL32 0x0000
1389 #define MFI_FRAME_SGL64 0x0002
1390 #define MFI_FRAME_SENSE32 0x0000
1391 #define MFI_FRAME_SENSE64 0x0004
1392 #define MFI_FRAME_DIR_NONE 0x0000
1393 #define MFI_FRAME_DIR_WRITE 0x0008
1394 #define MFI_FRAME_DIR_READ 0x0010
1395 #define MFI_FRAME_DIR_BOTH 0x0018
1396 #define MFI_FRAME_IEEE 0x0020
1397
1398 /*
1399 * Definition for cmd_status
1400 */
1401 #define MFI_CMD_STATUS_POLL_MODE 0xFF
1402
1403 /*
1404 * MFI command opcodes
1405 */
1406 #define MFI_CMD_INIT 0x00
1407 #define MFI_CMD_LD_READ 0x01
1408 #define MFI_CMD_LD_WRITE 0x02
1409 #define MFI_CMD_LD_SCSI_IO 0x03
1410 #define MFI_CMD_PD_SCSI_IO 0x04
1411 #define MFI_CMD_DCMD 0x05
1412 #define MFI_CMD_ABORT 0x06
1413 #define MFI_CMD_SMP 0x07
1414 #define MFI_CMD_STP 0x08
1415 #define MFI_CMD_INVALID 0xff
1416
1417 #define MR_DCMD_CTRL_GET_INFO 0x01010000
1418 #define MR_DCMD_LD_GET_LIST 0x03010000
1419 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
1420 #define MR_FLUSH_CTRL_CACHE 0x01
1421 #define MR_FLUSH_DISK_CACHE 0x02
1422
1423 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
1424 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
1425 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
1426
1427 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
1428 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
1429 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
1430 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
1431
1432 #define MR_DCMD_CLUSTER 0x08000000
1433 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
1434 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
1435 #define MR_DCMD_PD_LIST_QUERY 0x02010100
1436
1437 #define MR_DCMD_CTRL_MISC_CPX 0x0100e200
1438 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201
1439 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202
1440 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203
1441 #define MAX_MR_ROW_SIZE 32
1442 #define MR_CPX_DIR_WRITE 1
1443 #define MR_CPX_DIR_READ 0
1444 #define MR_CPX_VERSION 1
1445
1446 #define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200
1447
1448 #define MR_EVT_CFG_CLEARED 0x0004
1449
1450 #define MR_EVT_LD_STATE_CHANGE 0x0051
1451 #define MR_EVT_PD_INSERTED 0x005b
1452 #define MR_EVT_PD_REMOVED 0x0070
1453 #define MR_EVT_LD_CREATED 0x008a
1454 #define MR_EVT_LD_DELETED 0x008b
1455 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
1456 #define MR_EVT_LD_OFFLINE 0x00fc
1457 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
1458 #define MR_EVT_CTRL_PERF_COLLECTION 0x017e
1459
1460 /*
1461 * MFI command completion codes
1462 */
1463 enum MFI_STAT {
1464 MFI_STAT_OK = 0x00,
1465 MFI_STAT_INVALID_CMD = 0x01,
1466 MFI_STAT_INVALID_DCMD = 0x02,
1467 MFI_STAT_INVALID_PARAMETER = 0x03,
1468 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
1469 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
1470 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
1471 MFI_STAT_APP_IN_USE = 0x07,
1472 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
1473 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
1474 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
1475 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
1476 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
1477 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
1478 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
1479 MFI_STAT_FLASH_BUSY = 0x0f,
1480 MFI_STAT_FLASH_ERROR = 0x10,
1481 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
1482 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
1483 MFI_STAT_FLASH_NOT_OPEN = 0x13,
1484 MFI_STAT_FLASH_NOT_STARTED = 0x14,
1485 MFI_STAT_FLUSH_FAILED = 0x15,
1486 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
1487 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
1488 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
1489 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
1490 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
1491 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
1492 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
1493 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
1494 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
1495 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
1496 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
1497 MFI_STAT_MFC_HW_ERROR = 0x21,
1498 MFI_STAT_NO_HW_PRESENT = 0x22,
1499 MFI_STAT_NOT_FOUND = 0x23,
1500 MFI_STAT_NOT_IN_ENCL = 0x24,
1501 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
1502 MFI_STAT_PD_TYPE_WRONG = 0x26,
1503 MFI_STAT_PR_DISABLED = 0x27,
1504 MFI_STAT_ROW_INDEX_INVALID = 0x28,
1505 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
1506 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
1507 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
1508 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
1509 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
1510 MFI_STAT_SCSI_IO_FAILED = 0x2e,
1511 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
1512 MFI_STAT_SHUTDOWN_FAILED = 0x30,
1513 MFI_STAT_TIME_NOT_SET = 0x31,
1514 MFI_STAT_WRONG_STATE = 0x32,
1515 MFI_STAT_LD_OFFLINE = 0x33,
1516 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
1517 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
1518 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
1519 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
1520 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
1521 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
1522
1523 MFI_STAT_INVALID_STATUS = 0xFF
1524 };
1525
1526 /*
1527 * Number of mailbox bytes in DCMD message frame
1528 */
1529 #define MFI_MBOX_SIZE 12
1530
1531 enum MR_EVT_CLASS {
1532 MR_EVT_CLASS_DEBUG = -2,
1533 MR_EVT_CLASS_PROGRESS = -1,
1534 MR_EVT_CLASS_INFO = 0,
1535 MR_EVT_CLASS_WARNING = 1,
1536 MR_EVT_CLASS_CRITICAL = 2,
1537 MR_EVT_CLASS_FATAL = 3,
1538 MR_EVT_CLASS_DEAD = 4,
1539
1540 };
1541
1542 enum MR_EVT_LOCALE {
1543 MR_EVT_LOCALE_LD = 0x0001,
1544 MR_EVT_LOCALE_PD = 0x0002,
1545 MR_EVT_LOCALE_ENCL = 0x0004,
1546 MR_EVT_LOCALE_BBU = 0x0008,
1547 MR_EVT_LOCALE_SAS = 0x0010,
1548 MR_EVT_LOCALE_CTRL = 0x0020,
1549 MR_EVT_LOCALE_CONFIG = 0x0040,
1550 MR_EVT_LOCALE_CLUSTER = 0x0080,
1551 MR_EVT_LOCALE_ALL = 0xffff,
1552
1553 };
1554
1555 enum MR_EVT_ARGS {
1556 MR_EVT_ARGS_NONE,
1557 MR_EVT_ARGS_CDB_SENSE,
1558 MR_EVT_ARGS_LD,
1559 MR_EVT_ARGS_LD_COUNT,
1560 MR_EVT_ARGS_LD_LBA,
1561 MR_EVT_ARGS_LD_OWNER,
1562 MR_EVT_ARGS_LD_LBA_PD_LBA,
1563 MR_EVT_ARGS_LD_PROG,
1564 MR_EVT_ARGS_LD_STATE,
1565 MR_EVT_ARGS_LD_STRIP,
1566 MR_EVT_ARGS_PD,
1567 MR_EVT_ARGS_PD_ERR,
1568 MR_EVT_ARGS_PD_LBA,
1569 MR_EVT_ARGS_PD_LBA_LD,
1570 MR_EVT_ARGS_PD_PROG,
1571 MR_EVT_ARGS_PD_STATE,
1572 MR_EVT_ARGS_PCI,
1573 MR_EVT_ARGS_RATE,
1574 MR_EVT_ARGS_STR,
1575 MR_EVT_ARGS_TIME,
1576 MR_EVT_ARGS_ECC,
1577 MR_EVT_ARGS_LD_PROP,
1578 MR_EVT_ARGS_PD_SPARE,
1579 MR_EVT_ARGS_PD_INDEX,
1580 MR_EVT_ARGS_DIAG_PASS,
1581 MR_EVT_ARGS_DIAG_FAIL,
1582 MR_EVT_ARGS_PD_LBA_LBA,
1583 MR_EVT_ARGS_PORT_PHY,
1584 MR_EVT_ARGS_PD_MISSING,
1585 MR_EVT_ARGS_PD_ADDRESS,
1586 MR_EVT_ARGS_BITMAP,
1587 MR_EVT_ARGS_CONNECTOR,
1588 MR_EVT_ARGS_PD_PD,
1589 MR_EVT_ARGS_PD_FRU,
1590 MR_EVT_ARGS_PD_PATHINFO,
1591 MR_EVT_ARGS_PD_POWER_STATE,
1592 MR_EVT_ARGS_GENERIC,
1593 };
1594
1595 /*
1596 * Thunderbolt (and later) Defines
1597 */
1598 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
1599 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
1600 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
1601 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
1602 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
1603 #define MRSAS_LOAD_BALANCE_FLAG 0x1
1604 #define MRSAS_DCMD_MBOX_PEND_FLAG 0x1
1605 #define HOST_DIAG_WRITE_ENABLE 0x80
1606 #define HOST_DIAG_RESET_ADAPTER 0x4
1607 #define MRSAS_TBOLT_MAX_RESET_TRIES 3
1608 #define MRSAS_MAX_MFI_CMDS 16
1609 #define MRSAS_MAX_IOCTL_CMDS 3
1610
1611 /*
1612 * Invader Defines
1613 */
1614 #define MPI2_TYPE_CUDA 0x2
1615 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
1616 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
1617 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
1618 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
1619 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
1620 #define MR_RL_WRITE_THROUGH_MODE 0x00
1621 #define MR_RL_WRITE_BACK_MODE 0x01
1622
1623 /*
1624 * T10 PI defines
1625 */
1626 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8
1627 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
1628 #define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9
1629 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB
1630 #define MRSAS_SCSI_ADDL_CDB_LEN 0x18
1631 #define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20
1632 #define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60
1633 #define MRSAS_SCSIBLOCKSIZE 512
1634
1635 /*
1636 * Raid context flags
1637 */
1638 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
1639 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
1640 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
1641 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
1642 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
1643 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2,
1644 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3,
1645 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4,
1646 MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6,
1647 MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7
1648 } MR_RAID_FLAGS_IO_SUB_TYPE;
1649 /*
1650 * Request descriptor types
1651 */
1652 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
1653 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1
1654 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
1655 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
1656 #define MRSAS_FP_CMD_LEN 16
1657 #define MRSAS_FUSION_IN_RESET 0
1658
1659 #define RAID_CTX_SPANARM_ARM_SHIFT (0)
1660 #define RAID_CTX_SPANARM_ARM_MASK (0x1f)
1661 #define RAID_CTX_SPANARM_SPAN_SHIFT (5)
1662 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
1663
1664 /*
1665 * Define region lock types
1666 */
1667 typedef enum _REGION_TYPE {
1668 REGION_TYPE_UNUSED = 0,
1669 REGION_TYPE_SHARED_READ = 1,
1670 REGION_TYPE_SHARED_WRITE = 2,
1671 REGION_TYPE_EXCLUSIVE = 3,
1672 } REGION_TYPE;
1673
1674 /*
1675 * SCSI-CAM Related Defines
1676 */
1677 #define MRSAS_SCSI_MAX_LUNS 0
1678 #define MRSAS_SCSI_INITIATOR_ID 255
1679 #define MRSAS_SCSI_MAX_CMDS 8
1680 #define MRSAS_SCSI_MAX_CDB_LEN 16
1681 #define MRSAS_SCSI_SENSE_BUFFERSIZE 96
1682 #define MRSAS_INTERNAL_CMDS 32
1683 #define MRSAS_FUSION_INT_CMDS 8
1684
1685 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000
1686 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0
1687 #define MEGASAS_256K_IO 128
1688 #define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4)
1689
1690 /* Request types */
1691 #define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0
1692 #define MRSAS_REQ_TYPE_AEN_FETCH 0x1
1693 #define MRSAS_REQ_TYPE_PASSTHRU 0x2
1694 #define MRSAS_REQ_TYPE_GETSET_PARAM 0x3
1695 #define MRSAS_REQ_TYPE_SCSI_IO 0x4
1696
1697 /* Request states */
1698 #define MRSAS_REQ_STATE_FREE 0
1699 #define MRSAS_REQ_STATE_BUSY 1
1700 #define MRSAS_REQ_STATE_TRAN 2
1701 #define MRSAS_REQ_STATE_COMPLETE 3
1702
1703 typedef enum _MR_SCSI_CMD_TYPE {
1704 READ_WRITE_LDIO = 0,
1705 NON_READ_WRITE_LDIO = 1,
1706 READ_WRITE_SYSPDIO = 2,
1707 NON_READ_WRITE_SYSPDIO = 3,
1708 } MR_SCSI_CMD_TYPE;
1709
1710 enum mrsas_req_flags {
1711 MRSAS_DIR_UNKNOWN = 0x1,
1712 MRSAS_DIR_IN = 0x2,
1713 MRSAS_DIR_OUT = 0x4,
1714 MRSAS_DIR_NONE = 0x8,
1715 };
1716
1717 /*
1718 * Adapter Reset States
1719 */
1720 enum {
1721 MRSAS_HBA_OPERATIONAL = 0,
1722 MRSAS_ADPRESET_SM_INFAULT = 1,
1723 MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1724 MRSAS_ADPRESET_SM_OPERATIONAL = 3,
1725 MRSAS_HW_CRITICAL_ERROR = 4,
1726 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1727 };
1728
1729 /*
1730 * MPT Command Structure
1731 */
1732 struct mrsas_mpt_cmd {
1733 MRSAS_RAID_SCSI_IO_REQUEST *io_request;
1734 bus_addr_t io_request_phys_addr;
1735 MPI2_SGE_IO_UNION *chain_frame;
1736 bus_addr_t chain_frame_phys_addr;
1737 u_int32_t sge_count;
1738 u_int8_t *sense;
1739 bus_addr_t sense_phys_addr;
1740 u_int8_t retry_for_fw_reset;
1741 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1742 u_int32_t sync_cmd_idx;
1743 u_int32_t index;
1744 u_int8_t flags;
1745 u_int8_t pd_r1_lb;
1746 u_int8_t load_balance;
1747 bus_size_t length;
1748 u_int32_t error_code;
1749 bus_dmamap_t data_dmamap;
1750 void *data;
1751 union ccb *ccb_ptr;
1752 struct callout cm_callout;
1753 struct mrsas_softc *sc;
1754 boolean_t tmCapable;
1755 u_int16_t r1_alt_dev_handle;
1756 boolean_t cmd_completed;
1757 struct mrsas_mpt_cmd *peer_cmd;
1758 bool callout_owner;
1759 TAILQ_ENTRY(mrsas_mpt_cmd) next;
1760 u_int8_t pdInterface;
1761 };
1762
1763 /*
1764 * MFI Command Structure
1765 */
1766 struct mrsas_mfi_cmd {
1767 union mrsas_frame *frame;
1768 bus_dmamap_t frame_dmamap;
1769 void *frame_mem;
1770 bus_addr_t frame_phys_addr;
1771 u_int8_t *sense;
1772 bus_dmamap_t sense_dmamap;
1773 void *sense_mem;
1774 bus_addr_t sense_phys_addr;
1775 u_int32_t index;
1776 u_int8_t sync_cmd;
1777 u_int8_t cmd_status;
1778 u_int8_t abort_aen;
1779 u_int8_t retry_for_fw_reset;
1780 struct mrsas_softc *sc;
1781 union ccb *ccb_ptr;
1782 union {
1783 struct {
1784 u_int16_t smid;
1785 u_int16_t resvd;
1786 } context;
1787 u_int32_t frame_count;
1788 } cmd_id;
1789 TAILQ_ENTRY(mrsas_mfi_cmd) next;
1790 };
1791
1792 /*
1793 * define constants for device list query options
1794 */
1795 enum MR_PD_QUERY_TYPE {
1796 MR_PD_QUERY_TYPE_ALL = 0,
1797 MR_PD_QUERY_TYPE_STATE = 1,
1798 MR_PD_QUERY_TYPE_POWER_STATE = 2,
1799 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
1800 MR_PD_QUERY_TYPE_SPEED = 4,
1801 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
1802 };
1803
1804 #define MR_EVT_CFG_CLEARED 0x0004
1805 #define MR_EVT_LD_STATE_CHANGE 0x0051
1806 #define MR_EVT_PD_INSERTED 0x005b
1807 #define MR_EVT_PD_REMOVED 0x0070
1808 #define MR_EVT_LD_CREATED 0x008a
1809 #define MR_EVT_LD_DELETED 0x008b
1810 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
1811 #define MR_EVT_LD_OFFLINE 0x00fc
1812 #define MR_EVT_CTRL_PROP_CHANGED 0x012f
1813 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
1814
1815 enum MR_PD_STATE {
1816 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
1817 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
1818 MR_PD_STATE_HOT_SPARE = 0x02,
1819 MR_PD_STATE_OFFLINE = 0x10,
1820 MR_PD_STATE_FAILED = 0x11,
1821 MR_PD_STATE_REBUILD = 0x14,
1822 MR_PD_STATE_ONLINE = 0x18,
1823 MR_PD_STATE_COPYBACK = 0x20,
1824 MR_PD_STATE_SYSTEM = 0x40,
1825 };
1826
1827 /*
1828 * defines the physical drive address structure
1829 */
1830 #pragma pack(1)
1831 struct MR_PD_ADDRESS {
1832 u_int16_t deviceId;
1833 u_int16_t enclDeviceId;
1834
1835 union {
1836 struct {
1837 u_int8_t enclIndex;
1838 u_int8_t slotNumber;
1839 } mrPdAddress;
1840 struct {
1841 u_int8_t enclPosition;
1842 u_int8_t enclConnectorIndex;
1843 } mrEnclAddress;
1844 } u1;
1845 u_int8_t scsiDevType;
1846 union {
1847 u_int8_t connectedPortBitmap;
1848 u_int8_t connectedPortNumbers;
1849 } u2;
1850 u_int64_t sasAddr[2];
1851 };
1852
1853 #pragma pack()
1854
1855 /*
1856 * defines the physical drive list structure
1857 */
1858 #pragma pack(1)
1859 struct MR_PD_LIST {
1860 u_int32_t size;
1861 u_int32_t count;
1862 struct MR_PD_ADDRESS addr[1];
1863 };
1864
1865 #pragma pack()
1866
1867 #pragma pack(1)
1868 struct mrsas_pd_list {
1869 u_int16_t tid;
1870 u_int8_t driveType;
1871 u_int8_t driveState;
1872 };
1873
1874 #pragma pack()
1875
1876 /*
1877 * defines the logical drive reference structure
1878 */
1879 typedef union _MR_LD_REF {
1880 struct {
1881 u_int8_t targetId;
1882 u_int8_t reserved;
1883 u_int16_t seqNum;
1884 } ld_context;
1885 u_int32_t ref;
1886 } MR_LD_REF;
1887
1888 /*
1889 * defines the logical drive list structure
1890 */
1891 #pragma pack(1)
1892 struct MR_LD_LIST {
1893 u_int32_t ldCount;
1894 u_int32_t reserved;
1895 struct {
1896 MR_LD_REF ref;
1897 u_int8_t state;
1898 u_int8_t reserved[3];
1899 u_int64_t size;
1900 } ldList[MAX_LOGICAL_DRIVES_EXT];
1901 };
1902
1903 #pragma pack()
1904
1905 /*
1906 * SAS controller properties
1907 */
1908 #pragma pack(1)
1909 struct mrsas_ctrl_prop {
1910 u_int16_t seq_num;
1911 u_int16_t pred_fail_poll_interval;
1912 u_int16_t intr_throttle_count;
1913 u_int16_t intr_throttle_timeouts;
1914 u_int8_t rebuild_rate;
1915 u_int8_t patrol_read_rate;
1916 u_int8_t bgi_rate;
1917 u_int8_t cc_rate;
1918 u_int8_t recon_rate;
1919 u_int8_t cache_flush_interval;
1920 u_int8_t spinup_drv_count;
1921 u_int8_t spinup_delay;
1922 u_int8_t cluster_enable;
1923 u_int8_t coercion_mode;
1924 u_int8_t alarm_enable;
1925 u_int8_t disable_auto_rebuild;
1926 u_int8_t disable_battery_warn;
1927 u_int8_t ecc_bucket_size;
1928 u_int16_t ecc_bucket_leak_rate;
1929 u_int8_t restore_hotspare_on_insertion;
1930 u_int8_t expose_encl_devices;
1931 u_int8_t maintainPdFailHistory;
1932 u_int8_t disallowHostRequestReordering;
1933 u_int8_t abortCCOnError;
1934 u_int8_t loadBalanceMode;
1935 u_int8_t disableAutoDetectBackplane;
1936 u_int8_t snapVDSpace;
1937 /*
1938 * Add properties that can be controlled by a bit in the following
1939 * structure.
1940 */
1941 struct {
1942 #if _BYTE_ORDER == _LITTLE_ENDIAN
1943 u_int32_t copyBackDisabled:1;
1944 u_int32_t SMARTerEnabled:1;
1945 u_int32_t prCorrectUnconfiguredAreas:1;
1946 u_int32_t useFdeOnly:1;
1947 u_int32_t disableNCQ:1;
1948 u_int32_t SSDSMARTerEnabled:1;
1949 u_int32_t SSDPatrolReadEnabled:1;
1950 u_int32_t enableSpinDownUnconfigured:1;
1951 u_int32_t autoEnhancedImport:1;
1952 u_int32_t enableSecretKeyControl:1;
1953 u_int32_t disableOnlineCtrlReset:1;
1954 u_int32_t allowBootWithPinnedCache:1;
1955 u_int32_t disableSpinDownHS:1;
1956 u_int32_t enableJBOD:1;
1957 u_int32_t disableCacheBypass:1;
1958 u_int32_t useDiskActivityForLocate:1;
1959 u_int32_t enablePI:1;
1960 u_int32_t preventPIImport:1;
1961 u_int32_t useGlobalSparesForEmergency:1;
1962 u_int32_t useUnconfGoodForEmergency:1;
1963 u_int32_t useEmergencySparesforSMARTer:1;
1964 u_int32_t forceSGPIOForQuadOnly:1;
1965 u_int32_t enableConfigAutoBalance:1;
1966 u_int32_t enableVirtualCache:1;
1967 u_int32_t enableAutoLockRecovery:1;
1968 u_int32_t disableImmediateIO:1;
1969 u_int32_t disableT10RebuildAssist:1;
1970 u_int32_t ignore64ldRestriction:1;
1971 u_int32_t enableSwZone:1;
1972 u_int32_t limitMaxRateSATA3G:1;
1973 u_int32_t reserved:2;
1974 #else
1975 u_int32_t reserved:2;
1976 u_int32_t limitMaxRateSATA3G:1;
1977 u_int32_t enableSwZone:1;
1978 u_int32_t ignore64ldRestriction:1;
1979 u_int32_t disableT10RebuildAssist:1;
1980 u_int32_t disableImmediateIO:1;
1981 u_int32_t enableAutoLockRecovery:1;
1982 u_int32_t enableVirtualCache:1;
1983 u_int32_t enableConfigAutoBalance:1;
1984 u_int32_t forceSGPIOForQuadOnly:1;
1985 u_int32_t useEmergencySparesforSMARTer:1;
1986 u_int32_t useUnconfGoodForEmergency:1;
1987 u_int32_t useGlobalSparesForEmergency:1;
1988 u_int32_t preventPIImport:1;
1989 u_int32_t enablePI:1;
1990 u_int32_t useDiskActivityForLocate:1;
1991 u_int32_t disableCacheBypass:1;
1992 u_int32_t enableJBOD:1;
1993 u_int32_t disableSpinDownHS:1;
1994 u_int32_t allowBootWithPinnedCache:1;
1995 u_int32_t disableOnlineCtrlReset:1;
1996 u_int32_t enableSecretKeyControl:1;
1997 u_int32_t autoEnhancedImport:1;
1998 u_int32_t enableSpinDownUnconfigured:1;
1999 u_int32_t SSDPatrolReadEnabled:1;
2000 u_int32_t SSDSMARTerEnabled:1;
2001 u_int32_t disableNCQ:1;
2002 u_int32_t useFdeOnly:1;
2003 u_int32_t prCorrectUnconfiguredAreas:1;
2004 u_int32_t SMARTerEnabled:1;
2005 u_int32_t copyBackDisabled:1;
2006 #endif
2007 } OnOffProperties;
2008 u_int8_t autoSnapVDSpace;
2009 u_int8_t viewSpace;
2010 u_int16_t spinDownTime;
2011 u_int8_t reserved[24];
2012
2013 };
2014
2015 #pragma pack()
2016
2017 /*
2018 * SAS controller information
2019 */
2020 struct mrsas_ctrl_info {
2021 /*
2022 * PCI device information
2023 */
2024 struct {
2025 u_int16_t vendor_id;
2026 u_int16_t device_id;
2027 u_int16_t sub_vendor_id;
2028 u_int16_t sub_device_id;
2029 u_int8_t reserved[24];
2030 } __packed pci;
2031 /*
2032 * Host interface information
2033 */
2034 struct {
2035 u_int8_t PCIX:1;
2036 u_int8_t PCIE:1;
2037 u_int8_t iSCSI:1;
2038 u_int8_t SAS_3G:1;
2039 u_int8_t reserved_0:4;
2040 u_int8_t reserved_1[6];
2041 u_int8_t port_count;
2042 u_int64_t port_addr[8];
2043 } __packed host_interface;
2044 /*
2045 * Device (backend) interface information
2046 */
2047 struct {
2048 u_int8_t SPI:1;
2049 u_int8_t SAS_3G:1;
2050 u_int8_t SATA_1_5G:1;
2051 u_int8_t SATA_3G:1;
2052 u_int8_t reserved_0:4;
2053 u_int8_t reserved_1[6];
2054 u_int8_t port_count;
2055 u_int64_t port_addr[8];
2056 } __packed device_interface;
2057
2058 u_int32_t image_check_word;
2059 u_int32_t image_component_count;
2060
2061 struct {
2062 char name[8];
2063 char version[32];
2064 char build_date[16];
2065 char built_time[16];
2066 } __packed image_component[8];
2067
2068 u_int32_t pending_image_component_count;
2069
2070 struct {
2071 char name[8];
2072 char version[32];
2073 char build_date[16];
2074 char build_time[16];
2075 } __packed pending_image_component[8];
2076
2077 u_int8_t max_arms;
2078 u_int8_t max_spans;
2079 u_int8_t max_arrays;
2080 u_int8_t max_lds;
2081 char product_name[80];
2082 char serial_no[32];
2083
2084 /*
2085 * Other physical/controller/operation information. Indicates the
2086 * presence of the hardware
2087 */
2088 struct {
2089 u_int32_t bbu:1;
2090 u_int32_t alarm:1;
2091 u_int32_t nvram:1;
2092 u_int32_t uart:1;
2093 u_int32_t reserved:28;
2094 } __packed hw_present;
2095
2096 u_int32_t current_fw_time;
2097
2098 /*
2099 * Maximum data transfer sizes
2100 */
2101 u_int16_t max_concurrent_cmds;
2102 u_int16_t max_sge_count;
2103 u_int32_t max_request_size;
2104
2105 /*
2106 * Logical and physical device counts
2107 */
2108 u_int16_t ld_present_count;
2109 u_int16_t ld_degraded_count;
2110 u_int16_t ld_offline_count;
2111
2112 u_int16_t pd_present_count;
2113 u_int16_t pd_disk_present_count;
2114 u_int16_t pd_disk_pred_failure_count;
2115 u_int16_t pd_disk_failed_count;
2116
2117 /*
2118 * Memory size information
2119 */
2120 u_int16_t nvram_size;
2121 u_int16_t memory_size;
2122 u_int16_t flash_size;
2123
2124 /*
2125 * Error counters
2126 */
2127 u_int16_t mem_correctable_error_count;
2128 u_int16_t mem_uncorrectable_error_count;
2129
2130 /*
2131 * Cluster information
2132 */
2133 u_int8_t cluster_permitted;
2134 u_int8_t cluster_active;
2135
2136 /*
2137 * Additional max data transfer sizes
2138 */
2139 u_int16_t max_strips_per_io;
2140
2141 /*
2142 * Controller capabilities structures
2143 */
2144 struct {
2145 u_int32_t raid_level_0:1;
2146 u_int32_t raid_level_1:1;
2147 u_int32_t raid_level_5:1;
2148 u_int32_t raid_level_1E:1;
2149 u_int32_t raid_level_6:1;
2150 u_int32_t reserved:27;
2151 } __packed raid_levels;
2152
2153 struct {
2154 u_int32_t rbld_rate:1;
2155 u_int32_t cc_rate:1;
2156 u_int32_t bgi_rate:1;
2157 u_int32_t recon_rate:1;
2158 u_int32_t patrol_rate:1;
2159 u_int32_t alarm_control:1;
2160 u_int32_t cluster_supported:1;
2161 u_int32_t bbu:1;
2162 u_int32_t spanning_allowed:1;
2163 u_int32_t dedicated_hotspares:1;
2164 u_int32_t revertible_hotspares:1;
2165 u_int32_t foreign_config_import:1;
2166 u_int32_t self_diagnostic:1;
2167 u_int32_t mixed_redundancy_arr:1;
2168 u_int32_t global_hot_spares:1;
2169 u_int32_t reserved:17;
2170 } __packed adapter_operations;
2171
2172 struct {
2173 u_int32_t read_policy:1;
2174 u_int32_t write_policy:1;
2175 u_int32_t io_policy:1;
2176 u_int32_t access_policy:1;
2177 u_int32_t disk_cache_policy:1;
2178 u_int32_t reserved:27;
2179 } __packed ld_operations;
2180
2181 struct {
2182 u_int8_t min;
2183 u_int8_t max;
2184 u_int8_t reserved[2];
2185 } __packed stripe_sz_ops;
2186
2187 struct {
2188 u_int32_t force_online:1;
2189 u_int32_t force_offline:1;
2190 u_int32_t force_rebuild:1;
2191 u_int32_t reserved:29;
2192 } __packed pd_operations;
2193
2194 struct {
2195 u_int32_t ctrl_supports_sas:1;
2196 u_int32_t ctrl_supports_sata:1;
2197 u_int32_t allow_mix_in_encl:1;
2198 u_int32_t allow_mix_in_ld:1;
2199 u_int32_t allow_sata_in_cluster:1;
2200 u_int32_t reserved:27;
2201 } __packed pd_mix_support;
2202
2203 /*
2204 * Define ECC single-bit-error bucket information
2205 */
2206 u_int8_t ecc_bucket_count;
2207 u_int8_t reserved_2[11];
2208
2209 /*
2210 * Include the controller properties (changeable items)
2211 */
2212 struct mrsas_ctrl_prop properties;
2213
2214 /*
2215 * Define FW pkg version (set in envt v'bles on OEM basis)
2216 */
2217 char package_version[0x60];
2218
2219 u_int64_t deviceInterfacePortAddr2[8];
2220 u_int8_t reserved3[128];
2221
2222 struct {
2223 u_int16_t minPdRaidLevel_0:4;
2224 u_int16_t maxPdRaidLevel_0:12;
2225
2226 u_int16_t minPdRaidLevel_1:4;
2227 u_int16_t maxPdRaidLevel_1:12;
2228
2229 u_int16_t minPdRaidLevel_5:4;
2230 u_int16_t maxPdRaidLevel_5:12;
2231
2232 u_int16_t minPdRaidLevel_1E:4;
2233 u_int16_t maxPdRaidLevel_1E:12;
2234
2235 u_int16_t minPdRaidLevel_6:4;
2236 u_int16_t maxPdRaidLevel_6:12;
2237
2238 u_int16_t minPdRaidLevel_10:4;
2239 u_int16_t maxPdRaidLevel_10:12;
2240
2241 u_int16_t minPdRaidLevel_50:4;
2242 u_int16_t maxPdRaidLevel_50:12;
2243
2244 u_int16_t minPdRaidLevel_60:4;
2245 u_int16_t maxPdRaidLevel_60:12;
2246
2247 u_int16_t minPdRaidLevel_1E_RLQ0:4;
2248 u_int16_t maxPdRaidLevel_1E_RLQ0:12;
2249
2250 u_int16_t minPdRaidLevel_1E0_RLQ0:4;
2251 u_int16_t maxPdRaidLevel_1E0_RLQ0:12;
2252
2253 u_int16_t reserved[6];
2254 } pdsForRaidLevels;
2255
2256 u_int16_t maxPds; /* 0x780 */
2257 u_int16_t maxDedHSPs; /* 0x782 */
2258 u_int16_t maxGlobalHSPs; /* 0x784 */
2259 u_int16_t ddfSize; /* 0x786 */
2260 u_int8_t maxLdsPerArray; /* 0x788 */
2261 u_int8_t partitionsInDDF; /* 0x789 */
2262 u_int8_t lockKeyBinding; /* 0x78a */
2263 u_int8_t maxPITsPerLd; /* 0x78b */
2264 u_int8_t maxViewsPerLd; /* 0x78c */
2265 u_int8_t maxTargetId; /* 0x78d */
2266 u_int16_t maxBvlVdSize; /* 0x78e */
2267
2268 u_int16_t maxConfigurableSSCSize; /* 0x790 */
2269 u_int16_t currentSSCsize; /* 0x792 */
2270
2271 char expanderFwVersion[12]; /* 0x794 */
2272
2273 u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */
2274
2275 u_int16_t cacheMemorySize; /* 0x7A2 */
2276
2277 struct { /* 0x7A4 */
2278 #if _BYTE_ORDER == _LITTLE_ENDIAN
2279 u_int32_t supportPIcontroller:1;
2280 u_int32_t supportLdPIType1:1;
2281 u_int32_t supportLdPIType2:1;
2282 u_int32_t supportLdPIType3:1;
2283 u_int32_t supportLdBBMInfo:1;
2284 u_int32_t supportShieldState:1;
2285 u_int32_t blockSSDWriteCacheChange:1;
2286 u_int32_t supportSuspendResumeBGops:1;
2287 u_int32_t supportEmergencySpares:1;
2288 u_int32_t supportSetLinkSpeed:1;
2289 u_int32_t supportBootTimePFKChange:1;
2290 u_int32_t supportJBOD:1;
2291 u_int32_t disableOnlinePFKChange:1;
2292 u_int32_t supportPerfTuning:1;
2293 u_int32_t supportSSDPatrolRead:1;
2294 u_int32_t realTimeScheduler:1;
2295
2296 u_int32_t supportResetNow:1;
2297 u_int32_t supportEmulatedDrives:1;
2298 u_int32_t headlessMode:1;
2299 u_int32_t dedicatedHotSparesLimited:1;
2300
2301 u_int32_t supportUnevenSpans:1;
2302 u_int32_t reserved:11;
2303 #else
2304 u_int32_t reserved:11;
2305 u_int32_t supportUnevenSpans:1;
2306 u_int32_t dedicatedHotSparesLimited:1;
2307 u_int32_t headlessMode:1;
2308 u_int32_t supportEmulatedDrives:1;
2309 u_int32_t supportResetNow:1;
2310 u_int32_t realTimeScheduler:1;
2311 u_int32_t supportSSDPatrolRead:1;
2312 u_int32_t supportPerfTuning:1;
2313 u_int32_t disableOnlinePFKChange:1;
2314 u_int32_t supportJBOD:1;
2315 u_int32_t supportBootTimePFKChange:1;
2316 u_int32_t supportSetLinkSpeed:1;
2317 u_int32_t supportEmergencySpares:1;
2318 u_int32_t supportSuspendResumeBGops:1;
2319 u_int32_t blockSSDWriteCacheChange:1;
2320 u_int32_t supportShieldState:1;
2321 u_int32_t supportLdBBMInfo:1;
2322 u_int32_t supportLdPIType3:1;
2323 u_int32_t supportLdPIType2:1;
2324 u_int32_t supportLdPIType1:1;
2325 u_int32_t supportPIcontroller:1;
2326 #endif
2327 } adapterOperations2;
2328
2329 u_int8_t driverVersion[32]; /* 0x7A8 */
2330 u_int8_t maxDAPdCountSpinup60; /* 0x7C8 */
2331 u_int8_t temperatureROC; /* 0x7C9 */
2332 u_int8_t temperatureCtrl; /* 0x7CA */
2333 u_int8_t reserved4; /* 0x7CB */
2334 u_int16_t maxConfigurablePds; /* 0x7CC */
2335
2336 u_int8_t reserved5[2]; /* 0x7CD reserved */
2337
2338 struct {
2339 #if _BYTE_ORDER == _LITTLE_ENDIAN
2340 u_int32_t peerIsPresent:1;
2341 u_int32_t peerIsIncompatible:1;
2342
2343 u_int32_t hwIncompatible:1;
2344 u_int32_t fwVersionMismatch:1;
2345 u_int32_t ctrlPropIncompatible:1;
2346 u_int32_t premiumFeatureMismatch:1;
2347 u_int32_t reserved:26;
2348 #else
2349 u_int32_t reserved:26;
2350 u_int32_t premiumFeatureMismatch:1;
2351 u_int32_t ctrlPropIncompatible:1;
2352 u_int32_t fwVersionMismatch:1;
2353 u_int32_t hwIncompatible:1;
2354 u_int32_t peerIsIncompatible:1;
2355 u_int32_t peerIsPresent:1;
2356 #endif
2357 } cluster;
2358
2359 char clusterId[16]; /* 0x7D4 */
2360
2361 char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */
2362
2363 struct { /* 0x7E8 */
2364 #if _BYTE_ORDER == _LITTLE_ENDIAN
2365 u_int32_t supportPersonalityChange:2;
2366 u_int32_t supportThermalPollInterval:1;
2367 u_int32_t supportDisableImmediateIO:1;
2368 u_int32_t supportT10RebuildAssist:1;
2369 u_int32_t supportMaxExtLDs:1;
2370 u_int32_t supportCrashDump:1;
2371 u_int32_t supportSwZone:1;
2372 u_int32_t supportDebugQueue:1;
2373 u_int32_t supportNVCacheErase:1;
2374 u_int32_t supportForceTo512e:1;
2375 u_int32_t supportHOQRebuild:1;
2376 u_int32_t supportAllowedOpsforDrvRemoval:1;
2377 u_int32_t supportDrvActivityLEDSetting:1;
2378 u_int32_t supportNVDRAM:1;
2379 u_int32_t supportForceFlash:1;
2380 u_int32_t supportDisableSESMonitoring:1;
2381 u_int32_t supportCacheBypassModes:1;
2382 u_int32_t supportSecurityonJBOD:1;
2383 u_int32_t discardCacheDuringLDDelete:1;
2384 u_int32_t supportTTYLogCompression:1;
2385 u_int32_t supportCPLDUpdate:1;
2386 u_int32_t supportDiskCacheSettingForSysPDs:1;
2387 u_int32_t supportExtendedSSCSize:1;
2388 u_int32_t useSeqNumJbodFP:1;
2389 u_int32_t reserved:7;
2390 #else
2391 u_int32_t reserved:7;
2392 u_int32_t useSeqNumJbodFP:1;
2393 u_int32_t supportExtendedSSCSize:1;
2394 u_int32_t supportDiskCacheSettingForSysPDs:1;
2395 u_int32_t supportCPLDUpdate:1;
2396 u_int32_t supportTTYLogCompression:1;
2397 u_int32_t discardCacheDuringLDDelete:1;
2398 u_int32_t supportSecurityonJBOD:1;
2399 u_int32_t supportCacheBypassModes:1;
2400 u_int32_t supportDisableSESMonitoring:1;
2401 u_int32_t supportForceFlash:1;
2402 u_int32_t supportNVDRAM:1;
2403 u_int32_t supportDrvActivityLEDSetting:1;
2404 u_int32_t supportAllowedOpsforDrvRemoval:1;
2405 u_int32_t supportHOQRebuild:1;
2406 u_int32_t supportForceTo512e:1;
2407 u_int32_t supportNVCacheErase:1;
2408 u_int32_t supportDebugQueue:1;
2409 u_int32_t supportSwZone:1;
2410 u_int32_t supportCrashDump:1;
2411 u_int32_t supportMaxExtLDs:1;
2412 u_int32_t supportT10RebuildAssist:1;
2413 u_int32_t supportDisableImmediateIO:1;
2414 u_int32_t supportThermalPollInterval:1;
2415 u_int32_t supportPersonalityChange:2;
2416 #endif
2417 } adapterOperations3;
2418
2419 u_int8_t pad_cpld[16];
2420
2421 struct {
2422 #if _BYTE_ORDER == _LITTLE_ENDIAN
2423 u_int16_t ctrlInfoExtSupported:1;
2424 u_int16_t supportIbuttonLess:1;
2425 u_int16_t supportedEncAlgo:1;
2426 u_int16_t supportEncryptedMfc:1;
2427 u_int16_t imageUploadSupported:1;
2428 u_int16_t supportSESCtrlInMultipathCfg:1;
2429 u_int16_t supportPdMapTargetId:1;
2430 u_int16_t FWSwapsBBUVPDInfo:1;
2431 u_int16_t reserved:8;
2432 #else
2433 u_int16_t reserved:8;
2434 u_int16_t FWSwapsBBUVPDInfo:1;
2435 u_int16_t supportPdMapTargetId:1;
2436 u_int16_t supportSESCtrlInMultipathCfg:1;
2437 u_int16_t imageUploadSupported:1;
2438 u_int16_t supportEncryptedMfc:1;
2439 u_int16_t supportedEncAlgo:1;
2440 u_int16_t supportIbuttonLess:1;
2441 u_int16_t ctrlInfoExtSupported:1;
2442 #endif
2443 } adapterOperations4;
2444
2445 u_int8_t pad[0x800 - 0x7FE]; /* 0x7FE */
2446 } __packed;
2447
2448 /*
2449 * When SCSI mid-layer calls driver's reset routine, driver waits for
2450 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
2451 * that the driver cannot _actually_ abort or reset pending commands. While
2452 * it is waiting for the commands to complete, it prints a diagnostic message
2453 * every MRSAS_RESET_NOTICE_INTERVAL seconds
2454 */
2455 #define MRSAS_RESET_WAIT_TIME 180
2456 #define MRSAS_INTERNAL_CMD_WAIT_TIME 180
2457 #define MRSAS_RESET_NOTICE_INTERVAL 5
2458 #define MRSAS_IOCTL_CMD 0
2459 #define MRSAS_DEFAULT_CMD_TIMEOUT 90
2460 #define MRSAS_THROTTLE_QUEUE_DEPTH 16
2461
2462 /*
2463 * MSI-x regsiters offset defines
2464 */
2465 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
2466 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
2467 #define MR_MAX_REPLY_QUEUES_OFFSET (0x0000001F)
2468 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET (0x003FC000)
2469 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
2470 #define MR_MAX_MSIX_REG_ARRAY 16
2471
2472 /*
2473 * SYNC CACHE offset define
2474 */
2475 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
2476
2477 #define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET (1 << 24)
2478
2479 /*
2480 * FW reports the maximum of number of commands that it can accept (maximum
2481 * commands that can be outstanding) at any time. The driver must report a
2482 * lower number to the mid layer because it can issue a few internal commands
2483 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
2484 * is shown below
2485 */
2486 #define MRSAS_INT_CMDS 32
2487 #define MRSAS_SKINNY_INT_CMDS 5
2488 #define MRSAS_MAX_MSIX_QUEUES 128
2489
2490 /*
2491 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit SGLs
2492 * based on the size of bus_addr_t
2493 */
2494 #define IS_DMA64 (sizeof(bus_addr_t) == 8)
2495
2496 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
2497 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
2498 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
2499 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
2500
2501 #define MFI_OB_INTR_STATUS_MASK 0x00000002
2502 #define MFI_POLL_TIMEOUT_SECS 60
2503
2504 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
2505 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
2506 #define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001
2507 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
2508 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
2509 #define MFI_1068_PCSR_OFFSET 0x84
2510 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
2511 #define MFI_1068_FW_READY 0xDDDD0000
2512
2513 typedef union _MFI_CAPABILITIES {
2514 struct {
2515 #if _BYTE_ORDER == _LITTLE_ENDIAN
2516 u_int32_t support_fp_remote_lun:1;
2517 u_int32_t support_additional_msix:1;
2518 u_int32_t support_fastpath_wb:1;
2519 u_int32_t support_max_255lds:1;
2520 u_int32_t support_ndrive_r1_lb:1;
2521 u_int32_t support_core_affinity:1;
2522 u_int32_t security_protocol_cmds_fw:1;
2523 u_int32_t support_ext_queue_depth:1;
2524 u_int32_t support_ext_io_size:1;
2525 u_int32_t reserved:23;
2526 #else
2527 u_int32_t reserved:23;
2528 u_int32_t support_ext_io_size:1;
2529 u_int32_t support_ext_queue_depth:1;
2530 u_int32_t security_protocol_cmds_fw:1;
2531 u_int32_t support_core_affinity:1;
2532 u_int32_t support_ndrive_r1_lb:1;
2533 u_int32_t support_max_255lds:1;
2534 u_int32_t support_fastpath_wb:1;
2535 u_int32_t support_additional_msix:1;
2536 u_int32_t support_fp_remote_lun:1;
2537 #endif
2538 } mfi_capabilities;
2539 u_int32_t reg;
2540 } MFI_CAPABILITIES;
2541
2542 #pragma pack(1)
2543 struct mrsas_sge32 {
2544 u_int32_t phys_addr;
2545 u_int32_t length;
2546 };
2547
2548 #pragma pack()
2549
2550 #pragma pack(1)
2551 struct mrsas_sge64 {
2552 u_int64_t phys_addr;
2553 u_int32_t length;
2554 };
2555
2556 #pragma pack()
2557
2558 #pragma pack()
2559 union mrsas_sgl {
2560 struct mrsas_sge32 sge32[1];
2561 struct mrsas_sge64 sge64[1];
2562 };
2563
2564 #pragma pack()
2565
2566 #pragma pack(1)
2567 struct mrsas_header {
2568 u_int8_t cmd; /* 00e */
2569 u_int8_t sense_len; /* 01h */
2570 u_int8_t cmd_status; /* 02h */
2571 u_int8_t scsi_status; /* 03h */
2572
2573 u_int8_t target_id; /* 04h */
2574 u_int8_t lun; /* 05h */
2575 u_int8_t cdb_len; /* 06h */
2576 u_int8_t sge_count; /* 07h */
2577
2578 u_int32_t context; /* 08h */
2579 u_int32_t pad_0; /* 0Ch */
2580
2581 u_int16_t flags; /* 10h */
2582 u_int16_t timeout; /* 12h */
2583 u_int32_t data_xferlen; /* 14h */
2584 };
2585
2586 #pragma pack()
2587
2588 #pragma pack(1)
2589 struct mrsas_init_frame {
2590 u_int8_t cmd; /* 00h */
2591 u_int8_t reserved_0; /* 01h */
2592 u_int8_t cmd_status; /* 02h */
2593
2594 u_int8_t reserved_1; /* 03h */
2595 MFI_CAPABILITIES driver_operations; /* 04h */
2596 u_int32_t context; /* 08h */
2597 u_int32_t pad_0; /* 0Ch */
2598
2599 u_int16_t flags; /* 10h */
2600 u_int16_t reserved_3; /* 12h */
2601 u_int32_t data_xfer_len; /* 14h */
2602
2603 u_int32_t queue_info_new_phys_addr_lo; /* 18h */
2604 u_int32_t queue_info_new_phys_addr_hi; /* 1Ch */
2605 u_int32_t queue_info_old_phys_addr_lo; /* 20h */
2606 u_int32_t queue_info_old_phys_addr_hi; /* 24h */
2607 u_int32_t driver_ver_lo; /* 28h */
2608 u_int32_t driver_ver_hi; /* 2Ch */
2609 u_int32_t reserved_4[4]; /* 30h */
2610 };
2611
2612 #pragma pack()
2613
2614 #pragma pack(1)
2615 struct mrsas_io_frame {
2616 u_int8_t cmd; /* 00h */
2617 u_int8_t sense_len; /* 01h */
2618 u_int8_t cmd_status; /* 02h */
2619 u_int8_t scsi_status; /* 03h */
2620
2621 u_int8_t target_id; /* 04h */
2622 u_int8_t access_byte; /* 05h */
2623 u_int8_t reserved_0; /* 06h */
2624 u_int8_t sge_count; /* 07h */
2625
2626 u_int32_t context; /* 08h */
2627 u_int32_t pad_0; /* 0Ch */
2628
2629 u_int16_t flags; /* 10h */
2630 u_int16_t timeout; /* 12h */
2631 u_int32_t lba_count; /* 14h */
2632
2633 u_int32_t sense_buf_phys_addr_lo; /* 18h */
2634 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */
2635
2636 u_int32_t start_lba_lo; /* 20h */
2637 u_int32_t start_lba_hi; /* 24h */
2638
2639 union mrsas_sgl sgl; /* 28h */
2640 };
2641
2642 #pragma pack()
2643
2644 #pragma pack(1)
2645 struct mrsas_pthru_frame {
2646 u_int8_t cmd; /* 00h */
2647 u_int8_t sense_len; /* 01h */
2648 u_int8_t cmd_status; /* 02h */
2649 u_int8_t scsi_status; /* 03h */
2650
2651 u_int8_t target_id; /* 04h */
2652 u_int8_t lun; /* 05h */
2653 u_int8_t cdb_len; /* 06h */
2654 u_int8_t sge_count; /* 07h */
2655
2656 u_int32_t context; /* 08h */
2657 u_int32_t pad_0; /* 0Ch */
2658
2659 u_int16_t flags; /* 10h */
2660 u_int16_t timeout; /* 12h */
2661 u_int32_t data_xfer_len; /* 14h */
2662
2663 u_int32_t sense_buf_phys_addr_lo; /* 18h */
2664 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */
2665
2666 u_int8_t cdb[16]; /* 20h */
2667 union mrsas_sgl sgl; /* 30h */
2668 };
2669
2670 #pragma pack()
2671
2672 #pragma pack(1)
2673 struct mrsas_dcmd_frame {
2674 u_int8_t cmd; /* 00h */
2675 u_int8_t reserved_0; /* 01h */
2676 u_int8_t cmd_status; /* 02h */
2677 u_int8_t reserved_1[4]; /* 03h */
2678 u_int8_t sge_count; /* 07h */
2679
2680 u_int32_t context; /* 08h */
2681 u_int32_t pad_0; /* 0Ch */
2682
2683 u_int16_t flags; /* 10h */
2684 u_int16_t timeout; /* 12h */
2685
2686 u_int32_t data_xfer_len; /* 14h */
2687 u_int32_t opcode; /* 18h */
2688
2689 union { /* 1Ch */
2690 u_int8_t b[12];
2691 u_int16_t s[6];
2692 u_int32_t w[3];
2693 } mbox;
2694
2695 union mrsas_sgl sgl; /* 28h */
2696 };
2697
2698 #pragma pack()
2699
2700 #pragma pack(1)
2701 struct mrsas_abort_frame {
2702 u_int8_t cmd; /* 00h */
2703 u_int8_t reserved_0; /* 01h */
2704 u_int8_t cmd_status; /* 02h */
2705
2706 u_int8_t reserved_1; /* 03h */
2707 MFI_CAPABILITIES driver_operations; /* 04h */
2708 u_int32_t context; /* 08h */
2709 u_int32_t pad_0; /* 0Ch */
2710
2711 u_int16_t flags; /* 10h */
2712 u_int16_t reserved_3; /* 12h */
2713 u_int32_t reserved_4; /* 14h */
2714
2715 u_int32_t abort_context; /* 18h */
2716 u_int32_t pad_1; /* 1Ch */
2717
2718 u_int32_t abort_mfi_phys_addr_lo; /* 20h */
2719 u_int32_t abort_mfi_phys_addr_hi; /* 24h */
2720
2721 u_int32_t reserved_5[6]; /* 28h */
2722 };
2723
2724 #pragma pack()
2725
2726 #pragma pack(1)
2727 struct mrsas_smp_frame {
2728 u_int8_t cmd; /* 00h */
2729 u_int8_t reserved_1; /* 01h */
2730 u_int8_t cmd_status; /* 02h */
2731 u_int8_t connection_status; /* 03h */
2732
2733 u_int8_t reserved_2[3]; /* 04h */
2734 u_int8_t sge_count; /* 07h */
2735
2736 u_int32_t context; /* 08h */
2737 u_int32_t pad_0; /* 0Ch */
2738
2739 u_int16_t flags; /* 10h */
2740 u_int16_t timeout; /* 12h */
2741
2742 u_int32_t data_xfer_len; /* 14h */
2743 u_int64_t sas_addr; /* 18h */
2744
2745 union {
2746 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */
2747 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */
2748 } sgl;
2749 };
2750
2751 #pragma pack()
2752
2753 #pragma pack(1)
2754 struct mrsas_stp_frame {
2755 u_int8_t cmd; /* 00h */
2756 u_int8_t reserved_1; /* 01h */
2757 u_int8_t cmd_status; /* 02h */
2758 u_int8_t reserved_2; /* 03h */
2759
2760 u_int8_t target_id; /* 04h */
2761 u_int8_t reserved_3[2]; /* 05h */
2762 u_int8_t sge_count; /* 07h */
2763
2764 u_int32_t context; /* 08h */
2765 u_int32_t pad_0; /* 0Ch */
2766
2767 u_int16_t flags; /* 10h */
2768 u_int16_t timeout; /* 12h */
2769
2770 u_int32_t data_xfer_len; /* 14h */
2771
2772 u_int16_t fis[10]; /* 18h */
2773 u_int32_t stp_flags;
2774
2775 union {
2776 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */
2777 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */
2778 } sgl;
2779 };
2780
2781 #pragma pack()
2782
2783 union mrsas_frame {
2784 struct mrsas_header hdr;
2785 struct mrsas_init_frame init;
2786 struct mrsas_io_frame io;
2787 struct mrsas_pthru_frame pthru;
2788 struct mrsas_dcmd_frame dcmd;
2789 struct mrsas_abort_frame abort;
2790 struct mrsas_smp_frame smp;
2791 struct mrsas_stp_frame stp;
2792 u_int8_t raw_bytes[64];
2793 };
2794
2795 #pragma pack(1)
2796 union mrsas_evt_class_locale {
2797 struct {
2798 #if _BYTE_ORDER == _LITTLE_ENDIAN
2799 u_int16_t locale;
2800 u_int8_t reserved;
2801 int8_t class;
2802 #else
2803 int8_t class;
2804 u_int8_t reserved;
2805 u_int16_t locale;
2806 #endif
2807 } __packed members;
2808
2809 u_int32_t word;
2810
2811 } __packed;
2812
2813 #pragma pack()
2814
2815 #pragma pack(1)
2816 struct mrsas_evt_log_info {
2817 u_int32_t newest_seq_num;
2818 u_int32_t oldest_seq_num;
2819 u_int32_t clear_seq_num;
2820 u_int32_t shutdown_seq_num;
2821 u_int32_t boot_seq_num;
2822
2823 } __packed;
2824
2825 #pragma pack()
2826
2827 struct mrsas_progress {
2828 u_int16_t progress;
2829 u_int16_t elapsed_seconds;
2830
2831 } __packed;
2832
2833 struct mrsas_evtarg_ld {
2834 u_int16_t target_id;
2835 u_int8_t ld_index;
2836 u_int8_t reserved;
2837
2838 } __packed;
2839
2840 struct mrsas_evtarg_pd {
2841 u_int16_t device_id;
2842 u_int8_t encl_index;
2843 u_int8_t slot_number;
2844
2845 } __packed;
2846
2847 struct mrsas_evt_detail {
2848 u_int32_t seq_num;
2849 u_int32_t time_stamp;
2850 u_int32_t code;
2851 union mrsas_evt_class_locale cl;
2852 u_int8_t arg_type;
2853 u_int8_t reserved1[15];
2854
2855 union {
2856 struct {
2857 struct mrsas_evtarg_pd pd;
2858 u_int8_t cdb_length;
2859 u_int8_t sense_length;
2860 u_int8_t reserved[2];
2861 u_int8_t cdb[16];
2862 u_int8_t sense[64];
2863 } __packed cdbSense;
2864
2865 struct mrsas_evtarg_ld ld;
2866
2867 struct {
2868 struct mrsas_evtarg_ld ld;
2869 u_int64_t count;
2870 } __packed ld_count;
2871
2872 struct {
2873 u_int64_t lba;
2874 struct mrsas_evtarg_ld ld;
2875 } __packed ld_lba;
2876
2877 struct {
2878 struct mrsas_evtarg_ld ld;
2879 u_int32_t prevOwner;
2880 u_int32_t newOwner;
2881 } __packed ld_owner;
2882
2883 struct {
2884 u_int64_t ld_lba;
2885 u_int64_t pd_lba;
2886 struct mrsas_evtarg_ld ld;
2887 struct mrsas_evtarg_pd pd;
2888 } __packed ld_lba_pd_lba;
2889
2890 struct {
2891 struct mrsas_evtarg_ld ld;
2892 struct mrsas_progress prog;
2893 } __packed ld_prog;
2894
2895 struct {
2896 struct mrsas_evtarg_ld ld;
2897 u_int32_t prev_state;
2898 u_int32_t new_state;
2899 } __packed ld_state;
2900
2901 struct {
2902 u_int64_t strip;
2903 struct mrsas_evtarg_ld ld;
2904 } __packed ld_strip;
2905
2906 struct mrsas_evtarg_pd pd;
2907
2908 struct {
2909 struct mrsas_evtarg_pd pd;
2910 u_int32_t err;
2911 } __packed pd_err;
2912
2913 struct {
2914 u_int64_t lba;
2915 struct mrsas_evtarg_pd pd;
2916 } __packed pd_lba;
2917
2918 struct {
2919 u_int64_t lba;
2920 struct mrsas_evtarg_pd pd;
2921 struct mrsas_evtarg_ld ld;
2922 } __packed pd_lba_ld;
2923
2924 struct {
2925 struct mrsas_evtarg_pd pd;
2926 struct mrsas_progress prog;
2927 } __packed pd_prog;
2928
2929 struct {
2930 struct mrsas_evtarg_pd pd;
2931 u_int32_t prevState;
2932 u_int32_t newState;
2933 } __packed pd_state;
2934
2935 struct {
2936 u_int16_t vendorId;
2937 u_int16_t deviceId;
2938 u_int16_t subVendorId;
2939 u_int16_t subDeviceId;
2940 } __packed pci;
2941
2942 u_int32_t rate;
2943 char str[96];
2944
2945 struct {
2946 u_int32_t rtc;
2947 u_int32_t elapsedSeconds;
2948 } __packed time;
2949
2950 struct {
2951 u_int32_t ecar;
2952 u_int32_t elog;
2953 char str[64];
2954 } __packed ecc;
2955
2956 u_int8_t b[96];
2957 u_int16_t s[48];
2958 u_int32_t w[24];
2959 u_int64_t d[12];
2960 } args;
2961
2962 char description[128];
2963
2964 } __packed;
2965
2966 struct mrsas_irq_context {
2967 struct mrsas_softc *sc;
2968 uint32_t MSIxIndex;
2969 };
2970
2971 enum MEGASAS_OCR_REASON {
2972 FW_FAULT_OCR = 0,
2973 MFI_DCMD_TIMEOUT_OCR = 1,
2974 };
2975
2976 /* Controller management info added to support Linux Emulator */
2977 #define MAX_MGMT_ADAPTERS 1024
2978
2979 struct mrsas_mgmt_info {
2980 u_int16_t count;
2981 struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS];
2982 int max_index;
2983 };
2984
2985 #define PCI_TYPE0_ADDRESSES 6
2986 #define PCI_TYPE1_ADDRESSES 2
2987 #define PCI_TYPE2_ADDRESSES 5
2988
2989 typedef struct _MRSAS_DRV_PCI_COMMON_HEADER {
2990 u_int16_t vendorID;
2991 //(ro)
2992 u_int16_t deviceID;
2993 //(ro)
2994 u_int16_t command;
2995 //Device control
2996 u_int16_t status;
2997 u_int8_t revisionID;
2998 //(ro)
2999 u_int8_t progIf;
3000 //(ro)
3001 u_int8_t subClass;
3002 //(ro)
3003 u_int8_t baseClass;
3004 //(ro)
3005 u_int8_t cacheLineSize;
3006 //(ro +)
3007 u_int8_t latencyTimer;
3008 //(ro +)
3009 u_int8_t headerType;
3010 //(ro)
3011 u_int8_t bist;
3012 //Built in self test
3013
3014 union {
3015 struct _MRSAS_DRV_PCI_HEADER_TYPE_0 {
3016 u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES];
3017 u_int32_t cis;
3018 u_int16_t subVendorID;
3019 u_int16_t subSystemID;
3020 u_int32_t romBaseAddress;
3021 u_int8_t capabilitiesPtr;
3022 u_int8_t reserved1[3];
3023 u_int32_t reserved2;
3024 u_int8_t interruptLine;
3025 u_int8_t interruptPin;
3026 //(ro)
3027 u_int8_t minimumGrant;
3028 //(ro)
3029 u_int8_t maximumLatency;
3030 //(ro)
3031 } type0;
3032
3033 /*
3034 * PCI to PCI Bridge
3035 */
3036
3037 struct _MRSAS_DRV_PCI_HEADER_TYPE_1 {
3038 u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES];
3039 u_int8_t primaryBus;
3040 u_int8_t secondaryBus;
3041 u_int8_t subordinateBus;
3042 u_int8_t secondaryLatency;
3043 u_int8_t ioBase;
3044 u_int8_t ioLimit;
3045 u_int16_t secondaryStatus;
3046 u_int16_t memoryBase;
3047 u_int16_t memoryLimit;
3048 u_int16_t prefetchBase;
3049 u_int16_t prefetchLimit;
3050 u_int32_t prefetchBaseUpper32;
3051 u_int32_t prefetchLimitUpper32;
3052 u_int16_t ioBaseUpper16;
3053 u_int16_t ioLimitUpper16;
3054 u_int8_t capabilitiesPtr;
3055 u_int8_t reserved1[3];
3056 u_int32_t romBaseAddress;
3057 u_int8_t interruptLine;
3058 u_int8_t interruptPin;
3059 u_int16_t bridgeControl;
3060 } type1;
3061
3062 /*
3063 * PCI to CARDBUS Bridge
3064 */
3065
3066 struct _MRSAS_DRV_PCI_HEADER_TYPE_2 {
3067 u_int32_t socketRegistersBaseAddress;
3068 u_int8_t capabilitiesPtr;
3069 u_int8_t reserved;
3070 u_int16_t secondaryStatus;
3071 u_int8_t primaryBus;
3072 u_int8_t secondaryBus;
3073 u_int8_t subordinateBus;
3074 u_int8_t secondaryLatency;
3075 struct {
3076 u_int32_t base;
3077 u_int32_t limit;
3078 } range [PCI_TYPE2_ADDRESSES - 1];
3079 u_int8_t interruptLine;
3080 u_int8_t interruptPin;
3081 u_int16_t bridgeControl;
3082 } type2;
3083 } u;
3084
3085 } MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER;
3086
3087 #define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes
3088
3089 typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY {
3090 union {
3091 struct {
3092 #if _BYTE_ORDER == _LITTLE_ENDIAN
3093 u_int32_t linkSpeed:4;
3094 u_int32_t linkWidth:6;
3095 u_int32_t aspmSupport:2;
3096 u_int32_t losExitLatency:3;
3097 u_int32_t l1ExitLatency:3;
3098 u_int32_t rsvdp:6;
3099 u_int32_t portNumber:8;
3100 #else
3101 u_int32_t portNumber:8;
3102 u_int32_t rsvdp:6;
3103 u_int32_t l1ExitLatency:3;
3104 u_int32_t losExitLatency:3;
3105 u_int32_t aspmSupport:2;
3106 u_int32_t linkWidth:6;
3107 u_int32_t linkSpeed:4;
3108 #endif
3109 } bits;
3110
3111 u_int32_t asUlong;
3112 } u;
3113 } MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY;
3114
3115 #define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY)
3116
3117 typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY {
3118 union {
3119 struct {
3120 #if _BYTE_ORDER == _LITTLE_ENDIAN
3121 u_int16_t linkSpeed:4;
3122 u_int16_t negotiatedLinkWidth:6;
3123 u_int16_t linkTrainingError:1;
3124 u_int16_t linkTraning:1;
3125 u_int16_t slotClockConfig:1;
3126 u_int16_t rsvdZ:3;
3127 #else
3128 u_int16_t rsvdZ:3;
3129 u_int16_t slotClockConfig:1;
3130 u_int16_t linkTraning:1;
3131 u_int16_t linkTrainingError:1;
3132 u_int16_t negotiatedLinkWidth:6;
3133 u_int16_t linkSpeed:4;
3134 #endif
3135 } bits;
3136
3137 u_int16_t asUshort;
3138 } u;
3139 u_int16_t reserved;
3140 } MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY;
3141
3142 #define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY)
3143
3144 typedef struct _MRSAS_DRV_PCI_CAPABILITIES {
3145 MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability;
3146 MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability;
3147 } MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES;
3148
3149 #define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES)
3150
3151 /* PCI information */
3152 typedef struct _MRSAS_DRV_PCI_INFORMATION {
3153 u_int32_t busNumber;
3154 u_int8_t deviceNumber;
3155 u_int8_t functionNumber;
3156 u_int8_t interruptVector;
3157 u_int8_t reserved1;
3158 MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo;
3159 MRSAS_DRV_PCI_CAPABILITIES capability;
3160 u_int32_t domainID;
3161 u_int8_t reserved2[28];
3162 } MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION;
3163
3164 typedef enum _MR_PD_TYPE {
3165 UNKNOWN_DRIVE = 0,
3166 PARALLEL_SCSI = 1,
3167 SAS_PD = 2,
3168 SATA_PD = 3,
3169 FC_PD = 4,
3170 NVME_PD = 5,
3171 } MR_PD_TYPE;
3172
3173 typedef union _MR_PD_REF {
3174 struct {
3175 u_int16_t deviceId;
3176 u_int16_t seqNum;
3177 } mrPdRef;
3178 u_int32_t ref;
3179 } MR_PD_REF;
3180
3181 /*
3182 * define the DDF Type bit structure
3183 */
3184 union MR_PD_DDF_TYPE {
3185 struct {
3186 union {
3187 struct {
3188 #if _BYTE_ORDER == _LITTLE_ENDIAN
3189 u_int16_t forcedPDGUID:1;
3190 u_int16_t inVD:1;
3191 u_int16_t isGlobalSpare:1;
3192 u_int16_t isSpare:1;
3193 u_int16_t isForeign:1;
3194 u_int16_t reserved:7;
3195 u_int16_t intf:4;
3196 #else
3197 u_int16_t intf:4;
3198 u_int16_t reserved:7;
3199 u_int16_t isForeign:1;
3200 u_int16_t isSpare:1;
3201 u_int16_t isGlobalSpare:1;
3202 u_int16_t inVD:1;
3203 u_int16_t forcedPDGUID:1;
3204 #endif
3205 } pdType;
3206 u_int16_t type;
3207 };
3208 u_int16_t reserved;
3209 } ddf;
3210 struct {
3211 u_int32_t reserved;
3212 } nonDisk;
3213 u_int32_t type;
3214 } __packed;
3215
3216 /*
3217 * defines the progress structure
3218 */
3219 union MR_PROGRESS {
3220 struct {
3221 u_int16_t progress;
3222 union {
3223 u_int16_t elapsedSecs;
3224 u_int16_t elapsedSecsForLastPercent;
3225 };
3226 } mrProgress;
3227 u_int32_t w;
3228 } __packed;
3229
3230 /*
3231 * defines the physical drive progress structure
3232 */
3233 struct MR_PD_PROGRESS {
3234 struct {
3235 #if _BYTE_ORDER == _LITTLE_ENDIAN
3236 u_int32_t rbld:1;
3237 u_int32_t patrol:1;
3238 u_int32_t clear:1;
3239 u_int32_t copyBack:1;
3240 u_int32_t erase:1;
3241 u_int32_t locate:1;
3242 u_int32_t reserved:26;
3243 #else
3244 u_int32_t reserved:26;
3245 u_int32_t locate:1;
3246 u_int32_t erase:1;
3247 u_int32_t copyBack:1;
3248 u_int32_t clear:1;
3249 u_int32_t patrol:1;
3250 u_int32_t rbld:1;
3251 #endif
3252 } active;
3253 union MR_PROGRESS rbld;
3254 union MR_PROGRESS patrol;
3255 union {
3256 union MR_PROGRESS clear;
3257 union MR_PROGRESS erase;
3258 };
3259
3260 struct {
3261 #if _BYTE_ORDER == _LITTLE_ENDIAN
3262 u_int32_t rbld:1;
3263 u_int32_t patrol:1;
3264 u_int32_t clear:1;
3265 u_int32_t copyBack:1;
3266 u_int32_t erase:1;
3267 u_int32_t reserved:27;
3268 #else
3269 u_int32_t reserved:27;
3270 u_int32_t erase:1;
3271 u_int32_t copyBack:1;
3272 u_int32_t clear:1;
3273 u_int32_t patrol:1;
3274 u_int32_t rbld:1;
3275 #endif
3276 } pause;
3277
3278 union MR_PROGRESS reserved[3];
3279 } __packed;
3280
3281 struct mrsas_pd_info {
3282 MR_PD_REF ref;
3283 u_int8_t inquiryData[96];
3284 u_int8_t vpdPage83[64];
3285
3286 u_int8_t notSupported;
3287 u_int8_t scsiDevType;
3288
3289 union {
3290 u_int8_t connectedPortBitmap;
3291 u_int8_t connectedPortNumbers;
3292 };
3293
3294 u_int8_t deviceSpeed;
3295 u_int32_t mediaErrCount;
3296 u_int32_t otherErrCount;
3297 u_int32_t predFailCount;
3298 u_int32_t lastPredFailEventSeqNum;
3299
3300 u_int16_t fwState;
3301 u_int8_t disabledForRemoval;
3302 u_int8_t linkSpeed;
3303 union MR_PD_DDF_TYPE state;
3304
3305 struct {
3306 u_int8_t count;
3307 #if _BYTE_ORDER == _LITTLE_ENDIAN
3308 u_int8_t isPathBroken:4;
3309 u_int8_t reserved3:3;
3310 u_int8_t widePortCapable:1;
3311 #else
3312 u_int8_t widePortCapable:1;
3313 u_int8_t reserved3:3;
3314 u_int8_t isPathBroken:4;
3315 #endif
3316 u_int8_t connectorIndex[2];
3317 u_int8_t reserved[4];
3318 u_int64_t sasAddr[2];
3319 u_int8_t reserved2[16];
3320 } pathInfo;
3321
3322 u_int64_t rawSize;
3323 u_int64_t nonCoercedSize;
3324 u_int64_t coercedSize;
3325 u_int16_t enclDeviceId;
3326 u_int8_t enclIndex;
3327
3328 union {
3329 u_int8_t slotNumber;
3330 u_int8_t enclConnectorIndex;
3331 };
3332
3333 struct MR_PD_PROGRESS progInfo;
3334 u_int8_t badBlockTableFull;
3335 u_int8_t unusableInCurrentConfig;
3336 u_int8_t vpdPage83Ext[64];
3337 u_int8_t powerState;
3338 u_int8_t enclPosition;
3339 u_int32_t allowedOps;
3340 u_int16_t copyBackPartnerId;
3341 u_int16_t enclPartnerDeviceId;
3342 struct {
3343 #if _BYTE_ORDER == _LITTLE_ENDIAN
3344 u_int16_t fdeCapable:1;
3345 u_int16_t fdeEnabled:1;
3346 u_int16_t secured:1;
3347 u_int16_t locked:1;
3348 u_int16_t foreign:1;
3349 u_int16_t needsEKM:1;
3350 u_int16_t reserved:10;
3351 #else
3352 u_int16_t reserved:10;
3353 u_int16_t needsEKM:1;
3354 u_int16_t foreign:1;
3355 u_int16_t locked:1;
3356 u_int16_t secured:1;
3357 u_int16_t fdeEnabled:1;
3358 u_int16_t fdeCapable:1;
3359 #endif
3360 } security;
3361 u_int8_t mediaType;
3362 u_int8_t notCertified;
3363 u_int8_t bridgeVendor[8];
3364 u_int8_t bridgeProductIdentification[16];
3365 u_int8_t bridgeProductRevisionLevel[4];
3366 u_int8_t satBridgeExists;
3367
3368 u_int8_t interfaceType;
3369 u_int8_t temperature;
3370 u_int8_t emulatedBlockSize;
3371 u_int16_t userDataBlockSize;
3372 u_int16_t reserved2;
3373
3374 struct {
3375 #if _BYTE_ORDER == _LITTLE_ENDIAN
3376 u_int32_t piType:3;
3377 u_int32_t piFormatted:1;
3378 u_int32_t piEligible:1;
3379 u_int32_t NCQ:1;
3380 u_int32_t WCE:1;
3381 u_int32_t commissionedSpare:1;
3382 u_int32_t emergencySpare:1;
3383 u_int32_t ineligibleForSSCD:1;
3384 u_int32_t ineligibleForLd:1;
3385 u_int32_t useSSEraseType:1;
3386 u_int32_t wceUnchanged:1;
3387 u_int32_t supportScsiUnmap:1;
3388 u_int32_t reserved:18;
3389 #else
3390 u_int32_t reserved:18;
3391 u_int32_t supportScsiUnmap:1;
3392 u_int32_t wceUnchanged:1;
3393 u_int32_t useSSEraseType:1;
3394 u_int32_t ineligibleForLd:1;
3395 u_int32_t ineligibleForSSCD:1;
3396 u_int32_t emergencySpare:1;
3397 u_int32_t commissionedSpare:1;
3398 u_int32_t WCE:1;
3399 u_int32_t NCQ:1;
3400 u_int32_t piEligible:1;
3401 u_int32_t piFormatted:1;
3402 u_int32_t piType:3;
3403 #endif
3404 } properties;
3405
3406 u_int64_t shieldDiagCompletionTime;
3407 u_int8_t shieldCounter;
3408
3409 u_int8_t linkSpeedOther;
3410 u_int8_t reserved4[2];
3411
3412 struct {
3413 #if _BYTE_ORDER == _LITTLE_ENDIAN
3414 u_int32_t bbmErrCountSupported:1;
3415 u_int32_t bbmErrCount:31;
3416 #else
3417 u_int32_t bbmErrCount:31;
3418 u_int32_t bbmErrCountSupported:1;
3419 #endif
3420 } bbmErr;
3421
3422 u_int8_t reserved1[512-428];
3423 } __packed;
3424
3425 struct mrsas_target {
3426 u_int16_t target_id;
3427 u_int32_t queue_depth;
3428 u_int8_t interface_type;
3429 u_int32_t max_io_size_kb;
3430 } __packed;
3431
3432 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF
3433 #define MR_DEFAULT_NVME_PAGE_SIZE 4096
3434 #define MR_DEFAULT_NVME_PAGE_SHIFT 12
3435
3436 /*******************************************************************
3437 * per-instance data
3438 ********************************************************************/
3439 struct mrsas_softc {
3440 device_t mrsas_dev;
3441 struct cdev *mrsas_cdev;
3442 struct intr_config_hook mrsas_ich;
3443 struct cdev *mrsas_linux_emulator_cdev;
3444 uint16_t device_id;
3445 struct resource *reg_res;
3446 int reg_res_id;
3447 bus_space_tag_t bus_tag;
3448 bus_space_handle_t bus_handle;
3449 bus_dma_tag_t mrsas_parent_tag;
3450 bus_dma_tag_t verbuf_tag;
3451 bus_dmamap_t verbuf_dmamap;
3452 void *verbuf_mem;
3453 bus_addr_t verbuf_phys_addr;
3454 bus_dma_tag_t sense_tag;
3455 bus_dmamap_t sense_dmamap;
3456 void *sense_mem;
3457 bus_addr_t sense_phys_addr;
3458 bus_dma_tag_t io_request_tag;
3459 bus_dmamap_t io_request_dmamap;
3460 void *io_request_mem;
3461 bus_addr_t io_request_phys_addr;
3462 bus_dma_tag_t chain_frame_tag;
3463 bus_dmamap_t chain_frame_dmamap;
3464 void *chain_frame_mem;
3465 bus_addr_t chain_frame_phys_addr;
3466 bus_dma_tag_t reply_desc_tag;
3467 bus_dmamap_t reply_desc_dmamap;
3468 void *reply_desc_mem;
3469 bus_addr_t reply_desc_phys_addr;
3470 bus_dma_tag_t ioc_init_tag;
3471 bus_dmamap_t ioc_init_dmamap;
3472 void *ioc_init_mem;
3473 bus_addr_t ioc_init_phys_mem;
3474 bus_dma_tag_t data_tag;
3475 struct cam_sim *sim_0;
3476 struct cam_sim *sim_1;
3477 struct cam_path *path_0;
3478 struct cam_path *path_1;
3479 struct mtx sim_lock;
3480 struct mtx pci_lock;
3481 struct mtx io_lock;
3482 struct mtx ioctl_lock;
3483 struct mtx mpt_cmd_pool_lock;
3484 struct mtx mfi_cmd_pool_lock;
3485 struct mtx raidmap_lock;
3486 struct mtx aen_lock;
3487 struct mtx stream_lock;
3488 struct selinfo mrsas_select;
3489 uint32_t mrsas_aen_triggered;
3490 uint32_t mrsas_poll_waiting;
3491
3492 struct sema ioctl_count_sema;
3493 uint32_t max_fw_cmds;
3494 uint16_t max_scsi_cmds;
3495 uint32_t max_num_sge;
3496 struct resource *mrsas_irq[MAX_MSIX_COUNT];
3497 void *intr_handle[MAX_MSIX_COUNT];
3498 int irq_id[MAX_MSIX_COUNT];
3499 struct mrsas_irq_context irq_context[MAX_MSIX_COUNT];
3500 int msix_vectors;
3501 int msix_enable;
3502 uint32_t msix_reg_offset[16];
3503 uint8_t mask_interrupts;
3504 uint16_t max_chain_frame_sz;
3505 struct mrsas_mpt_cmd **mpt_cmd_list;
3506 struct mrsas_mfi_cmd **mfi_cmd_list;
3507 TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head;
3508 TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head;
3509 bus_addr_t req_frames_desc_phys;
3510 u_int8_t *req_frames_desc;
3511 u_int8_t *req_desc;
3512 bus_addr_t io_request_frames_phys;
3513 u_int8_t *io_request_frames;
3514 bus_addr_t reply_frames_desc_phys;
3515 u_int16_t last_reply_idx[MAX_MSIX_COUNT];
3516 u_int32_t reply_q_depth;
3517 u_int32_t request_alloc_sz;
3518 u_int32_t reply_alloc_sz;
3519 u_int32_t io_frames_alloc_sz;
3520 u_int32_t chain_frames_alloc_sz;
3521 u_int16_t max_sge_in_main_msg;
3522 u_int16_t max_sge_in_chain;
3523 u_int8_t chain_offset_io_request;
3524 u_int8_t chain_offset_mfi_pthru;
3525 u_int32_t map_sz;
3526 u_int64_t map_id;
3527 u_int64_t pd_seq_map_id;
3528 struct mrsas_mfi_cmd *map_update_cmd;
3529 struct mrsas_mfi_cmd *jbod_seq_cmd;
3530 struct mrsas_mfi_cmd *aen_cmd;
3531 u_int8_t fast_path_io;
3532 void *chan;
3533 void *ocr_chan;
3534 u_int8_t adprecovery;
3535 u_int8_t remove_in_progress;
3536 u_int8_t ocr_thread_active;
3537 u_int8_t do_timedout_reset;
3538 u_int32_t reset_in_progress;
3539 u_int32_t reset_count;
3540 u_int32_t block_sync_cache;
3541 u_int32_t drv_stream_detection;
3542 u_int8_t fw_sync_cache_support;
3543 mrsas_atomic_t target_reset_outstanding;
3544 #define MRSAS_MAX_TM_TARGETS (MRSAS_MAX_PD + MRSAS_MAX_LD_IDS)
3545 struct mrsas_mpt_cmd *target_reset_pool[MRSAS_MAX_TM_TARGETS];
3546
3547 bus_dma_tag_t jbodmap_tag[2];
3548 bus_dmamap_t jbodmap_dmamap[2];
3549 void *jbodmap_mem[2];
3550 bus_addr_t jbodmap_phys_addr[2];
3551
3552 bus_dma_tag_t raidmap_tag[2];
3553 bus_dmamap_t raidmap_dmamap[2];
3554 void *raidmap_mem[2];
3555 bus_addr_t raidmap_phys_addr[2];
3556 bus_dma_tag_t mficmd_frame_tag;
3557 bus_dma_tag_t mficmd_sense_tag;
3558 bus_addr_t evt_detail_phys_addr;
3559 bus_dma_tag_t evt_detail_tag;
3560 bus_dmamap_t evt_detail_dmamap;
3561 struct mrsas_evt_detail *evt_detail_mem;
3562 bus_addr_t pd_info_phys_addr;
3563 bus_dma_tag_t pd_info_tag;
3564 bus_dmamap_t pd_info_dmamap;
3565 struct mrsas_pd_info *pd_info_mem;
3566 struct mrsas_ctrl_info *ctrl_info;
3567 bus_dma_tag_t ctlr_info_tag;
3568 bus_dmamap_t ctlr_info_dmamap;
3569 void *ctlr_info_mem;
3570 bus_addr_t ctlr_info_phys_addr;
3571 u_int32_t max_sectors_per_req;
3572 u_int32_t disableOnlineCtrlReset;
3573 mrsas_atomic_t fw_outstanding;
3574 mrsas_atomic_t prp_count;
3575 mrsas_atomic_t sge_holes;
3576
3577 u_int32_t mrsas_debug;
3578 u_int32_t mrsas_io_timeout;
3579 u_int32_t mrsas_fw_fault_check_delay;
3580 u_int32_t io_cmds_highwater;
3581 u_int8_t UnevenSpanSupport;
3582 struct sysctl_ctx_list sysctl_ctx;
3583 struct sysctl_oid *sysctl_tree;
3584 struct proc *ocr_thread;
3585 u_int32_t last_seq_num;
3586 bus_dma_tag_t el_info_tag;
3587 bus_dmamap_t el_info_dmamap;
3588 void *el_info_mem;
3589 bus_addr_t el_info_phys_addr;
3590 struct mrsas_pd_list pd_list[MRSAS_MAX_PD];
3591 struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD];
3592 struct mrsas_target target_list[MRSAS_MAX_TM_TARGETS];
3593 u_int8_t ld_ids[MRSAS_MAX_LD_IDS];
3594 struct taskqueue *ev_tq;
3595 struct task ev_task;
3596 u_int32_t CurLdCount;
3597 u_int64_t reset_flags;
3598 int lb_pending_cmds;
3599 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT];
3600 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
3601
3602 u_int8_t mrsas_gen3_ctrl;
3603 u_int8_t secure_jbod_support;
3604 u_int8_t use_seqnum_jbod_fp;
3605 /* FW suport for more than 256 PD/JBOD */
3606 u_int32_t support_morethan256jbod;
3607 u_int8_t max256vdSupport;
3608 u_int16_t fw_supported_vd_count;
3609 u_int16_t fw_supported_pd_count;
3610
3611 u_int16_t drv_supported_vd_count;
3612 u_int16_t drv_supported_pd_count;
3613
3614 u_int32_t max_map_sz;
3615 u_int32_t current_map_sz;
3616 u_int32_t old_map_sz;
3617 u_int32_t new_map_sz;
3618 u_int32_t drv_map_sz;
3619
3620 u_int32_t nvme_page_size;
3621 boolean_t is_ventura;
3622 boolean_t is_aero;
3623 boolean_t msix_combined;
3624 boolean_t atomic_desc_support;
3625 u_int16_t maxRaidMapSize;
3626
3627 /* Non dma-able memory. Driver local copy. */
3628 MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
3629 PTR_LD_STREAM_DETECT *streamDetectByLD;
3630 };
3631
3632 /* Compatibility shims for different OS versions */
3633 #if __FreeBSD_version >= 800001
3634 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
3635 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
3636 #define mrsas_kproc_exit(arg) kproc_exit(arg)
3637 #else
3638 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
3639 kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
3640 #define mrsas_kproc_exit(arg) kthread_exit(arg)
3641 #endif
3642
3643 static __inline void
mrsas_clear_bit(int b,volatile void * p)3644 mrsas_clear_bit(int b, volatile void *p)
3645 {
3646 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
3647 }
3648
3649 static __inline void
mrsas_set_bit(int b,volatile void * p)3650 mrsas_set_bit(int b, volatile void *p)
3651 {
3652 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
3653 }
3654
3655 static __inline int
mrsas_test_bit(int b,volatile void * p)3656 mrsas_test_bit(int b, volatile void *p)
3657 {
3658 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f));
3659 }
3660
3661 #endif /* MRSAS_H */
3662