1 /*-
2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #ifndef MLX5_DEVICE_H
27 #define MLX5_DEVICE_H
28
29 #include <linux/types.h>
30 #include <rdma/ib_verbs.h>
31 #include <dev/mlx5/mlx5_ifc.h>
32
33 #define FW_INIT_TIMEOUT_MILI 2000
34 #define FW_INIT_WAIT_MS 2
35 #define FW_PRE_INIT_TIMEOUT_MILI 120000
36 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
37
38 #if defined(__LITTLE_ENDIAN)
39 #define MLX5_SET_HOST_ENDIANNESS 0
40 #elif defined(__BIG_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0x80
42 #else
43 #error Host endianness not defined
44 #endif
45
46 /* helper macros */
47 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
48 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
49 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld)
50 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
51 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
52 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
53 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
59 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
60
61 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
62 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
63 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
64 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
65 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
66 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
67 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
68 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
69
70 /* insert a value to a struct */
71 #define MLX5_SET(typ, p, fld, v) do { \
72 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
73 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
74 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
75 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
76 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
77 << __mlx5_dw_bit_off(typ, fld))); \
78 } while (0)
79
80 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
81 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
82 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
83 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
84 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
85 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
86 << __mlx5_dw_bit_off(typ, fld))); \
87 } while (0)
88
89 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
90 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
91 __mlx5_mask(typ, fld))
92
93 #define MLX5_GET_PR(typ, p, fld) ({ \
94 u32 ___t = MLX5_GET(typ, p, fld); \
95 pr_debug(#fld " = 0x%x\n", ___t); \
96 ___t; \
97 })
98
99 #define __MLX5_SET64(typ, p, fld, v) do { \
100 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
101 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
102 } while (0)
103
104 #define MLX5_SET64(typ, p, fld, v) do { \
105 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
106 __MLX5_SET64(typ, p, fld, v); \
107 } while (0)
108
109 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
110 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
111 __MLX5_SET64(typ, p, fld[idx], v); \
112 } while (0)
113
114 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
115
116 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
117 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
118 __mlx5_mask16(typ, fld))
119
120 #define MLX5_SET16(typ, p, fld, v) do { \
121 u16 _v = v; \
122 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
123 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
124 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
125 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
126 << __mlx5_16_bit_off(typ, fld))); \
127 } while (0)
128
129 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
130 __mlx5_64_off(typ, fld)))
131
132 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
133 type_t tmp; \
134 switch (sizeof(tmp)) { \
135 case sizeof(u8): \
136 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
137 break; \
138 case sizeof(u16): \
139 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
140 break; \
141 case sizeof(u32): \
142 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
143 break; \
144 case sizeof(u64): \
145 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
146 break; \
147 } \
148 tmp; \
149 })
150
151 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
152 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
153 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
154 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
155 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
156 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
157
158 /* insert a value to a struct */
159 #define MLX5_VSC_SET(typ, p, fld, v) do { \
160 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
161 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
162 *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \
163 cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \
164 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
165 << __mlx5_dw_bit_off(typ, fld))); \
166 } while (0)
167
168 #define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\
169 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
170 __mlx5_mask(typ, fld))
171
172 #define MLX5_VSC_GET_PR(typ, p, fld) ({ \
173 u32 ___t = MLX5_VSC_GET(typ, p, fld); \
174 pr_debug(#fld " = 0x%x\n", ___t); \
175 ___t; \
176 })
177
178 enum {
179 MLX5_MAX_COMMANDS = 32,
180 MLX5_CMD_DATA_BLOCK_SIZE = 512,
181 MLX5_CMD_MBOX_SIZE = 1024,
182 MLX5_PCI_CMD_XPORT = 7,
183 MLX5_MKEY_BSF_OCTO_SIZE = 4,
184 MLX5_MAX_PSVS = 4,
185 };
186
187 enum {
188 MLX5_EXTENDED_UD_AV = 0x80000000,
189 };
190
191 enum {
192 MLX5_CQ_FLAGS_OI = 2,
193 };
194
195 enum {
196 MLX5_STAT_RATE_OFFSET = 5,
197 };
198
199 enum {
200 MLX5_INLINE_SEG = 0x80000000,
201 };
202
203 enum {
204 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
205 };
206
207 enum {
208 MLX5_MIN_PKEY_TABLE_SIZE = 128,
209 MLX5_MAX_LOG_PKEY_TABLE = 5,
210 };
211
212 enum {
213 MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31
214 };
215
216 enum {
217 MLX5_PERM_LOCAL_READ = 1 << 2,
218 MLX5_PERM_LOCAL_WRITE = 1 << 3,
219 MLX5_PERM_REMOTE_READ = 1 << 4,
220 MLX5_PERM_REMOTE_WRITE = 1 << 5,
221 MLX5_PERM_ATOMIC = 1 << 6,
222 MLX5_PERM_UMR_EN = 1 << 7,
223 };
224
225 enum {
226 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
227 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
228 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
229 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
230 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
231 };
232
233 enum {
234 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
235 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
236 MLX5_MKEY_BSF_EN = 1 << 30,
237 MLX5_MKEY_LEN64 = 1U << 31,
238 };
239
240 enum {
241 MLX5_EN_RD = (u64)1,
242 MLX5_EN_WR = (u64)2
243 };
244
245 enum {
246 MLX5_ADAPTER_PAGE_SHIFT = 12,
247 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
248 };
249
250 enum {
251 MLX5_BFREGS_PER_UAR = 4,
252 MLX5_MAX_UARS = 1 << 8,
253 MLX5_NON_FP_BFREGS_PER_UAR = 2,
254 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
255 MLX5_NON_FP_BFREGS_PER_UAR,
256 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
257 MLX5_NON_FP_BFREGS_PER_UAR,
258 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
259 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
260 MLX5_MIN_DYN_BFREGS = 512,
261 MLX5_MAX_DYN_BFREGS = 1024,
262 };
263
264 enum {
265 MLX5_MKEY_MASK_LEN = 1ull << 0,
266 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
267 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
268 MLX5_MKEY_MASK_PD = 1ull << 7,
269 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
270 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
271 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
272 MLX5_MKEY_MASK_KEY = 1ull << 13,
273 MLX5_MKEY_MASK_QPN = 1ull << 14,
274 MLX5_MKEY_MASK_LR = 1ull << 17,
275 MLX5_MKEY_MASK_LW = 1ull << 18,
276 MLX5_MKEY_MASK_RR = 1ull << 19,
277 MLX5_MKEY_MASK_RW = 1ull << 20,
278 MLX5_MKEY_MASK_A = 1ull << 21,
279 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
280 MLX5_MKEY_MASK_FREE = 1ull << 29,
281 };
282
283 enum {
284 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
285
286 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
287 MLX5_UMR_CHECK_FREE = (2 << 5),
288
289 MLX5_UMR_INLINE = (1 << 7),
290 };
291
292 #define MLX5_UMR_MTT_ALIGNMENT 0x40
293 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
294 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
295
296 enum {
297 MLX5_EVENT_QUEUE_TYPE_QP = 0,
298 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
299 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
300 };
301
302 enum {
303 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
304 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
305 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
306 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
307 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
308 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
309 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
310 };
311
312 enum {
313 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1,
314 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE,
315 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE,
316 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE,
317 MLX5_MAX_INLINE_RECEIVE_SIZE = 64
318 };
319
320 enum {
321 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
322 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
323 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
324 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
325 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21,
326 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
327 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
328 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
329 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33,
330 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34,
331 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
332 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
333 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
334 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48,
335 };
336
337 enum {
338 MLX5_ROCE_VERSION_1 = 0,
339 MLX5_ROCE_VERSION_1_5 = 1,
340 MLX5_ROCE_VERSION_2 = 2,
341 };
342
343 enum {
344 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
345 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5,
346 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
347 };
348
349 enum {
350 MLX5_ROCE_L3_TYPE_IPV4 = 0,
351 MLX5_ROCE_L3_TYPE_IPV6 = 1,
352 };
353
354 enum {
355 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
356 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
357 };
358
359 enum {
360 MLX5_OPCODE_NOP = 0x00,
361 MLX5_OPCODE_SEND_INVAL = 0x01,
362 MLX5_OPCODE_RDMA_WRITE = 0x08,
363 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
364 MLX5_OPCODE_SEND = 0x0a,
365 MLX5_OPCODE_SEND_IMM = 0x0b,
366 MLX5_OPCODE_LSO = 0x0e,
367 MLX5_OPCODE_RDMA_READ = 0x10,
368 MLX5_OPCODE_ATOMIC_CS = 0x11,
369 MLX5_OPCODE_ATOMIC_FA = 0x12,
370 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
371 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
372 MLX5_OPCODE_BIND_MW = 0x18,
373 MLX5_OPCODE_CONFIG_CMD = 0x1f,
374 MLX5_OPCODE_DUMP = 0x23,
375
376 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
377 MLX5_RECV_OPCODE_SEND = 0x01,
378 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
379 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
380
381 MLX5_CQE_OPCODE_ERROR = 0x1e,
382 MLX5_CQE_OPCODE_RESIZE = 0x16,
383
384 MLX5_OPCODE_SET_PSV = 0x20,
385 MLX5_OPCODE_GET_PSV = 0x21,
386 MLX5_OPCODE_CHECK_PSV = 0x22,
387 MLX5_OPCODE_RGET_PSV = 0x26,
388 MLX5_OPCODE_RCHECK_PSV = 0x27,
389
390 MLX5_OPCODE_UMR = 0x25,
391 MLX5_OPCODE_QOS_REMAP = 0x2a,
392
393 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15),
394 };
395
396 enum {
397 MLX5_OPCODE_MOD_UMR_UMR = 0x0,
398 MLX5_OPCODE_MOD_UMR_TLS_TIS_STATIC_PARAMS = 0x1,
399 MLX5_OPCODE_MOD_UMR_TLS_TIR_STATIC_PARAMS = 0x2,
400 };
401
402 enum {
403 MLX5_OPCODE_MOD_PSV_PSV = 0x0,
404 MLX5_OPCODE_MOD_PSV_TLS_TIS_PROGRESS_PARAMS = 0x1,
405 MLX5_OPCODE_MOD_PSV_TLS_TIR_PROGRESS_PARAMS = 0x2,
406 };
407
408 enum {
409 MLX5_SET_PORT_RESET_QKEY = 0,
410 MLX5_SET_PORT_GUID0 = 16,
411 MLX5_SET_PORT_NODE_GUID = 17,
412 MLX5_SET_PORT_SYS_GUID = 18,
413 MLX5_SET_PORT_GID_TABLE = 19,
414 MLX5_SET_PORT_PKEY_TABLE = 20,
415 };
416
417 enum {
418 MLX5_MAX_PAGE_SHIFT = 31
419 };
420
421 enum {
422 MLX5_CAP_OFF_CMDIF_CSUM = 46,
423 };
424
425 enum {
426 /*
427 * Max wqe size for rdma read is 512 bytes, so this
428 * limits our max_sge_rd as the wqe needs to fit:
429 * - ctrl segment (16 bytes)
430 * - rdma segment (16 bytes)
431 * - scatter elements (16 bytes each)
432 */
433 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
434 };
435
436 struct mlx5_cmd_layout {
437 u8 type;
438 u8 rsvd0[3];
439 __be32 inlen;
440 __be64 in_ptr;
441 __be32 in[4];
442 __be32 out[4];
443 __be64 out_ptr;
444 __be32 outlen;
445 u8 token;
446 u8 sig;
447 u8 rsvd1;
448 u8 status_own;
449 };
450
451 enum mlx5_fatal_assert_bit_offsets {
452 MLX5_RFR_OFFSET = 31,
453 };
454
455 struct mlx5_health_buffer {
456 __be32 assert_var[5];
457 __be32 rsvd0[3];
458 __be32 assert_exit_ptr;
459 __be32 assert_callra;
460 __be32 rsvd1[2];
461 __be32 fw_ver;
462 __be32 hw_id;
463 __be32 rfr;
464 u8 irisc_index;
465 u8 synd;
466 __be16 ext_synd;
467 };
468
469 enum mlx5_initializing_bit_offsets {
470 MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
471 };
472
473 enum mlx5_cmd_addr_l_sz_offset {
474 MLX5_NIC_IFC_OFFSET = 8,
475 };
476
477 struct mlx5_init_seg {
478 __be32 fw_rev;
479 __be32 cmdif_rev_fw_sub;
480 __be32 rsvd0[2];
481 __be32 cmdq_addr_h;
482 __be32 cmdq_addr_l_sz;
483 __be32 cmd_dbell;
484 __be32 rsvd1[120];
485 __be32 initializing;
486 struct mlx5_health_buffer health;
487 __be32 rsvd2[880];
488 __be32 internal_timer_h;
489 __be32 internal_timer_l;
490 __be32 rsvd3[2];
491 __be32 health_counter;
492 __be32 rsvd4[1019];
493 __be64 ieee1588_clk;
494 __be32 ieee1588_clk_type;
495 __be32 clr_intx;
496 };
497
498 struct mlx5_eqe_comp {
499 __be32 reserved[6];
500 __be32 cqn;
501 };
502
503 struct mlx5_eqe_qp_srq {
504 __be32 reserved[6];
505 __be32 qp_srq_n;
506 };
507
508 struct mlx5_eqe_cq_err {
509 __be32 cqn;
510 u8 reserved1[7];
511 u8 syndrome;
512 };
513
514 struct mlx5_eqe_port_state {
515 u8 reserved0[8];
516 u8 port;
517 };
518
519 struct mlx5_eqe_gpio {
520 __be32 reserved0[2];
521 __be64 gpio_event;
522 };
523
524 struct mlx5_eqe_congestion {
525 u8 type;
526 u8 rsvd0;
527 u8 congestion_level;
528 };
529
530 struct mlx5_eqe_stall_vl {
531 u8 rsvd0[3];
532 u8 port_vl;
533 };
534
535 struct mlx5_eqe_cmd {
536 __be32 vector;
537 __be32 rsvd[6];
538 };
539
540 struct mlx5_eqe_page_req {
541 u8 rsvd0[2];
542 __be16 func_id;
543 __be32 num_pages;
544 __be32 rsvd1[5];
545 };
546
547 struct mlx5_eqe_vport_change {
548 u8 rsvd0[2];
549 __be16 vport_num;
550 __be32 rsvd1[6];
551 };
552
553
554 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
555 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
556
557 enum {
558 MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1,
559 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
560 MLX5_MODULE_STATUS_ERROR = 0x3,
561 MLX5_MODULE_STATUS_NUM ,
562 };
563
564 enum {
565 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0,
566 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1,
567 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2,
568 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3,
569 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4,
570 MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5,
571 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6,
572 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7,
573 MLX5_MODULE_EVENT_ERROR_PMD_TYPE_NOT_ENABLED = 0x8,
574 MLX5_MODULE_EVENT_ERROR_LASTER_TEC_FAILURE = 0x9,
575 MLX5_MODULE_EVENT_ERROR_HIGH_CURRENT = 0xa,
576 MLX5_MODULE_EVENT_ERROR_HIGH_VOLTAGE = 0xb,
577 MLX5_MODULE_EVENT_ERROR_PCIE_SYS_POWER_SLOT_EXCEEDED = 0xc,
578 MLX5_MODULE_EVENT_ERROR_HIGH_POWER = 0xd,
579 MLX5_MODULE_EVENT_ERROR_MODULE_STATE_MACHINE_FAULT = 0xe,
580 MLX5_MODULE_EVENT_ERROR_NUM ,
581 };
582
583 struct mlx5_eqe_port_module_event {
584 u8 rsvd0;
585 u8 module;
586 u8 rsvd1;
587 u8 module_status;
588 u8 rsvd2[2];
589 u8 error_type;
590 };
591
592 struct mlx5_eqe_general_notification_event {
593 u32 rq_user_index_delay_drop;
594 u32 rsvd0[6];
595 };
596
597 struct mlx5_eqe_temp_warning {
598 __be64 sensor_warning_msb;
599 __be64 sensor_warning_lsb;
600 } __packed;
601
602 union ev_data {
603 __be32 raw[7];
604 struct mlx5_eqe_cmd cmd;
605 struct mlx5_eqe_comp comp;
606 struct mlx5_eqe_qp_srq qp_srq;
607 struct mlx5_eqe_cq_err cq_err;
608 struct mlx5_eqe_port_state port;
609 struct mlx5_eqe_gpio gpio;
610 struct mlx5_eqe_congestion cong;
611 struct mlx5_eqe_stall_vl stall_vl;
612 struct mlx5_eqe_page_req req_pages;
613 struct mlx5_eqe_port_module_event port_module_event;
614 struct mlx5_eqe_vport_change vport_change;
615 struct mlx5_eqe_general_notification_event general_notifications;
616 struct mlx5_eqe_temp_warning temp_warning;
617 } __packed;
618
619 struct mlx5_eqe {
620 u8 rsvd0;
621 u8 type;
622 u8 rsvd1;
623 u8 sub_type;
624 __be32 rsvd2[7];
625 union ev_data data;
626 __be16 rsvd3;
627 u8 signature;
628 u8 owner;
629 } __packed;
630
631 struct mlx5_cmd_prot_block {
632 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
633 u8 rsvd0[48];
634 __be64 next;
635 __be32 block_num;
636 u8 rsvd1;
637 u8 token;
638 u8 ctrl_sig;
639 u8 sig;
640 };
641
642 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \
643 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE)
644 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block));
645 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE);
646
647 enum {
648 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
649 };
650
651 struct mlx5_err_cqe {
652 u8 rsvd0[32];
653 __be32 srqn;
654 u8 rsvd1[18];
655 u8 vendor_err_synd;
656 u8 syndrome;
657 __be32 s_wqe_opcode_qpn;
658 __be16 wqe_counter;
659 u8 signature;
660 u8 op_own;
661 };
662
663 struct mlx5_cqe64 {
664 u8 tls_outer_l3_tunneled;
665 u8 rsvd0;
666 __be16 wqe_id;
667 u8 lro_tcppsh_abort_dupack;
668 u8 lro_min_ttl;
669 __be16 lro_tcp_win;
670 __be32 lro_ack_seq_num;
671 __be32 rss_hash_result;
672 u8 rss_hash_type;
673 u8 ml_path;
674 u8 rsvd20[2];
675 __be16 check_sum;
676 __be16 slid;
677 __be32 flags_rqpn;
678 u8 hds_ip_ext;
679 u8 l4_hdr_type_etc;
680 __be16 vlan_info;
681 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
682 __be32 imm_inval_pkey;
683 u8 rsvd40[4];
684 __be32 byte_cnt;
685 __be64 timestamp;
686 __be32 sop_drop_qpn;
687 __be16 wqe_counter;
688 u8 signature;
689 u8 op_own;
690 };
691
692 #define MLX5_CQE_TSTMP_PTP (1ULL << 63)
693
get_cqe_opcode(struct mlx5_cqe64 * cqe)694 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
695 {
696 return (cqe->op_own >> 4);
697 }
698
get_cqe_lro_timestamp_valid(struct mlx5_cqe64 * cqe)699 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe)
700 {
701 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1;
702 }
703
get_cqe_lro_tcppsh(struct mlx5_cqe64 * cqe)704 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
705 {
706 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
707 }
708
get_cqe_l4_hdr_type(struct mlx5_cqe64 * cqe)709 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
710 {
711 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
712 }
713
get_cqe_vlan(struct mlx5_cqe64 * cqe)714 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe)
715 {
716 return be16_to_cpu(cqe->vlan_info) & 0xfff;
717 }
718
get_cqe_smac(struct mlx5_cqe64 * cqe,u8 * smac)719 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac)
720 {
721 memcpy(smac, &cqe->rss_hash_type , 4);
722 memcpy(smac + 4, &cqe->slid , 2);
723 }
724
cqe_has_vlan(struct mlx5_cqe64 * cqe)725 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
726 {
727 return cqe->l4_hdr_type_etc & 0x1;
728 }
729
cqe_is_tunneled(struct mlx5_cqe64 * cqe)730 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
731 {
732 return cqe->tls_outer_l3_tunneled & 0x1;
733 }
734
735 enum {
736 CQE_L4_HDR_TYPE_NONE = 0x0,
737 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
738 CQE_L4_HDR_TYPE_UDP = 0x2,
739 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
740 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
741 };
742
743 enum {
744 /* source L3 hash types */
745 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0,
746 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0,
747 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0,
748
749 /* destination L3 hash types */
750 CQE_RSS_DST_HTYPE_IP = 0x3 << 2,
751 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2,
752 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2,
753
754 /* source L4 hash types */
755 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4,
756 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4,
757 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4,
758 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4,
759
760 /* destination L4 hash types */
761 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6,
762 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6,
763 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6,
764 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6,
765 };
766
767 enum {
768 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
769 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
770 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
771 };
772
773 enum {
774 CQE_L2_OK = 1 << 0,
775 CQE_L3_OK = 1 << 1,
776 CQE_L4_OK = 1 << 2,
777 };
778
779 struct mlx5_sig_err_cqe {
780 u8 rsvd0[16];
781 __be32 expected_trans_sig;
782 __be32 actual_trans_sig;
783 __be32 expected_reftag;
784 __be32 actual_reftag;
785 __be16 syndrome;
786 u8 rsvd22[2];
787 __be32 mkey;
788 __be64 err_offset;
789 u8 rsvd30[8];
790 __be32 qpn;
791 u8 rsvd38[2];
792 u8 signature;
793 u8 op_own;
794 };
795
796 struct mlx5_wqe_srq_next_seg {
797 u8 rsvd0[2];
798 __be16 next_wqe_index;
799 u8 signature;
800 u8 rsvd1[11];
801 };
802
803 union mlx5_ext_cqe {
804 struct ib_grh grh;
805 u8 inl[64];
806 };
807
808 struct mlx5_cqe128 {
809 union mlx5_ext_cqe inl_grh;
810 struct mlx5_cqe64 cqe64;
811 };
812
813 enum {
814 MLX5_MKEY_STATUS_FREE = 1 << 6,
815 };
816
817 struct mlx5_mkey_seg {
818 /* This is a two bit field occupying bits 31-30.
819 * bit 31 is always 0,
820 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
821 */
822 u8 status;
823 u8 pcie_control;
824 u8 flags;
825 u8 version;
826 __be32 qpn_mkey7_0;
827 u8 rsvd1[4];
828 __be32 flags_pd;
829 __be64 start_addr;
830 __be64 len;
831 __be32 bsfs_octo_size;
832 u8 rsvd2[16];
833 __be32 xlt_oct_size;
834 u8 rsvd3[3];
835 u8 log2_page_size;
836 u8 rsvd4[4];
837 };
838
839 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
840
841 enum {
842 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
843 };
844
mlx5_host_is_le(void)845 static inline int mlx5_host_is_le(void)
846 {
847 #if defined(__LITTLE_ENDIAN)
848 return 1;
849 #elif defined(__BIG_ENDIAN)
850 return 0;
851 #else
852 #error Host endianness not defined
853 #endif
854 }
855
856 #define MLX5_CMD_OP_MAX 0x939
857
858 enum {
859 VPORT_STATE_DOWN = 0x0,
860 VPORT_STATE_UP = 0x1,
861 VPORT_STATE_FOLLOW = 0x2,
862 };
863
864 enum {
865 MLX5_L3_PROT_TYPE_IPV4 = 0,
866 MLX5_L3_PROT_TYPE_IPV6 = 1,
867 };
868
869 enum {
870 MLX5_L4_PROT_TYPE_TCP = 0,
871 MLX5_L4_PROT_TYPE_UDP = 1,
872 };
873
874 enum {
875 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
876 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
877 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
878 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
879 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
880 };
881
882 enum {
883 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
884 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
885 MLX5_MATCH_INNER_HEADERS = 1 << 2,
886
887 };
888
889 enum {
890 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
891 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2,
892 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3,
893 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
894 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5,
895 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6,
896 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7,
897 };
898
899 enum {
900 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0,
901 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1,
902 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2
903 };
904
905 enum {
906 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0,
907 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1,
908 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2,
909 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3
910 };
911
912 enum {
913 MLX5_UC_ADDR_CHANGE = (1 << 0),
914 MLX5_MC_ADDR_CHANGE = (1 << 1),
915 MLX5_VLAN_CHANGE = (1 << 2),
916 MLX5_PROMISC_CHANGE = (1 << 3),
917 MLX5_MTU_CHANGE = (1 << 4),
918 };
919
920 enum mlx5_list_type {
921 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0,
922 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1,
923 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2,
924 };
925
926 enum {
927 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
928 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
929 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
930 };
931
932 /* MLX5 DEV CAPs */
933
934 /* TODO: EAT.ME */
935 enum mlx5_cap_mode {
936 HCA_CAP_OPMOD_GET_MAX = 0,
937 HCA_CAP_OPMOD_GET_CUR = 1,
938 };
939
940 enum mlx5_cap_type {
941 MLX5_CAP_GENERAL = 0,
942 MLX5_CAP_ETHERNET_OFFLOADS,
943 MLX5_CAP_ODP,
944 MLX5_CAP_ATOMIC,
945 MLX5_CAP_ROCE,
946 MLX5_CAP_IPOIB_OFFLOADS,
947 MLX5_CAP_EOIB_OFFLOADS,
948 MLX5_CAP_FLOW_TABLE,
949 MLX5_CAP_ESWITCH_FLOW_TABLE,
950 MLX5_CAP_ESWITCH,
951 MLX5_CAP_SNAPSHOT,
952 MLX5_CAP_VECTOR_CALC,
953 MLX5_CAP_QOS,
954 MLX5_CAP_DEBUG,
955 MLX5_CAP_NVME,
956 MLX5_CAP_DMC,
957 MLX5_CAP_DEC,
958 MLX5_CAP_TLS,
959 /* NUM OF CAP Types */
960 MLX5_CAP_NUM
961 };
962
963 enum mlx5_qcam_reg_groups {
964 MLX5_QCAM_REGS_FIRST_128 = 0x0,
965 };
966
967 enum mlx5_qcam_feature_groups {
968 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
969 };
970
971 enum mlx5_pcam_reg_groups {
972 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
973 };
974
975 enum mlx5_pcam_feature_groups {
976 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
977 };
978
979 enum mlx5_mcam_reg_groups {
980 MLX5_MCAM_REGS_FIRST_128 = 0x0,
981 };
982
983 enum mlx5_mcam_feature_groups {
984 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
985 };
986
987 /* GET Dev Caps macros */
988 #define MLX5_CAP_GEN(mdev, cap) \
989 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
990
991 #define MLX5_CAP_GEN_64(mdev, cap) \
992 MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
993
994 #define MLX5_CAP_GEN_MAX(mdev, cap) \
995 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
996
997 #define MLX5_CAP_ETH(mdev, cap) \
998 MLX5_GET(per_protocol_networking_offload_caps,\
999 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1000
1001 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1002 MLX5_GET(per_protocol_networking_offload_caps,\
1003 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1004
1005 #define MLX5_CAP_ROCE(mdev, cap) \
1006 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1007
1008 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1009 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1010
1011 #define MLX5_CAP_ATOMIC(mdev, cap) \
1012 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1013
1014 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1015 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1016
1017 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1018 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1019
1020 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1021 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1022
1023 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1024 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1025
1026 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1027 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1028
1029 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1030 MLX5_GET(flow_table_eswitch_cap, \
1031 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1032
1033 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1034 MLX5_GET(flow_table_eswitch_cap, \
1035 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1036
1037 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1038 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1039
1040 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1041 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1042
1043 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1044 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1045
1046 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1047 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1048
1049 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1050 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1051
1052 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1053 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1054
1055 #define MLX5_CAP_ESW(mdev, cap) \
1056 MLX5_GET(e_switch_cap, \
1057 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1058
1059 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1060 MLX5_GET(e_switch_cap, \
1061 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1062
1063 #define MLX5_CAP_ODP(mdev, cap)\
1064 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1065
1066 #define MLX5_CAP_ODP_MAX(mdev, cap)\
1067 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1068
1069 #define MLX5_CAP_SNAPSHOT(mdev, cap) \
1070 MLX5_GET(snapshot_cap, \
1071 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1072
1073 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \
1074 MLX5_GET(snapshot_cap, \
1075 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1076
1077 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \
1078 MLX5_GET(per_protocol_networking_offload_caps,\
1079 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1080
1081 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \
1082 MLX5_GET(per_protocol_networking_offload_caps,\
1083 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1084
1085 #define MLX5_CAP_DEBUG(mdev, cap) \
1086 MLX5_GET(debug_cap, \
1087 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1088
1089 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \
1090 MLX5_GET(debug_cap, \
1091 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1092
1093 #define MLX5_CAP_QOS(mdev, cap) \
1094 MLX5_GET(qos_cap,\
1095 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1096
1097 #define MLX5_CAP_QOS_MAX(mdev, cap) \
1098 MLX5_GET(qos_cap,\
1099 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1100
1101 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1102 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1103
1104 #define MLX5_CAP_PCAM_REG(mdev, reg) \
1105 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1106
1107 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1108 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1109
1110 #define MLX5_CAP_MCAM_REG(mdev, reg) \
1111 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1112
1113 #define MLX5_CAP_QCAM_REG(mdev, fld) \
1114 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1115
1116 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1117 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1118
1119 #define MLX5_CAP_FPGA(mdev, cap) \
1120 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1121
1122 #define MLX5_CAP64_FPGA(mdev, cap) \
1123 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1124
1125 #define MLX5_CAP_TLS(mdev, cap) \
1126 MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap)
1127
1128 enum {
1129 MLX5_CMD_STAT_OK = 0x0,
1130 MLX5_CMD_STAT_INT_ERR = 0x1,
1131 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1132 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1133 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1134 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1135 MLX5_CMD_STAT_RES_BUSY = 0x6,
1136 MLX5_CMD_STAT_LIM_ERR = 0x8,
1137 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1138 MLX5_CMD_STAT_IX_ERR = 0xa,
1139 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1140 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1141 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1142 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1143 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1144 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1145 };
1146
1147 enum {
1148 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1149 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1150 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1151 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1152 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1153 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6,
1154 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1155 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1156 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1157 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1158 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1159 };
1160
1161 enum {
1162 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1163 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1,
1164 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2,
1165 };
1166
1167 enum {
1168 MLX5_CAP_PORT_TYPE_IB = 0x0,
1169 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1170 };
1171
1172 enum {
1173 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0,
1174 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1,
1175 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2
1176 };
1177
1178 enum mlx5_inline_modes {
1179 MLX5_INLINE_MODE_NONE,
1180 MLX5_INLINE_MODE_L2,
1181 MLX5_INLINE_MODE_IP,
1182 MLX5_INLINE_MODE_TCP_UDP,
1183 };
1184
1185 enum {
1186 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2,
1187 };
1188
mlx5_to_sw_pkey_sz(int pkey_sz)1189 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1190 {
1191 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1192 return 0;
1193 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1194 }
1195
1196 struct mlx5_ifc_mcia_reg_bits {
1197 u8 l[0x1];
1198 u8 reserved_0[0x7];
1199 u8 module[0x8];
1200 u8 reserved_1[0x8];
1201 u8 status[0x8];
1202
1203 u8 i2c_device_address[0x8];
1204 u8 page_number[0x8];
1205 u8 device_address[0x10];
1206
1207 u8 reserved_2[0x10];
1208 u8 size[0x10];
1209
1210 u8 reserved_3[0x20];
1211
1212 u8 dword_0[0x20];
1213 u8 dword_1[0x20];
1214 u8 dword_2[0x20];
1215 u8 dword_3[0x20];
1216 u8 dword_4[0x20];
1217 u8 dword_5[0x20];
1218 u8 dword_6[0x20];
1219 u8 dword_7[0x20];
1220 u8 dword_8[0x20];
1221 u8 dword_9[0x20];
1222 u8 dword_10[0x20];
1223 u8 dword_11[0x20];
1224 };
1225
1226 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c
1227
1228 struct mlx5_mini_cqe8 {
1229 union {
1230 __be32 rx_hash_result;
1231 __be16 checksum;
1232 __be16 rsvd;
1233 struct {
1234 __be16 wqe_counter;
1235 u8 s_wqe_opcode;
1236 u8 reserved;
1237 } s_wqe_info;
1238 };
1239 __be32 byte_cnt;
1240 };
1241
1242 enum {
1243 MLX5_NO_INLINE_DATA,
1244 MLX5_INLINE_DATA32_SEG,
1245 MLX5_INLINE_DATA64_SEG,
1246 MLX5_COMPRESSED,
1247 };
1248
1249 enum mlx5_exp_cqe_zip_recv_type {
1250 MLX5_CQE_FORMAT_HASH,
1251 MLX5_CQE_FORMAT_CSUM,
1252 };
1253
1254 #define MLX5E_CQE_FORMAT_MASK 0xc
mlx5_get_cqe_format(const struct mlx5_cqe64 * cqe)1255 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe)
1256 {
1257 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2;
1258 }
1259
1260 enum {
1261 MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
1262 MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
1263 };
1264
1265 enum {
1266 MLX5_FRL_LEVEL3 = 0x8,
1267 MLX5_FRL_LEVEL6 = 0x40,
1268 };
1269
1270 /* 8 regular priorities + 1 for multicast */
1271 #define MLX5_NUM_BYPASS_FTS 9
1272
1273 #endif /* MLX5_DEVICE_H */
1274