1 /* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */ 2 3 /* 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Ralph Campbell and Rick Macklem. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 37 * 38 * machConst.h -- 39 * 40 * Machine dependent constants. 41 * 42 * Copyright (C) 1989 Digital Equipment Corporation. 43 * Permission to use, copy, modify, and distribute this software and 44 * its documentation for any purpose and without fee is hereby granted, 45 * provided that the above copyright notice appears in all copies. 46 * Digital Equipment Corporation makes no representations about the 47 * suitability of this software for any purpose. It is provided "as is" 48 * without express or implied warranty. 49 * 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 51 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 52 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 53 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 54 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 55 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 56 */ 57 58 #ifndef _MIPS_CPUREGS_H_ 59 #define _MIPS_CPUREGS_H_ 60 61 #ifndef _KVM_MINIDUMP 62 #include <machine/cca.h> 63 #endif 64 65 /* 66 * Address space. 67 * 32-bit mips CPUS partition their 32-bit address space into four segments: 68 * 69 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 70 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 71 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 72 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 73 * 74 * Caching of mapped addresses is controlled by bits in the TLB entry. 75 */ 76 77 #define MIPS_KSEG0_LARGEST_PHYS (0x20000000) 78 #define MIPS_KSEG0_PHYS_MASK (0x1fffffff) 79 #define MIPS_XKPHYS_LARGEST_PHYS (0x10000000000) /* 40 bit PA */ 80 #define MIPS_XKPHYS_PHYS_MASK (0x0ffffffffff) 81 82 #ifndef LOCORE 83 #define MIPS_KUSEG_START 0x00000000 84 #define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000) 85 #define MIPS_KSEG0_END ((intptr_t)(int32_t)0x9fffffff) 86 #define MIPS_KSEG1_START ((intptr_t)(int32_t)0xa0000000) 87 #define MIPS_KSEG1_END ((intptr_t)(int32_t)0xbfffffff) 88 #define MIPS_KSSEG_START ((intptr_t)(int32_t)0xc0000000) 89 #define MIPS_KSSEG_END ((intptr_t)(int32_t)0xdfffffff) 90 #define MIPS_KSEG3_START ((intptr_t)(int32_t)0xe0000000) 91 #define MIPS_KSEG3_END ((intptr_t)(int32_t)0xffffffff) 92 #define MIPS_KSEG2_START MIPS_KSSEG_START 93 #define MIPS_KSEG2_END MIPS_KSSEG_END 94 #endif 95 96 #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) 97 #define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START) 98 #define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) 99 #define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) 100 101 #define MIPS_IS_KSEG0_ADDR(x) \ 102 (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \ 103 ((vm_offset_t)(x) <= MIPS_KSEG0_END)) 104 #define MIPS_IS_KSEG1_ADDR(x) \ 105 (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \ 106 ((vm_offset_t)(x) <= MIPS_KSEG1_END)) 107 #define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \ 108 MIPS_IS_KSEG1_ADDR(x)) 109 110 #define MIPS_PHYS_TO_XKPHYS(cca,x) \ 111 ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) 112 #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \ 113 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CACHED) << 59) | (x)) 114 #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \ 115 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) | (x)) 116 117 #define MIPS_XKPHYS_TO_PHYS(x) ((uintptr_t)(x) & MIPS_XKPHYS_PHYS_MASK) 118 119 #define MIPS_XKPHYS_START 0x8000000000000000 120 #define MIPS_XKPHYS_END 0xbfffffffffffffff 121 #define MIPS_XUSEG_START 0x0000000000000000 122 #define MIPS_XUSEG_END 0x0000010000000000 123 #define MIPS_XKSEG_START 0xc000000000000000 124 #define MIPS_XKSEG_END 0xc00000ff80000000 125 #define MIPS_XKSEG_COMPAT32_START 0xffffffff80000000 126 #define MIPS_XKSEG_COMPAT32_END 0xffffffffffffffff 127 #define MIPS_XKSEG_TO_COMPAT32(va) ((va) & 0xffffffff) 128 129 #ifdef __mips_n64 130 #define MIPS_DIRECT_MAPPABLE(pa) 1 131 #define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_XKPHYS_CACHED(pa) 132 #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_XKPHYS_UNCACHED(pa) 133 #define MIPS_DIRECT_TO_PHYS(va) MIPS_XKPHYS_TO_PHYS(va) 134 #else 135 #define MIPS_DIRECT_MAPPABLE(pa) ((pa) < MIPS_KSEG0_LARGEST_PHYS) 136 #define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_KSEG0(pa) 137 #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_KSEG1(pa) 138 #define MIPS_DIRECT_TO_PHYS(va) MIPS_KSEG0_TO_PHYS(va) 139 #endif 140 141 /* CPU dependent mtc0 hazard hook */ 142 #if defined(CPU_CNMIPS) || defined(CPU_RMI) 143 #define COP0_SYNC 144 #elif defined(CPU_NLM) 145 #define COP0_SYNC .word 0xc0 /* ehb */ 146 #elif defined(CPU_SB1) 147 #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop 148 #elif defined(CPU_MIPS24K) || defined(CPU_MIPS34K) || \ 149 defined(CPU_MIPS74K) || defined(CPU_MIPS1004K) || \ 150 defined(CPU_MIPS1074K) || defined(CPU_INTERAPTIV) || \ 151 defined(CPU_PROAPTIV) 152 /* 153 * According to MIPS32tm Architecture for Programmers, Vol.II, rev. 2.00: 154 * "As EHB becomes standard in MIPS implementations, the previous SSNOPs can be 155 * removed, leaving only the EHB". 156 * Also, all MIPS32 Release 2 implementations have the EHB instruction, which 157 * resolves all execution hazards. The same goes for MIPS32 Release 3. 158 */ 159 #define COP0_SYNC .word 0xc0 /* ehb */ 160 #else 161 /* 162 * Pick a reasonable default based on the "typical" spacing described in the 163 * "CP0 Hazards" chapter of MIPS Architecture Book Vol III. 164 */ 165 #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; .word 0xc0; 166 #endif 167 #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; 168 169 /* 170 * The bits in the cause register. 171 * 172 * Bits common to r3000 and r4000: 173 * 174 * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 175 * MIPS_CR_COP_ERR Coprocessor error. 176 * MIPS_CR_IP Interrupt pending bits defined below. 177 * (same meaning as in CAUSE register). 178 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 179 * 180 * Differences: 181 * r3k has 4 bits of execption type, r4k has 5 bits. 182 */ 183 #define MIPS_CR_BR_DELAY 0x80000000 184 #define MIPS_CR_COP_ERR 0x30000000 185 #define MIPS_CR_EXC_CODE 0x0000007C /* five bits */ 186 #define MIPS_CR_IP 0x0000FF00 187 #define MIPS_CR_EXC_CODE_SHIFT 2 188 #define MIPS_CR_COP_ERR_SHIFT 28 189 190 /* 191 * The bits in the status register. All bits are active when set to 1. 192 * 193 * R3000 status register fields: 194 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors. 195 * MIPS_SR_TS TLB shutdown. 196 * 197 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 198 * 199 * Differences: 200 * r3k has cache control is via frobbing SR register bits, whereas the 201 * r4k cache control is via explicit instructions. 202 * r3k has a 3-entry stack of kernel/user bits, whereas the 203 * r4k has kernel/supervisor/user. 204 */ 205 #define MIPS_SR_COP_USABILITY 0xf0000000 206 #define MIPS_SR_COP_0_BIT 0x10000000 207 #define MIPS_SR_COP_1_BIT 0x20000000 208 #define MIPS_SR_COP_2_BIT 0x40000000 209 210 /* r4k and r3k differences, see below */ 211 212 #define MIPS_SR_MX 0x01000000 /* MIPS64 */ 213 #define MIPS_SR_PX 0x00800000 /* MIPS64 */ 214 #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */ 215 #define MIPS_SR_TS 0x00200000 216 #define MIPS_SR_DE 0x00010000 217 218 #define MIPS_SR_INT_IE 0x00000001 219 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 220 #define MIPS_SR_INT_MASK 0x0000ff00 221 222 /* 223 * R4000 status register bit definitions, 224 * where different from r2000/r3000. 225 */ 226 #define MIPS_SR_XX 0x80000000 227 #define MIPS_SR_RP 0x08000000 228 #define MIPS_SR_FR 0x04000000 229 #define MIPS_SR_RE 0x02000000 230 231 #define MIPS_SR_DIAG_DL 0x01000000 /* QED 52xx */ 232 #define MIPS_SR_DIAG_IL 0x00800000 /* QED 52xx */ 233 #define MIPS_SR_SR 0x00100000 234 #define MIPS_SR_NMI 0x00080000 /* MIPS32/64 */ 235 #define MIPS_SR_DIAG_CH 0x00040000 236 #define MIPS_SR_DIAG_CE 0x00020000 237 #define MIPS_SR_DIAG_PE 0x00010000 238 #define MIPS_SR_EIE 0x00010000 /* TX79/R5900 */ 239 #define MIPS_SR_KX 0x00000080 240 #define MIPS_SR_SX 0x00000040 241 #define MIPS_SR_UX 0x00000020 242 #define MIPS_SR_KSU_MASK 0x00000018 243 #define MIPS_SR_KSU_USER 0x00000010 244 #define MIPS_SR_KSU_SUPER 0x00000008 245 #define MIPS_SR_KSU_KERNEL 0x00000000 246 #define MIPS_SR_ERL 0x00000004 247 #define MIPS_SR_EXL 0x00000002 248 249 /* 250 * The interrupt masks. 251 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 252 */ 253 #define MIPS_INT_MASK 0xff00 254 #define MIPS_INT_MASK_5 0x8000 255 #define MIPS_INT_MASK_4 0x4000 256 #define MIPS_INT_MASK_3 0x2000 257 #define MIPS_INT_MASK_2 0x1000 258 #define MIPS_INT_MASK_1 0x0800 259 #define MIPS_INT_MASK_0 0x0400 260 #define MIPS_HARD_INT_MASK 0xfc00 261 #define MIPS_SOFT_INT_MASK_1 0x0200 262 #define MIPS_SOFT_INT_MASK_0 0x0100 263 264 /* 265 * The bits in the MIPS3 config register. 266 * 267 * bit 0..5: R/W, Bit 6..31: R/O 268 */ 269 270 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 271 #define MIPS_CONFIG_K0_MASK 0x00000007 272 273 /* 274 * R/W Update on Store Conditional 275 * 0: Store Conditional uses coherency algorithm specified by TLB 276 * 1: Store Conditional uses cacheable coherent update on write 277 */ 278 #define MIPS_CONFIG_CU 0x00000008 279 280 #define MIPS_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 281 #define MIPS_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 282 #define MIPS_CONFIG_CACHE_L1_LSIZE(config, bit) \ 283 (((config) & (bit)) ? 32 : 16) 284 285 #define MIPS_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 286 #define MIPS_CONFIG_DC_SHIFT 6 287 #define MIPS_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 288 #define MIPS_CONFIG_IC_SHIFT 9 289 #define MIPS_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ 290 291 /* Cache size mode indication: available only on Vr41xx CPUs */ 292 #define MIPS_CONFIG_CS 0x00001000 293 #define MIPS_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ 294 #define MIPS_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 295 ((base) << (((config) & (mask)) >> (shift))) 296 297 /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ 298 #define MIPS_CONFIG_SE 0x00001000 299 300 /* Block ordering: 0: sequential, 1: sub-block */ 301 #define MIPS_CONFIG_EB 0x00002000 302 303 /* ECC mode - 0: ECC mode, 1: parity mode */ 304 #define MIPS_CONFIG_EM 0x00004000 305 306 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 307 #define MIPS_CONFIG_BE 0x00008000 308 309 /* Dirty Shared coherency state - 0: enabled, 1: disabled */ 310 #define MIPS_CONFIG_SM 0x00010000 311 312 /* Secondary Cache - 0: present, 1: not present */ 313 #define MIPS_CONFIG_SC 0x00020000 314 315 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 316 #define MIPS_CONFIG_EW_MASK 0x000c0000 317 #define MIPS_CONFIG_EW_SHIFT 18 318 319 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 320 #define MIPS_CONFIG_SW 0x00100000 321 322 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 323 #define MIPS_CONFIG_SS 0x00200000 324 325 /* Secondary Cache line size */ 326 #define MIPS_CONFIG_SB_MASK 0x00c00000 327 #define MIPS_CONFIG_SB_SHIFT 22 328 #define MIPS_CONFIG_CACHE_L2_LSIZE(config) \ 329 (0x10 << (((config) & MIPS_CONFIG_SB_MASK) >> MIPS_CONFIG_SB_SHIFT)) 330 331 /* Write back data rate */ 332 #define MIPS_CONFIG_EP_MASK 0x0f000000 333 #define MIPS_CONFIG_EP_SHIFT 24 334 335 /* System clock ratio - this value is CPU dependent */ 336 #define MIPS_CONFIG_EC_MASK 0x70000000 337 #define MIPS_CONFIG_EC_SHIFT 28 338 339 /* Master-Checker Mode - 1: enabled */ 340 #define MIPS_CONFIG_CM 0x80000000 341 342 /* 343 * The bits in the MIPS4 config register. 344 */ 345 346 /* 347 * Location of exception vectors. 348 * 349 * Common vectors: reset and UTLB miss. 350 */ 351 #define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000) 352 #define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000) 353 354 /* 355 * MIPS-III exception vectors 356 */ 357 #define MIPS_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080) 358 #define MIPS_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100) 359 #define MIPS_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180) 360 361 /* 362 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. 363 */ 364 #define MIPS_INTR_EXC_VEC 0x80000200 365 366 /* 367 * Coprocessor 0 registers: 368 * 369 * v--- width for mips I,III,32,64 370 * (3=32bit, 6=64bit, i=impl dep) 371 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 372 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. 373 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. 374 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. 375 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. 376 * 4/2 MIPS_COP_0_USERLOCAL ..36 UserLocal. 377 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. 378 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. 379 * 7 MIPS_COP_0_HWRENA ..33 rdHWR Enable. 380 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. 381 * 9 MIPS_COP_0_COUNT .333 Count register. 382 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. 383 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). 384 * 12 MIPS_COP_0_STATUS 3333 Status register. 385 * 12/1 MIPS_COP_0_INTCTL ..33 Interrupt setup (MIPS32/64 r2). 386 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. 387 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. 388 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. 389 * 16 MIPS_COP_0_CONFIG 3333 Configuration register. 390 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. 391 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. 392 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. 393 * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 4. 394 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. 395 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. 396 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. 397 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. 398 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. 399 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. 400 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. 401 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. 402 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. 403 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). 404 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). 405 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). 406 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). 407 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). 408 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). 409 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). 410 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). 411 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. 412 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. 413 */ 414 415 /* Deal with inclusion from an assembly file. */ 416 #if defined(_LOCORE) || defined(LOCORE) 417 #define _(n) $n 418 #else 419 #define _(n) n 420 #endif 421 422 #define MIPS_COP_0_TLB_INDEX _(0) 423 #define MIPS_COP_0_TLB_RANDOM _(1) 424 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 425 426 #define MIPS_COP_0_TLB_CONTEXT _(4) 427 /* $5 and $6 new with MIPS-III */ 428 #define MIPS_COP_0_BAD_VADDR _(8) 429 #define MIPS_COP_0_TLB_HI _(10) 430 #define MIPS_COP_0_STATUS _(12) 431 #define MIPS_COP_0_CAUSE _(13) 432 #define MIPS_COP_0_EXC_PC _(14) 433 #define MIPS_COP_0_PRID _(15) 434 435 /* MIPS-III */ 436 #define MIPS_COP_0_TLB_LO0 _(2) 437 #define MIPS_COP_0_TLB_LO1 _(3) 438 439 #define MIPS_COP_0_TLB_PG_MASK _(5) 440 #define MIPS_COP_0_TLB_WIRED _(6) 441 442 #define MIPS_COP_0_COUNT _(9) 443 #define MIPS_COP_0_COMPARE _(11) 444 #ifdef CPU_XBURST 445 #define MIPS_COP_0_XBURST_C12 _(12) 446 #endif 447 #define MIPS_COP_0_CONFIG _(16) 448 #define MIPS_COP_0_LLADDR _(17) 449 #define MIPS_COP_0_WATCH_LO _(18) 450 #define MIPS_COP_0_WATCH_HI _(19) 451 #define MIPS_COP_0_TLB_XCONTEXT _(20) 452 #ifdef CPU_XBURST 453 #define MIPS_COP_0_XBURST_MBOX _(20) 454 #endif 455 456 #define MIPS_COP_0_ECC _(26) 457 #define MIPS_COP_0_CACHE_ERR _(27) 458 #define MIPS_COP_0_TAG_LO _(28) 459 #define MIPS_COP_0_TAG_HI _(29) 460 #define MIPS_COP_0_ERROR_PC _(30) 461 462 /* MIPS32/64 */ 463 #define MIPS_COP_0_USERLOCAL _(4) /* sel 2 is userlevel register */ 464 #define MIPS_COP_0_HWRENA _(7) 465 #define MIPS_COP_0_INTCTL _(12) 466 #define MIPS_COP_0_DEBUG _(23) 467 #define MIPS_COP_0_DEPC _(24) 468 #define MIPS_COP_0_PERFCNT _(25) 469 #define MIPS_COP_0_DATA_LO _(28) 470 #define MIPS_COP_0_DATA_HI _(29) 471 #define MIPS_COP_0_DESAVE _(31) 472 473 /* MIPS32 Config register definitions */ 474 #define MIPS_MMU_NONE 0x00 /* No MMU present */ 475 #define MIPS_MMU_TLB 0x01 /* Standard TLB */ 476 #define MIPS_MMU_BAT 0x02 /* Standard BAT */ 477 #define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */ 478 479 /* 480 * IntCtl Register Fields 481 */ 482 #define MIPS_INTCTL_IPTI_MASK 0xE0000000 /* bits 31..29 timer intr # */ 483 #define MIPS_INTCTL_IPTI_SHIFT 29 484 #define MIPS_INTCTL_IPPCI_MASK 0x1C000000 /* bits 26..29 perf counter intr # */ 485 #define MIPS_INTCTL_IPPCI_SHIFT 26 486 #define MIPS_INTCTL_VS_MASK 0x000001F0 /* bits 5..9 vector spacing */ 487 #define MIPS_INTCTL_VS_SHIFT 4 488 489 /* 490 * Config Register Fields 491 * (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9.39) 492 */ 493 #define MIPS_CONFIG0_M 0x80000000 /* Flag: Config1 is present. */ 494 #define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */ 495 #define MIPS_CONFIG0_MT_SHIFT 7 496 #define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */ 497 #define MIPS_CONFIG0_VI 0x00000008 /* inst cache is virtual */ 498 499 /* 500 * Config1 Register Fields 501 * (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9-1) 502 */ 503 #define MIPS_CONFIG1_M 0x80000000 /* Flag: Config2 is present. */ 504 #define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */ 505 #define MIPS_CONFIG1_TLBSZ_SHIFT 25 506 507 #define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */ 508 #define MIPS_CONFIG1_IS_SHIFT 22 509 #define MIPS_CONFIG1_IL_MASK 0x00380000 /* bits 21..19 icache line size */ 510 #define MIPS_CONFIG1_IL_SHIFT 19 511 #define MIPS_CONFIG1_IA_MASK 0x00070000 /* bits 18..16 icache associativity */ 512 #define MIPS_CONFIG1_IA_SHIFT 16 513 #define MIPS_CONFIG1_DS_MASK 0x0000E000 /* bits 15..13 dcache sets per way */ 514 #define MIPS_CONFIG1_DS_SHIFT 13 515 #define MIPS_CONFIG1_DL_MASK 0x00001C00 /* bits 12..10 dcache line size */ 516 #define MIPS_CONFIG1_DL_SHIFT 10 517 #define MIPS_CONFIG1_DA_MASK 0x00000380 /* bits 9.. 7 dcache associativity */ 518 #define MIPS_CONFIG1_DA_SHIFT 7 519 #define MIPS_CONFIG1_LOWBITS 0x0000007F 520 #define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */ 521 #define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */ 522 #define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */ 523 #define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */ 524 #define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */ 525 #define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */ 526 #define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */ 527 528 #define MIPS_CONFIG2_SA_SHIFT 0 /* Secondary cache associativity */ 529 #define MIPS_CONFIG2_SA_MASK 0xf 530 #define MIPS_CONFIG2_SL_SHIFT 4 /* Secondary cache line size */ 531 #define MIPS_CONFIG2_SL_MASK 0xf 532 #define MIPS_CONFIG2_SS_SHIFT 8 /* Secondary cache sets per way */ 533 #define MIPS_CONFIG2_SS_MASK 0xf 534 535 #define MIPS_CONFIG3_CMGCR_MASK (1 << 29) /* Coherence manager present */ 536 537 /* 538 * Config2 Register Fields 539 * (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9.40) 540 */ 541 #define MIPS_CONFIG2_M 0x80000000 /* Flag: Config3 is present. */ 542 543 /* 544 * Config3 Register Fields 545 * (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9.41) 546 */ 547 #define MIPS_CONFIG3_M 0x80000000 /* Flag: Config4 is present */ 548 #define MIPS_CONFIG3_ULR 0x00002000 /* UserLocal reg implemented */ 549 550 #define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */ 551 #define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */ 552 #define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */ 553 554 /* 555 * Values for the code field in a break instruction. 556 */ 557 #define MIPS_BREAK_INSTR 0x0000000d 558 #define MIPS_BREAK_VAL_MASK 0x03ff0000 559 #define MIPS_BREAK_VAL_SHIFT 16 560 #define MIPS_BREAK_KDB_VAL 512 561 #define MIPS_BREAK_SSTEP_VAL 513 562 #define MIPS_BREAK_BRKPT_VAL 514 563 #define MIPS_BREAK_SOVER_VAL 515 564 #define MIPS_BREAK_DDB_VAL 516 565 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 566 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 567 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 568 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 569 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 570 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 571 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 572 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 573 #define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \ 574 (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT)) 575 576 /* 577 * Mininum and maximum cache sizes. 578 */ 579 #define MIPS_MIN_CACHE_SIZE (16 * 1024) 580 #define MIPS_MAX_CACHE_SIZE (256 * 1024) 581 #define MIPS_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ 582 583 /* 584 * The floating point version and status registers. 585 */ 586 #define MIPS_FPU_ID $0 587 #define MIPS_FPU_CSR $31 588 589 /* 590 * The floating point coprocessor status register bits. 591 */ 592 #define MIPS_FPU_ROUNDING_BITS 0x00000003 593 #define MIPS_FPU_ROUND_RN 0x00000000 594 #define MIPS_FPU_ROUND_RZ 0x00000001 595 #define MIPS_FPU_ROUND_RP 0x00000002 596 #define MIPS_FPU_ROUND_RM 0x00000003 597 #define MIPS_FPU_STICKY_BITS 0x0000007c 598 #define MIPS_FPU_STICKY_INEXACT 0x00000004 599 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 600 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010 601 #define MIPS_FPU_STICKY_DIV0 0x00000020 602 #define MIPS_FPU_STICKY_INVALID 0x00000040 603 #define MIPS_FPU_ENABLE_BITS 0x00000f80 604 #define MIPS_FPU_ENABLE_INEXACT 0x00000080 605 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 606 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 607 #define MIPS_FPU_ENABLE_DIV0 0x00000400 608 #define MIPS_FPU_ENABLE_INVALID 0x00000800 609 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000 610 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 611 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 612 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 613 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000 614 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000 615 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 616 #define MIPS_FPU_COND_BIT 0x00800000 617 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 618 #define MIPS_FPC_MBZ_BITS 0xfe7c0000 619 620 /* 621 * Constants to determine if have a floating point instruction. 622 */ 623 #define MIPS_OPCODE_SHIFT 26 624 #define MIPS_OPCODE_C1 0x11 625 626 /* Coherence manager constants */ 627 #define MIPS_CMGCRB_BASE 11 628 #define MIPS_CMGCRF_BASE (~((1 << MIPS_CMGCRB_BASE) - 1)) 629 630 /* 631 * Bits defined for for the HWREna (CP0 register 7, select 0). 632 */ 633 #define MIPS_HWRENA_CPUNUM (1<<0) /* CPU number program is running on */ 634 #define MIPS_HWRENA_SYNCI_STEP (1<<1) /* Address step sized used with SYNCI */ 635 #define MIPS_HWRENA_CC (1<<2) /* Hi Res cycle counter */ 636 #define MIPS_HWRENA_CCRES (1<<3) /* Cycle counter resolution */ 637 #define MIPS_HWRENA_UL (1<<29) /* UserLocal Register */ 638 #define MIPS_HWRENA_IMPL30 (1<<30) /* Implementation-dependent 30 */ 639 #define MIPS_HWRENA_IMPL31 (1<<31) /* Implementation-dependent 31 */ 640 641 #endif /* _MIPS_CPUREGS_H_ */ 642