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Searched refs:MI1 (Results 1 – 25 of 27) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64MachineScheduler.cpp36 static bool mayOverlapWrite(const MachineInstr &MI0, const MachineInstr &MI1, in mayOverlapWrite() argument
39 const MachineOperand &Base1 = AArch64InstrInfo::getLdStBaseOp(MI1); in mayOverlapWrite()
46 int StoreSize1 = AArch64InstrInfo::getMemScale(MI1); in mayOverlapWrite()
50 Off1 = AArch64InstrInfo::hasUnscaledLdStOffset(MI1.getOpcode()) in mayOverlapWrite()
51 ? AArch64InstrInfo::getLdStOffsetOp(MI1).getImm() in mayOverlapWrite()
52 : AArch64InstrInfo::getLdStOffsetOp(MI1).getImm() * StoreSize1; in mayOverlapWrite()
54 const MachineInstr &MI = (Off0 < Off1) ? MI0 : MI1; in mayOverlapWrite()
HDAArch64CollectLOH.cpp281 const MachineInstr *MI1; ///< Second instruction involved in the LOH member
308 Info.MI1 = nullptr; in handleUse()
350 OpInfo.MI1 = &MI; in handleMiddleInst()
352 } else if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) { in handleMiddleInst()
355 OpInfo.MI1 = &MI; in handleMiddleInst()
364 if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) { in handleMiddleInst()
367 OpInfo.MI1 = &MI; in handleMiddleInst()
372 OpInfo.MI1 = &MI; in handleMiddleInst()
435 MachineInstr *AddMI = const_cast<MachineInstr *>(Info.MI1); in handleADRP()
443 << '\t' << MI << '\t' << *Info.MI1 << '\t' in handleADRP()
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMicroMipsSizeReduction.cpp398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr() argument
401 if (!GetImm(MI1, 2, Offset1)) in ConsecutiveInstr()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr()
464 MachineInstr *MI1 = Arguments->MI; in ReduceXWtoXWP() local
468 bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) || in ReduceXWtoXWP()
469 (MI1->getOpcode() == Mips::LW_MM) || in ReduceXWtoXWP()
470 (MI1->getOpcode() == Mips::LW16_MM); in ReduceXWtoXWP()
472 if (!CheckXWPInstr(MI1, ReduceToLwp, Entry)) in ReduceXWtoXWP()
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP()
484 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2); in ReduceXWtoXWP()
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDSIFixSGPRCopies.cpp473 MachineInstr *MI1 = *I1; in hoistAndMergeSGPRInits() local
511 if (MDT.dominates(MI1, MI2)) { in hoistAndMergeSGPRInits()
512 if (!interferes(MI2, MI1)) { in hoistAndMergeSGPRInits()
521 } else if (MDT.dominates(MI2, MI1)) { in hoistAndMergeSGPRInits()
522 if (!interferes(MI1, MI2)) { in hoistAndMergeSGPRInits()
525 << printMBBReference(*MI1->getParent()) << " " << *MI1); in hoistAndMergeSGPRInits()
526 MergedInstrs.insert(MI1); in hoistAndMergeSGPRInits()
532 auto *MBB = MDT.findNearestCommonDominator(MI1->getParent(), in hoistAndMergeSGPRInits()
540 if (!interferes(MI1, I) && !interferes(MI2, I)) { in hoistAndMergeSGPRInits()
543 << printMBBReference(*MI1->getParent()) << " " << *MI1 in hoistAndMergeSGPRInits()
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HDGCNHazardRecognizer.cpp2225 const MachineInstr *MI1; in checkMAIHazards90A() local
2227 auto IsOverlappedMFMAFn = [Reg, &FullReg, &MI1, in checkMAIHazards90A()
2233 MI1 = &MI; in checkMAIHazards90A()
2247 unsigned Opc1 = MI1->getOpcode(); in checkMAIHazards90A()
2259 TSchedModel.computeInstrLatency(MI1) == 2) in checkMAIHazards90A()
2276 int NumPasses = TSchedModel.computeInstrLatency(MI1); in checkMAIHazards90A()
2278 if (isXDL(ST, *MI) && !isXDL(ST, *MI1)) in checkMAIHazards90A()
2282 isXDL(ST, *MI1) in checkMAIHazards90A()
2326 int NumPasses = TSchedModel.computeInstrLatency(MI1); in checkMAIHazards90A()
2330 isXDL(ST, *MI1) in checkMAIHazards90A()
HDSIInstrInfo.cpp518 static bool memOpsHaveSameBasePtr(const MachineInstr &MI1, in memOpsHaveSameBasePtr() argument
528 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand()) in memOpsHaveSameBasePtr()
531 auto MO1 = *MI1.memoperands_begin(); in memOpsHaveSameBasePtr()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDDFAPacketizer.cpp272 bool VLIWPacketizerList::alias(const MachineInstr &MI1, in alias() argument
275 if (MI1.memoperands_empty() || MI2.memoperands_empty()) in alias()
278 for (const MachineMemOperand *Op1 : MI1.memoperands()) in alias()
HDTargetInstrInfo.cpp429 const MachineInstr &MI1, in produceSameValue() argument
431 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
841 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
844 MI1 = MRI.getUniqueVRegDef(Op1.getReg()); in hasReassociableOperands()
849 return MI1 && MI2 && (MI1->getParent() == MBB || MI2->getParent() == MBB); in hasReassociableOperands()
861 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
867 Commuted = !areOpcodesEqualOrInverse(Opcode, MI1->getOpcode()) && in hasReassociableSibling()
870 std::swap(MI1, MI2); in hasReassociableSibling()
880 return areOpcodesEqualOrInverse(Opcode, MI1->getOpcode()) && in hasReassociableSibling()
881 (isAssociativeAndCommutative(*MI1) || in hasReassociableSibling()
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonSubtarget.cpp264 MachineInstr &MI1 = *SU.getInstr(); in apply() local
266 bool IsStoreMI1 = MI1.mayStore(); in apply()
267 bool IsLoadMI1 = MI1.mayLoad(); in apply()
268 if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1)) in apply()
HDHexagonVLIWPacketizer.cpp967 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements() argument
971 if (getPredicateSense(MI1, HII) == PK_Unknown || in arePredicatesComplements()
976 SUnit *SU = MIToSUnit[&MI1]; in arePredicatesComplements()
1024 unsigned PReg1 = getPredicatedRegister(MI1, HII); in arePredicatesComplements()
1029 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
1030 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2); in arePredicatesComplements()
HDHexagonVLIWPacketizer.h144 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
HDHexagonInstrInfo.h407 bool isToBeScheduledASAP(const MachineInstr &MI1,
419 bool addLatencyToSchedule(const MachineInstr &MI1,
HDHexagonInstrInfo.cpp2687 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1, in isToBeScheduledASAP() argument
2689 if (mayBeCurLoad(MI1)) { in isToBeScheduledASAP()
2691 Register DstReg = MI1.getOperand(0).getReg(); in isToBeScheduledASAP()
2699 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() && in isToBeScheduledASAP()
2700 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
3063 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1, in addLatencyToSchedule() argument
3065 if (isHVXVec(MI1) && isHVXVec(MI2)) in addLatencyToSchedule()
3066 if (!isVecUsableNextPacket(MI1, MI2)) in addLatencyToSchedule()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86OptimizeLEAs.cpp276 int64_t getAddrDispShift(const MachineInstr &MI1, unsigned N1,
397 int64_t X86OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, in getAddrDispShift() argument
401 const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp); in getAddrDispShift()
HDX86ISelLowering.h1768 MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVInstrInfo.cpp1822 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableVectorSibling() local
1827 Commuted = !areRVVInstsReassociable(Inst, *MI1) && in hasReassociableVectorSibling()
1830 std::swap(MI1, MI2); in hasReassociableVectorSibling()
1832 return areRVVInstsReassociable(Inst, *MI1) && in hasReassociableVectorSibling()
1833 (isVectorAssociativeAndCommutative(*MI1) || in hasReassociableVectorSibling()
1834 isVectorAssociativeAndCommutative(*MI1, /* Invert */ true)) && in hasReassociableVectorSibling()
1835 hasReassociableOperands(*MI1, MBB) && in hasReassociableVectorSibling()
1836 MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg()); in hasReassociableVectorSibling()
1851 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
1854 MI1 = MRI.getUniqueVRegDef(Op1.getReg()); in hasReassociableOperands()
[all …]
HDRISCVInstrInfo.h312 bool areRVVInstsReassociable(const MachineInstr &MI1,
339 bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDMLxExpansionPass.cpp316 MachineInstr &MI1 = *MII; in ExpandFPMLxInstruction()
317 dbgs() << " " << MI1; in ExpandFPMLxInstruction()
HDARMBaseInstrInfo.cpp1862 const MachineInstr &MI1, in produceSameValue() argument
1871 if (MI1.getOpcode() != Opcode) in produceSameValue()
1873 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1877 const MachineOperand &MO1 = MI1.getOperand(1); in produceSameValue()
1907 if (MI1.getOpcode() != Opcode) in produceSameValue()
1909 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1913 Register Addr1 = MI1.getOperand(1).getReg(); in produceSameValue()
1930 const MachineOperand &MO1 = MI1.getOperand(i); in produceSameValue()
1937 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
HDARMBaseInstrInfo.h244 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
HDLoadStoreOpt.h63 bool aliasIsKnownForLoadStore(const MachineInstr &MI1, const MachineInstr &MI2,
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDDFAPacketizer.h215 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
HDTargetInstrInfo.h596 const MachineInstr &MI1,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
HDLoadStoreOpt.cpp104 bool GISelAddressing::aliasIsKnownForLoadStore(const MachineInstr &MI1, in aliasIsKnownForLoadStore() argument
108 auto *LdSt1 = dyn_cast<GLoadStore>(&MI1); in aliasIsKnownForLoadStore()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/
HDAVRExpandPseudoInsts.cpp1646 auto MI1 = in expandLSLW4Rd() local
1652 MI1->getOperand(3).setIsDead(); in expandLSLW4Rd()
1732 auto MI1 = in expandLSLW12Rd() local
1738 MI1->getOperand(3).setIsDead(); in expandLSLW12Rd()
1844 auto MI1 = in expandLSRW4Rd() local
1850 MI1->getOperand(3).setIsDead(); in expandLSRW4Rd()

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