1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _VMM_DEV_H_ 30 #define _VMM_DEV_H_ 31 32 struct vm_snapshot_meta; 33 34 #ifdef _KERNEL 35 void vmmdev_init(void); 36 int vmmdev_cleanup(void); 37 #endif 38 39 struct vm_memmap { 40 vm_paddr_t gpa; 41 int segid; /* memory segment */ 42 vm_ooffset_t segoff; /* offset into memory segment */ 43 size_t len; /* mmap length */ 44 int prot; /* RWX */ 45 int flags; 46 }; 47 #define VM_MEMMAP_F_WIRED 0x01 48 #define VM_MEMMAP_F_IOMMU 0x02 49 50 struct vm_munmap { 51 vm_paddr_t gpa; 52 size_t len; 53 }; 54 55 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL) 56 struct vm_memseg { 57 int segid; 58 size_t len; 59 char name[VM_MAX_SUFFIXLEN + 1]; 60 }; 61 62 struct vm_memseg_fbsd12 { 63 int segid; 64 size_t len; 65 char name[64]; 66 }; 67 _Static_assert(sizeof(struct vm_memseg_fbsd12) == 80, "COMPAT_FREEBSD12 ABI"); 68 69 struct vm_register { 70 int cpuid; 71 int regnum; /* enum vm_reg_name */ 72 uint64_t regval; 73 }; 74 75 struct vm_seg_desc { /* data or code segment */ 76 int cpuid; 77 int regnum; /* enum vm_reg_name */ 78 struct seg_desc desc; 79 }; 80 81 struct vm_register_set { 82 int cpuid; 83 unsigned int count; 84 const int *regnums; /* enum vm_reg_name */ 85 uint64_t *regvals; 86 }; 87 88 struct vm_run { 89 int cpuid; 90 struct vm_exit vm_exit; 91 }; 92 93 struct vm_exception { 94 int cpuid; 95 int vector; 96 uint32_t error_code; 97 int error_code_valid; 98 int restart_instruction; 99 }; 100 101 struct vm_lapic_msi { 102 uint64_t msg; 103 uint64_t addr; 104 }; 105 106 struct vm_lapic_irq { 107 int cpuid; 108 int vector; 109 }; 110 111 struct vm_ioapic_irq { 112 int irq; 113 }; 114 115 struct vm_isa_irq { 116 int atpic_irq; 117 int ioapic_irq; 118 }; 119 120 struct vm_isa_irq_trigger { 121 int atpic_irq; 122 enum vm_intr_trigger trigger; 123 }; 124 125 struct vm_capability { 126 int cpuid; 127 enum vm_cap_type captype; 128 int capval; 129 int allcpus; 130 }; 131 132 struct vm_pptdev { 133 int bus; 134 int slot; 135 int func; 136 }; 137 138 struct vm_pptdev_mmio { 139 int bus; 140 int slot; 141 int func; 142 vm_paddr_t gpa; 143 vm_paddr_t hpa; 144 size_t len; 145 }; 146 147 struct vm_pptdev_msi { 148 int vcpu; /* unused */ 149 int bus; 150 int slot; 151 int func; 152 int numvec; /* 0 means disabled */ 153 uint64_t msg; 154 uint64_t addr; 155 }; 156 157 struct vm_pptdev_msix { 158 int vcpu; /* unused */ 159 int bus; 160 int slot; 161 int func; 162 int idx; 163 uint64_t msg; 164 uint32_t vector_control; 165 uint64_t addr; 166 }; 167 168 struct vm_nmi { 169 int cpuid; 170 }; 171 172 #define MAX_VM_STATS 64 173 struct vm_stats { 174 int cpuid; /* in */ 175 int index; /* in */ 176 int num_entries; /* out */ 177 struct timeval tv; 178 uint64_t statbuf[MAX_VM_STATS]; 179 }; 180 181 struct vm_stat_desc { 182 int index; /* in */ 183 char desc[128]; /* out */ 184 }; 185 186 struct vm_x2apic { 187 int cpuid; 188 enum x2apic_state state; 189 }; 190 191 struct vm_gpa_pte { 192 uint64_t gpa; /* in */ 193 uint64_t pte[4]; /* out */ 194 int ptenum; 195 }; 196 197 struct vm_hpet_cap { 198 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 199 }; 200 201 struct vm_suspend { 202 enum vm_suspend_how how; 203 }; 204 205 struct vm_gla2gpa { 206 int vcpuid; /* inputs */ 207 int prot; /* PROT_READ or PROT_WRITE */ 208 uint64_t gla; 209 struct vm_guest_paging paging; 210 int fault; /* outputs */ 211 uint64_t gpa; 212 }; 213 214 struct vm_activate_cpu { 215 int vcpuid; 216 }; 217 218 struct vm_cpuset { 219 int which; 220 int cpusetsize; 221 cpuset_t *cpus; 222 }; 223 #define VM_ACTIVE_CPUS 0 224 #define VM_SUSPENDED_CPUS 1 225 #define VM_DEBUG_CPUS 2 226 227 struct vm_intinfo { 228 int vcpuid; 229 uint64_t info1; 230 uint64_t info2; 231 }; 232 233 struct vm_rtc_time { 234 time_t secs; 235 }; 236 237 struct vm_rtc_data { 238 int offset; 239 uint8_t value; 240 }; 241 242 struct vm_cpu_topology { 243 uint16_t sockets; 244 uint16_t cores; 245 uint16_t threads; 246 uint16_t maxcpus; 247 }; 248 249 struct vm_readwrite_kernemu_device { 250 int vcpuid; 251 unsigned access_width : 3; 252 unsigned _unused : 29; 253 uint64_t gpa; 254 uint64_t value; 255 }; 256 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI"); 257 258 enum { 259 /* general routines */ 260 IOCNUM_ABIVERS = 0, 261 IOCNUM_RUN = 1, 262 IOCNUM_SET_CAPABILITY = 2, 263 IOCNUM_GET_CAPABILITY = 3, 264 IOCNUM_SUSPEND = 4, 265 IOCNUM_REINIT = 5, 266 267 /* memory apis */ 268 IOCNUM_MAP_MEMORY = 10, /* deprecated */ 269 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */ 270 IOCNUM_GET_GPA_PMAP = 12, 271 IOCNUM_GLA2GPA = 13, 272 IOCNUM_ALLOC_MEMSEG = 14, 273 IOCNUM_GET_MEMSEG = 15, 274 IOCNUM_MMAP_MEMSEG = 16, 275 IOCNUM_MMAP_GETNEXT = 17, 276 IOCNUM_GLA2GPA_NOFAULT = 18, 277 IOCNUM_MUNMAP_MEMSEG = 19, 278 279 /* register/state accessors */ 280 IOCNUM_SET_REGISTER = 20, 281 IOCNUM_GET_REGISTER = 21, 282 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 283 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 284 IOCNUM_SET_REGISTER_SET = 24, 285 IOCNUM_GET_REGISTER_SET = 25, 286 IOCNUM_GET_KERNEMU_DEV = 26, 287 IOCNUM_SET_KERNEMU_DEV = 27, 288 289 /* interrupt injection */ 290 IOCNUM_GET_INTINFO = 28, 291 IOCNUM_SET_INTINFO = 29, 292 IOCNUM_INJECT_EXCEPTION = 30, 293 IOCNUM_LAPIC_IRQ = 31, 294 IOCNUM_INJECT_NMI = 32, 295 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 296 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 297 IOCNUM_IOAPIC_PULSE_IRQ = 35, 298 IOCNUM_LAPIC_MSI = 36, 299 IOCNUM_LAPIC_LOCAL_IRQ = 37, 300 IOCNUM_IOAPIC_PINCOUNT = 38, 301 IOCNUM_RESTART_INSTRUCTION = 39, 302 303 /* PCI pass-thru */ 304 IOCNUM_BIND_PPTDEV = 40, 305 IOCNUM_UNBIND_PPTDEV = 41, 306 IOCNUM_MAP_PPTDEV_MMIO = 42, 307 IOCNUM_PPTDEV_MSI = 43, 308 IOCNUM_PPTDEV_MSIX = 44, 309 IOCNUM_PPTDEV_DISABLE_MSIX = 45, 310 IOCNUM_UNMAP_PPTDEV_MMIO = 46, 311 312 /* statistics */ 313 IOCNUM_VM_STATS = 50, 314 IOCNUM_VM_STAT_DESC = 51, 315 316 /* kernel device state */ 317 IOCNUM_SET_X2APIC_STATE = 60, 318 IOCNUM_GET_X2APIC_STATE = 61, 319 IOCNUM_GET_HPET_CAPABILITIES = 62, 320 321 /* CPU Topology */ 322 IOCNUM_SET_TOPOLOGY = 63, 323 IOCNUM_GET_TOPOLOGY = 64, 324 325 /* legacy interrupt injection */ 326 IOCNUM_ISA_ASSERT_IRQ = 80, 327 IOCNUM_ISA_DEASSERT_IRQ = 81, 328 IOCNUM_ISA_PULSE_IRQ = 82, 329 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 330 331 /* vm_cpuset */ 332 IOCNUM_ACTIVATE_CPU = 90, 333 IOCNUM_GET_CPUSET = 91, 334 IOCNUM_SUSPEND_CPU = 92, 335 IOCNUM_RESUME_CPU = 93, 336 337 /* RTC */ 338 IOCNUM_RTC_READ = 100, 339 IOCNUM_RTC_WRITE = 101, 340 IOCNUM_RTC_SETTIME = 102, 341 IOCNUM_RTC_GETTIME = 103, 342 343 /* checkpoint */ 344 IOCNUM_SNAPSHOT_REQ = 113, 345 346 IOCNUM_RESTORE_TIME = 115 347 }; 348 349 #define VM_RUN \ 350 _IOWR('v', IOCNUM_RUN, struct vm_run) 351 #define VM_SUSPEND \ 352 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 353 #define VM_REINIT \ 354 _IO('v', IOCNUM_REINIT) 355 #define VM_ALLOC_MEMSEG_FBSD12 \ 356 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg_fbsd12) 357 #define VM_ALLOC_MEMSEG \ 358 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg) 359 #define VM_GET_MEMSEG_FBSD12 \ 360 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg_fbsd12) 361 #define VM_GET_MEMSEG \ 362 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg) 363 #define VM_MMAP_MEMSEG \ 364 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap) 365 #define VM_MMAP_GETNEXT \ 366 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap) 367 #define VM_MUNMAP_MEMSEG \ 368 _IOW('v', IOCNUM_MUNMAP_MEMSEG, struct vm_munmap) 369 #define VM_SET_REGISTER \ 370 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 371 #define VM_GET_REGISTER \ 372 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 373 #define VM_SET_SEGMENT_DESCRIPTOR \ 374 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 375 #define VM_GET_SEGMENT_DESCRIPTOR \ 376 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 377 #define VM_SET_REGISTER_SET \ 378 _IOW('v', IOCNUM_SET_REGISTER_SET, struct vm_register_set) 379 #define VM_GET_REGISTER_SET \ 380 _IOWR('v', IOCNUM_GET_REGISTER_SET, struct vm_register_set) 381 #define VM_SET_KERNEMU_DEV \ 382 _IOW('v', IOCNUM_SET_KERNEMU_DEV, \ 383 struct vm_readwrite_kernemu_device) 384 #define VM_GET_KERNEMU_DEV \ 385 _IOWR('v', IOCNUM_GET_KERNEMU_DEV, \ 386 struct vm_readwrite_kernemu_device) 387 #define VM_INJECT_EXCEPTION \ 388 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 389 #define VM_LAPIC_IRQ \ 390 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 391 #define VM_LAPIC_LOCAL_IRQ \ 392 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 393 #define VM_LAPIC_MSI \ 394 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 395 #define VM_IOAPIC_ASSERT_IRQ \ 396 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 397 #define VM_IOAPIC_DEASSERT_IRQ \ 398 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 399 #define VM_IOAPIC_PULSE_IRQ \ 400 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 401 #define VM_IOAPIC_PINCOUNT \ 402 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 403 #define VM_ISA_ASSERT_IRQ \ 404 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 405 #define VM_ISA_DEASSERT_IRQ \ 406 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 407 #define VM_ISA_PULSE_IRQ \ 408 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 409 #define VM_ISA_SET_IRQ_TRIGGER \ 410 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 411 #define VM_SET_CAPABILITY \ 412 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 413 #define VM_GET_CAPABILITY \ 414 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 415 #define VM_BIND_PPTDEV \ 416 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 417 #define VM_UNBIND_PPTDEV \ 418 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 419 #define VM_MAP_PPTDEV_MMIO \ 420 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 421 #define VM_PPTDEV_MSI \ 422 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 423 #define VM_PPTDEV_MSIX \ 424 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 425 #define VM_PPTDEV_DISABLE_MSIX \ 426 _IOW('v', IOCNUM_PPTDEV_DISABLE_MSIX, struct vm_pptdev) 427 #define VM_UNMAP_PPTDEV_MMIO \ 428 _IOW('v', IOCNUM_UNMAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 429 #define VM_INJECT_NMI \ 430 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 431 #define VM_STATS \ 432 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 433 #define VM_STAT_DESC \ 434 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 435 #define VM_SET_X2APIC_STATE \ 436 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 437 #define VM_GET_X2APIC_STATE \ 438 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 439 #define VM_GET_HPET_CAPABILITIES \ 440 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 441 #define VM_SET_TOPOLOGY \ 442 _IOW('v', IOCNUM_SET_TOPOLOGY, struct vm_cpu_topology) 443 #define VM_GET_TOPOLOGY \ 444 _IOR('v', IOCNUM_GET_TOPOLOGY, struct vm_cpu_topology) 445 #define VM_GET_GPA_PMAP \ 446 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 447 #define VM_GLA2GPA \ 448 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) 449 #define VM_GLA2GPA_NOFAULT \ 450 _IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa) 451 #define VM_ACTIVATE_CPU \ 452 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) 453 #define VM_GET_CPUS \ 454 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) 455 #define VM_SUSPEND_CPU \ 456 _IOW('v', IOCNUM_SUSPEND_CPU, struct vm_activate_cpu) 457 #define VM_RESUME_CPU \ 458 _IOW('v', IOCNUM_RESUME_CPU, struct vm_activate_cpu) 459 #define VM_SET_INTINFO \ 460 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) 461 #define VM_GET_INTINFO \ 462 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) 463 #define VM_RTC_WRITE \ 464 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) 465 #define VM_RTC_READ \ 466 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) 467 #define VM_RTC_SETTIME \ 468 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) 469 #define VM_RTC_GETTIME \ 470 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) 471 #define VM_RESTART_INSTRUCTION \ 472 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) 473 #define VM_SNAPSHOT_REQ \ 474 _IOWR('v', IOCNUM_SNAPSHOT_REQ, struct vm_snapshot_meta) 475 #define VM_RESTORE_TIME \ 476 _IOWR('v', IOCNUM_RESTORE_TIME, int) 477 #endif 478