Searched refs:FRM (Results 1 – 12 of 12) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| HD | RISCVInsertReadWriteCSR.cpp | 86 MI.readsRegister(RISCV::FRM, /*TRI=*/nullptr)) { in INITIALIZE_PASS() 96 assert(!MI.modifiesRegister(RISCV::FRM, /*TRI=*/nullptr) && in INITIALIZE_PASS() 107 MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false, in INITIALIZE_PASS() 164 MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false, in emitWriteRoundingMode()
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| HD | RISCVInstrInfoZvfbf.td | 24 let Uses = [FRM] in 30 RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true in {
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| HD | RISCVInstrInfoV.td | 1336 let Uses = [FRM], mayRaiseFPException = true in { 1344 Uses = [FRM], 1358 } // Constraints = "@earlyclobber $vd", Uses = [FRM], mayRaiseFPException = true 1361 let Uses = [FRM], mayRaiseFPException = true in { 1369 Uses = [FRM], mayRaiseFPException = true in { 1371 } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException =… 1374 let Uses = [FRM], mayRaiseFPException = true in { 1386 let Uses = [FRM], mayRaiseFPException = true in { 1391 } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException =… 1394 let Uses = [FRM], mayRaiseFPException = true in { [all …]
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| HD | RISCVInstrInfo.cpp | 1607 const MachineOperand &FRM = Root.getOperand(FrmOpIdx); in finalizeInsInstrs() local 1616 MIB.add(FRM); in finalizeInsInstrs() 1617 if (FRM.getImm() == RISCVFPRndMode::DYN) in finalizeInsInstrs() 1618 MIB.addUse(RISCV::FRM, RegState::Implicit); in finalizeInsInstrs() 2541 !MI.readsRegister(RISCV::FRM, /*TRI=*/nullptr)) { in verifyInstruction()
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| HD | RISCVInstrInfo.td | 1788 def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>; 1789 def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>; 1790 def WriteFRMImm : WriteSysRegImm<SysRegFRM, [FRM]>; 1791 def SwapFRMImm : SwapSysRegImm<SysRegFRM, [FRM]>;
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| HD | RISCVRegisterInfo.cpp | 144 markSuperRegs(Reserved, RISCV::FRM); in getReservedRegs()
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| HD | RISCVISelLowering.cpp | 3109 RISCVFPRndMode::RoundingMode FRM = matchRoundingOp(Op.getOpcode()); in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() local 3110 assert(FRM != RISCVFPRndMode::Invalid); in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() 3112 DAG.getTargetConstant(FRM, DL, XLenVT), VL); in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() 3212 RISCVFPRndMode::RoundingMode FRM = matchRoundingOp(Op.getOpcode()); in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND() local 3213 assert(FRM != RISCVFPRndMode::Invalid); in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND() 3216 {Chain, Src, Mask, DAG.getTargetConstant(FRM, DL, XLenVT), VL}); in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND() 3272 RISCVFPRndMode::RoundingMode FRM = matchRoundingOp(Op.getOpcode()); in lowerFTRUNC_FCEIL_FFLOOR_FROUND() local 3274 DAG.getTargetConstant(FRM, DL, Subtarget.getXLenVT())); in lowerFTRUNC_FCEIL_FFLOOR_FROUND() 15305 RISCVFPRndMode::RoundingMode FRM = matchRoundingOp(Src.getOpcode()); in performFP_TO_INTCombine() local 15307 if (FRM == RISCVFPRndMode::Invalid) in performFP_TO_INTCombine() [all …]
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| HD | RISCVRegisterInfo.td | 628 def FRM : RISCVReg<0, "frm">;
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| HD | RISCVInstrInfoXSf.td | 221 Uses = [FRM] in {
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| /freebsd-13-stable/sys/contrib/device-tree/src/arm/ |
| HD | ste-href-family-pinctrl.dtsi | 19 pins = "GPIO216_AG12"; /* FRM */ 57 "GPIO216_AG12", /* FRM */
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| HD | ste-snowball.dts | 532 pins = "GPIO144_B13"; /* FRM */
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| HD | RISCVAsmParser.cpp | 340 FRM, enumerator 374 RISCVFPRndMode::RoundingMode FRM; member 402 struct FRMOp FRM; member 435 case KindTy::FRM: in RISCVOperand() 436 FRM = o.FRM; in RISCVOperand() 605 bool isFRMArg() const { return Kind == KindTy::FRM; } in isFRMArg() 606 bool isFRMArgLegacy() const { return Kind == KindTy::FRM; } in isFRMArgLegacy() 607 bool isRTZArg() const { return isFRMArg() && FRM.FRM == RISCVFPRndMode::RTZ; } in isRTZArg() 1040 assert(Kind == KindTy::FRM && "Invalid type access!"); in getFRM() 1041 return FRM.FRM; in getFRM() [all …]
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