Searched refs:FPOWI (Results 1 – 18 of 18) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
| HD | ConstrainedOps.def | 95 DAG_FUNCTION(powi, 2, 1, experimental_constrained_powi, FPOWI)
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 972 FPOWI, enumerator
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| HD | LegalizeFloatTypes.cpp | 124 case ISD::FPOWI: in SoftenFloatResult()
677 N->getOpcode() == ISD::FPOWI || N->getOpcode() == ISD::STRICT_FPOWI; in SoftenFloatRes_ExpOp()
1450 case ISD::FPOWI: ExpandFloatRes_FPOWI(N, Lo, Hi); break; in ExpandFloatResult()
2642 case ISD::FPOWI: in PromoteFloatResult()
3082 case ISD::FPOWI: in SoftPromoteHalfResult()
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| HD | SelectionDAGDumper.cpp | 314 case ISD::FPOWI: return "fpowi"; in getOperationName()
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| HD | LegalizeVectorOps.cpp | 412 case ISD::FPOWI: in LegalizeOp()
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| HD | LegalizeVectorTypes.cpp | 63 case ISD::FPOWI: in ScalarizeVectorResult()
1087 case ISD::FPOWI: in SplitVectorResult()
4484 case ISD::FPOWI: in WidenVectorResult()
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| HD | LegalizeDAG.cpp | 4661 case ISD::FPOWI: in ConvertNodeToLibcall()
5495 case ISD::FPOWI: { in PromoteNode()
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| HD | LegalizeIntegerTypes.cpp | 1996 case ISD::FPOWI: in PromoteIntegerOperand()
2526 N->getOpcode() == ISD::FPOWI || N->getOpcode() == ISD::STRICT_FPOWI; in PromoteIntOp_ExpOp()
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| HD | SelectionDAGBuilder.cpp | 5881 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); in ExpandPowI()
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| HD | SelectionDAG.cpp | 5453 case ISD::FPOWI: in isKnownNeverNaN()
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| HD | TargetLoweringBase.cpp | 763 setOperationAction({ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP}, VT, in initActions()
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| HD | AMDGPUISelDAGToDAG.cpp | 152 case ISD::FPOWI: in fp16SrcZerosHighBits()
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| HD | SIISelLowering.cpp | 212 ISD::FSIN, ISD::FCOS, ISD::FPOW, ISD::FPOWI, in SITargetLowering()
475 setOperationAction({ISD::FPOW, ISD::FPOWI}, MVT::f16, Promote); in SITargetLowering()
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| HD | MipsSEISelLowering.cpp | 143 setOperationAction(ISD::FPOWI, MVT::f16, Promote); in MipsSETargetLowering()
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| HD | RISCVISelLowering.cpp | 505 setOperationAction({ISD::FREM, ISD::FPOW, ISD::FPOWI, in RISCVTargetLowering()
521 setOperationAction(ISD::FPOWI, MVT::i32, Custom); in RISCVTargetLowering()
6470 case ISD::FPOWI: { in LowerOperation()
6478 DAG.getNode(ISD::FPOWI, DL, MVT::f32, Op0, Op.getOperand(1)); in LowerOperation()
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 735 for (auto Op : {ISD::FREM, ISD::FPOW, ISD::FPOWI, in AArch64TargetLowering()
1625 setOperationAction(ISD::FPOWI, VT, Expand); in AArch64TargetLowering()
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| HD | PPCISelLowering.cpp | 1193 setOperationAction(ISD::FPOWI, MVT::f128, Expand); in PPCTargetLowering()
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| HD | ARMISelLowering.cpp | 1546 setOperationAction(ISD::FPOWI, MVT::f16, Promote); in ARMTargetLowering()
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