1 /* SPDX-License-Identifier: BSD-2-Clause AND BSD-3-Clause */ 2 /* $NetBSD: qat_c62xreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */ 3 4 /* 5 * Copyright (c) 2019 Internet Initiative Japan, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Copyright(c) 2014 Intel Corporation. 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 36 * * Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * * Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in 40 * the documentation and/or other materials provided with the 41 * distribution. 42 * * Neither the name of Intel Corporation nor the names of its 43 * contributors may be used to endorse or promote products derived 44 * from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 47 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 48 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 49 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 50 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 51 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 56 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 60 #ifndef _DEV_PCI_QAT_C62XREG_H_ 61 #define _DEV_PCI_QAT_C62XREG_H_ 62 63 /* Max number of accelerators and engines */ 64 #define MAX_ACCEL_C62X 5 65 #define MAX_AE_C62X 10 66 67 /* PCIe BAR index */ 68 #define BAR_SRAM_ID_C62X 0 69 #define BAR_PMISC_ID_C62X 1 70 #define BAR_ETR_ID_C62X 2 71 72 /* BAR PMISC sub-regions */ 73 #define AE_OFFSET_C62X 0x20000 74 #define AE_LOCAL_OFFSET_C62X 0x20800 75 #define CAP_GLOBAL_OFFSET_C62X 0x30000 76 77 #define SOFTSTRAP_REG_C62X 0x2EC 78 #define SOFTSTRAP_SS_POWERGATE_CY_C62X __BIT(23) 79 #define SOFTSTRAP_SS_POWERGATE_PKE_C62X __BIT(24) 80 81 #define ACCEL_REG_OFFSET_C62X 16 82 #define ACCEL_MASK_C62X 0x1F 83 #define AE_MASK_C62X 0x3FF 84 85 #define SMIAPF0_C62X 0x3A028 86 #define SMIAPF1_C62X 0x3A030 87 #define SMIA0_MASK_C62X 0xFFFF 88 #define SMIA1_MASK_C62X 0x1 89 90 /* Error detection and correction */ 91 #define AE_CTX_ENABLES_C62X(i) ((i) * 0x1000 + 0x20818) 92 #define AE_MISC_CONTROL_C62X(i) ((i) * 0x1000 + 0x20960) 93 #define ENABLE_AE_ECC_ERR_C62X __BIT(28) 94 #define ENABLE_AE_ECC_PARITY_CORR_C62X (__BIT(24) | __BIT(12)) 95 #define ERRSSMSH_EN_C62X __BIT(3) 96 /* BIT(2) enables the logging of push/pull data errors. */ 97 #define PPERR_EN_C62X (__BIT(2)) 98 99 /* Mask for VF2PF interrupts */ 100 #define VF2PF1_16_C62X (0xFFFF << 9) 101 #define ERRSOU3_VF2PF_C62X(errsou3) (((errsou3) & 0x01FFFE00) >> 9) 102 #define ERRMSK3_VF2PF_C62X(vf_mask) (((vf_mask) & 0xFFFF) << 9) 103 104 /* Masks for correctable error interrupts. */ 105 #define ERRMSK0_CERR_C62X (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0)) 106 #define ERRMSK1_CERR_C62X (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0)) 107 #define ERRMSK3_CERR_C62X (__BIT(7)) 108 #define ERRMSK4_CERR_C62X (__BIT(8) | __BIT(0)) 109 #define ERRMSK5_CERR_C62X (0) 110 111 /* Masks for uncorrectable error interrupts. */ 112 #define ERRMSK0_UERR_C62X (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1)) 113 #define ERRMSK1_UERR_C62X (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1)) 114 #define ERRMSK3_UERR_C62X (__BIT(8) | __BIT(6) | __BIT(5) | __BIT(4) | \ 115 __BIT(3) | __BIT(2) | __BIT(0)) 116 #define ERRMSK4_UERR_C62X (__BIT(9) | __BIT(1)) 117 #define ERRMSK5_UERR_C62X (__BIT(18) | __BIT(17) | __BIT(16)) 118 119 /* RI CPP control */ 120 #define RICPPINTCTL_C62X (0x3A000 + 0x110) 121 /* 122 * BIT(2) enables error detection and reporting on the RI Parity Error. 123 * BIT(1) enables error detection and reporting on the RI CPP Pull interface. 124 * BIT(0) enables error detection and reporting on the RI CPP Push interface. 125 */ 126 #define RICPP_EN_C62X (__BIT(2) | __BIT(1) | __BIT(0)) 127 128 /* TI CPP control */ 129 #define TICPPINTCTL_C62X (0x3A400 + 0x138) 130 /* 131 * BIT(3) enables error detection and reporting on the ETR Parity Error. 132 * BIT(2) enables error detection and reporting on the TI Parity Error. 133 * BIT(1) enables error detection and reporting on the TI CPP Pull interface. 134 * BIT(0) enables error detection and reporting on the TI CPP Push interface. 135 */ 136 #define TICPP_EN_C62X \ 137 (__BIT(4) | __BIT(3) | __BIT(2) | __BIT(1) | __BIT(0)) 138 139 /* CFC Uncorrectable Errors */ 140 #define CPP_CFC_ERR_CTRL_C62X (0x30000 + 0xC00) 141 /* 142 * BIT(1) enables interrupt. 143 * BIT(0) enables detecting and logging of push/pull data errors. 144 */ 145 #define CPP_CFC_UE_C62X (__BIT(1) | __BIT(0)) 146 147 /* Correctable SecureRAM Error Reg */ 148 #define SECRAMCERR_C62X (0x3AC00 + 0x00) 149 /* BIT(3) enables fixing and logging of correctable errors. */ 150 #define SECRAM_CERR_C62X (__BIT(3)) 151 152 /* Uncorrectable SecureRAM Error Reg */ 153 /* 154 * BIT(17) enables interrupt. 155 * BIT(3) enables detecting and logging of uncorrectable errors. 156 */ 157 #define SECRAM_UERR_C62X (__BIT(17) | __BIT(3)) 158 159 /* Miscellaneous Memory Target Errors Register */ 160 /* 161 * BIT(3) enables detecting and logging push/pull data errors. 162 * BIT(2) enables interrupt. 163 */ 164 #define TGT_UERR_C62X (__BIT(3) | __BIT(2)) 165 166 167 #define SLICEPWRDOWN_C62X(i) ((i) * 0x4000 + 0x2C) 168 /* Enabling PKE4-PKE0. */ 169 #define MMP_PWR_UP_MSK_C62X \ 170 (__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16)) 171 172 /* CPM Uncorrectable Errors */ 173 #define INTMASKSSM_C62X(i) ((i) * 0x4000 + 0x0) 174 /* Disabling interrupts for correctable errors. */ 175 #define INTMASKSSM_UERR_C62X \ 176 (__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1)) 177 178 /* MMP */ 179 /* BIT(3) enables correction. */ 180 #define CERRSSMMMP_EN_C62X (__BIT(3)) 181 182 /* BIT(3) enables logging. */ 183 #define UERRSSMMMP_EN_C62X (__BIT(3)) 184 185 /* ETR */ 186 #define ETR_MAX_BANKS_C62X 16 187 #define ETR_TX_RX_GAP_C62X 8 188 #define ETR_TX_RINGS_MASK_C62X 0xFF 189 #define ETR_BUNDLE_SIZE_C62X 0x1000 190 191 /* AE firmware */ 192 #define AE_FW_PROD_TYPE_C62X 0x01000000 193 #define AE_FW_MOF_NAME_C62X "qat_c62xfw" 194 #define AE_FW_MMP_NAME_C62X "qat_c62x_mmp" 195 #define AE_FW_UOF_NAME_C62X "icp_qat_ae.suof" 196 197 /* Clock frequency */ 198 #define CLOCK_PER_SEC_C62X (685 * 1000000 / 16) 199 200 #endif 201