Home
last modified time | relevance | path

Searched refs:v8i8 (Results 1 – 25 of 46) sorted by relevance

12

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td17 CCIfType<[i64,v2i32,v4i16,v8i8],
43 CCIfType<[i64,v2i32,v4i16,v8i8],
45 CCIfType<[i64,v2i32,v4i16,v8i8],
73 CCIfType<[i64,v2i32,v4i16,v8i8],
75 CCIfType<[i64,v2i32,v4i16,v8i8],
99 CCIfType<[i64,v2i32,v4i16,v8i8],
DHexagonPatterns.td86 def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>;
474 // All of these are bitcastable to one another: i64, v2i32, v4i16, v8i8.
477 defm: NopCast_pat<i64, v8i8, DoubleRegs>;
479 defm: NopCast_pat<v2i32, v8i8, DoubleRegs>;
480 defm: NopCast_pat<v4i16, v8i8, DoubleRegs>;
516 def: Pat<(v8i8 (sext V8I1:$Pu)), (C2_mask V8I1:$Pu)>;
529 def: Pat<(v8i8 (azext V8I1:$Pu)),
967 def: OpR_RR_pat<A2_vminb, Smin, v8i8, V8I8>;
968 def: OpR_RR_pat<A2_vmaxb, Smax, v8i8, V8I8>;
969 def: OpR_RR_pat<A2_vminub, Umin, v8i8, V8I8>;
[all …]
DHexagonISelLowering.cpp645 VT == MVT::v4i16 || VT == MVT::v8i8 || in getPostIndexedAddressParts()
1480 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1696 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1715 for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1726 for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8, in HexagonTargetLowering()
1738 for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16, in HexagonTargetLowering()
1756 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in HexagonTargetLowering()
1783 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) { in HexagonTargetLowering()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td643 (instregex "^ML(A|S)(v8i8|v4i16|v2i32)(_indexed)?$")>;
658 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^ADD(v1i64|v2i32|v4i16|v8i8)$")>;
660 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v8i8$")>;
662 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^NEG(v1i64|v2i32|v4i16|v8i8)$")>;
663 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^SUB(v1i64|v2i32|v4i16|v8i8)$")>;
665 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v2i32|v4i16|v8i8)(_v.…
667 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)SHR(v2i32|v4i16|v8i8)_shift$")>;
669 …_2cyc], (instregex "^((S|U)?(MAX|MIN)P?|ABS|ADDP|CM(EQ|GE|HS|GT|HI))(v1i64|v2i32|v4i16|v8i8)$")>;
670 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|GE|HS|GT|HI)(v1i64|v2i32|v4i16|v8i8)$")>;
671 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|LE|GE|GT|LT)(v1i64|v2i32|v4i16|v8i8)rz$")>;
[all …]
DAArch64SchedKryoDetails.td19 (instregex "(S|U)R?SRA(d|(v2i32|v4i16|v8i8)_shift)")>;
33 (instregex "(S|U)ABA(v8i8|v4i16|v2i32)")>;
57 (instregex "(S|U)(ABD|RHADD)(v8i8|v4i16|v2i32)")>;
69 (instregex "(S|U)ADALP(v8i8|v4i16|v2i32)_v.*")>;
87 (instregex "((S|U)ADDLP|ABS)(v2i32|v4i16|v8i8)(_v.*)?")>;
171 (instregex "((S|U)H(ADD|SUB)|ADDP)(v8i8|v4i16|v2i32)")>;
201 (instregex "^(S|U)QADD(v8i8|v4i16|v2i32)")>;
219 (instregex "(S|U)QSHLU?(d|s|h|b|(v8i8|v4i16|v2i32)_shift)$")>;
231 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;
255 (instregex "((S|U)QR?SHRN|SQR?SHRUN)(v8i8|v4i16|v2i32)_shift?")>;
[all …]
DAArch64ISelDAGToDAG.cpp3599 if (VT == MVT::v8i8) { in Select()
3626 if (VT == MVT::v8i8) { in Select()
3653 if (VT == MVT::v8i8) { in Select()
3680 if (VT == MVT::v8i8) { in Select()
3707 if (VT == MVT::v8i8) { in Select()
3734 if (VT == MVT::v8i8) { in Select()
3761 if (VT == MVT::v8i8) { in Select()
3788 if (VT == MVT::v8i8) { in Select()
3815 if (VT == MVT::v8i8) { in Select()
3842 if (VT == MVT::v16i8 || VT == MVT::v8i8) { in Select()
[all …]
DAArch64TargetTransformInfo.cpp233 static const auto ValidMinMaxTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
244 static const auto ValidSatTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
257 static const auto ValidAbsTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
282 {Intrinsic::bitreverse, MVT::v8i8, 1}, in getIntrinsicInstrCost()
312 {ISD::CTPOP, MVT::v8i8, 1}, in getIntrinsicInstrCost()
951 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
977 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
978 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
981 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
982 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
[all …]
DAArch64InstrInfo.td914 def v8i8 : BaseSIMDSUDOTIndex<0, ".2s", ".8b", ".4b", V64, v2i32, v8i8>;
2445 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
2492 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
2601 def : Pat <(v8i8 (scalar_to_vector (i32
2603 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
2638 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
2830 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
3169 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
3268 def : Pat<(store (v8i8 FPR64:$Rt),
3411 def : Pat<(store (v8i8 FPR64:$Rt),
[all …]
DAArch64CallingConvention.td33 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8],
112 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
121 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16],
138 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8],
156 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
238 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
255 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16],
276 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
298 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
360 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
DAArch64SchedA57.td347 // D form - v8i8, v4i16, v2i32
359 def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)…
366 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
375 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
381 def : InstRW<[A57Write_5cyc_1W_Mul_Forward], (instregex "^MUL(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i…
383 def : InstRW<[A57Write_5cyc_1W], (instregex "^(PMUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1…
396 def : InstRW<[A57Write_5cyc_1W_Mul_Forward, A57ReadIVMA4], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_i…
408 def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>;
425 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
518 // D form - v8i8, v4i16, v2i32
DAArch64InstrFormats.td5357 def v8i8 : BaseSIMDThreeSameVectorPseudo<V64,
5358 [(set (v8i8 V64:$dst),
5359 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5367 (!cast<Instruction>(NAME#"v8i8")
5371 (!cast<Instruction>(NAME#"v8i8")
5375 (!cast<Instruction>(NAME#"v8i8")
5395 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64,
5397 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5419 def : Pat<(v8i8 (OpNode V64:$LHS, V64:$RHS)),
5420 (!cast<Instruction>(inst#"v8i8") V64:$LHS, V64:$RHS)>;
[all …]
DAArch64SchedTSV110.td521 // D form - v8i8, v4i16, v2i32
553 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v8i8|v4i16|v2i32|v1i8|v1i…
559 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v8i8|v16i8)")>;
574 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16…
580 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
589 def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
DAArch64SchedThunderX2T99.td1274 def : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^PMULL(v8i8|v16i8)")>;
1279 (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>;
1288 (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
1300 (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
1307 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1314 (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>;
1336 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
1343 (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;
DAArch64SchedThunderX3T110.td1381 def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^PMULL(v8i8|v16i8)")>;
1386 (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>;
1395 (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
1407 (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
1414 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1421 (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>;
1443 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
1450 (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;
DAArch64ISelLowering.cpp268 addDRTypeForNEON(MVT::v8i8); in AArch64TargetLowering()
1006 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i8, MVT::v8i32); in AArch64TargetLowering()
1007 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i8, MVT::v8i32); in AArch64TargetLowering()
1037 setOperationAction(ISD::BITREVERSE, MVT::v8i8, Legal); in AArch64TargetLowering()
1052 for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32, in AArch64TargetLowering()
1060 for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v16i8, MVT::v8i16, in AArch64TargetLowering()
1076 for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32, in AArch64TargetLowering()
1232 MVT::v2f64, MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16, in AArch64TargetLowering()
1321 for (auto VT : {MVT::v8i8, MVT::v4i16}) in AArch64TargetLowering()
1342 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); in AArch64TargetLowering()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMInstrNEON.td529 def SDTARMVTBL1 : SDTypeProfile<1, 2, [SDTCisVT<0, v8i8>, SDTCisVT<1, v8i8>,
530 SDTCisVT<2, v8i8>]>;
531 def SDTARMVTBL2 : SDTypeProfile<1, 3, [SDTCisVT<0, v8i8>, SDTCisVT<1, v8i8>,
532 SDTCisVT<2, v8i8>, SDTCisVT<3, v8i8>]>;
1060 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
1108 def : Pat<(insert_subvector (v16i8 undef), (v8i8 DPR:$src), (i32 0)),
1382 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8,
2166 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
2217 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
3309 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
[all …]
DARMTargetTransformInfo.cpp468 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost()
469 {ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost()
503 {ISD::TRUNCATE, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost()
505 {ISD::TRUNCATE, MVT::v8i32, MVT::v8i8, 1}, in getCastInstrCost()
534 { ISD::ADD, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
537 { ISD::SUB, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
540 { ISD::MUL, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
543 { ISD::SHL, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
584 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, in getCastInstrCost()
585 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, in getCastInstrCost()
[all …]
DARMCallingConv.td33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
186 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
213 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
236 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
DARMScheduleA57.td978 (instregex "VABA(s|u)(v8i8|v4i16|v2i32)")>;
1021 "VMUL(v8i8|v4i16|v2i32|pd)", "VMULsl(v4i16|v2i32)",
1043 (instregex "VMLA(sl)?(v8i8|v4i16|v2i32)", "VMLS(sl)?(v8i8|v4i16|v2i32)")>;
1120 "VSLI(v8i8|v4i16|v2i32|v1i64)", "VSRI(v8i8|v4i16|v2i32|v1i64)")>;
1128 "VSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;
1137 "VQRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)", "VQSHL(s|u)(v8i8|v4i16|v2i32|v1i64)",
1138 "VRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;
1213 "VMOV(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v1i64|v2i64|v2f32|v4f32)",
DARMScheduleR52.td764 def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VABA(u|s)(v8i8|v4i…
768 def : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VABD(u|s)(v8i8|v4i16|v2i32)")>;
775 (instregex "(VADD|VSUB)(v8i8|v4i16|v2i32|v1i64)")>;
779 (instregex "(VADDHN|VRADDHN|VSUBHN|VRSUBHN)(v8i8|v4i16|v2i32)")>;
809 def : InstRW<[R52WriteFPALU_F4, R52Read_F2, R52Read_F2], (instregex "(VHADD|VHSUB)(u|s)(v8i8|v4i16|…
819 def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VQABS(v8i8|v4i16|v2i32|v1i64)")>;
822 (instregex "(VQADD|VQSUB)(u|s)(v8i8|v4i16|v2i32|v1i64)")>;
DARMRegisterInfo.td432 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
453 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
460 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h79 v8i8 = 29, // 8 x i8 enumerator
399 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 || in is64BitVector()
544 case v8i8: in getVectorElementType()
759 case v8i8: in getVectorMinNumElements()
926 case v8i8: in getSizeInBits()
1198 if (NumElements == 8) return MVT::v8i8; in getVectorVT()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp1134 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw in getShuffleCost()
1145 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw in getShuffleCost()
1151 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw in getShuffleCost()
1530 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, in getCastInstrCost()
1543 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, in getCastInstrCost()
1559 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm in getCastInstrCost()
1561 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb in getCastInstrCost()
1593 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd in getCastInstrCost()
1612 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb in getCastInstrCost()
1627 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, in getCastInstrCost()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td151 [i64, f64, v8i8, v4i16, v2i32, v2f32], 64,
275 defm VR64 : SystemZRegClass<"VR64", [f64, v8i8, v4i16, v2i32, v2f32], 64,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp302 setLoadExtAction(Ext, MVT::v8i16, MVT::v8i8, Legal); in WebAssemblyTargetLowering()
307 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal); in WebAssemblyTargetLowering()
768 return (ExtT == MVT::v8i16 && MemT == MVT::v8i8) || in isVectorLoadExtDesirable()
2203 if (Extract.getValueType() != MVT::v8i8 || in performVectorExtendCombine()

12