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Searched refs:v64i1 (Results 1 – 17 of 17) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86InstrVecCompiler.td188 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
191 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
194 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
197 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
242 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
245 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
300 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
303 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
314 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
325 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
[all …]
DX86CallingConv.td93 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
94 CCIfType<[v64i1], CCPromoteToType<i64>>,
172 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
173 CCIfType<[v64i1], CCPromoteToType<i64>>,
231 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
552 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
845 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
DX86RegisterInfo.td615 def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}
633 def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
DX86FrameLowering.cpp2500 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1; in assignCalleeSavedSpillSlots()
2580 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1; in spillCalleeSavedRegisters()
2660 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1; in restoreCalleeSavedRegisters()
DX86TargetTransformInfo.cpp1536 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, in getCastInstrCost()
1549 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, in getCastInstrCost()
1566 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, in getCastInstrCost()
3857 { ISD::AND, MVT::v64i1, 13 }, in getArithmeticReductionCost()
3863 { ISD::OR, MVT::v64i1, 13 }, in getArithmeticReductionCost()
DX86ISelLowering.cpp1868 addRegisterClass(MVT::v64i1, &X86::VK64RegClass); in X86TargetLowering()
1870 for (auto VT : { MVT::v32i1, MVT::v64i1 }) { in X86TargetLowering()
2108 if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() && in getPreferredVectorAction()
2205 if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() && in getVectorTypeBreakdownForCallingConv()
2646 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) { in lowerMasksToReg()
2777 assert(VA.getValVT() == MVT::v64i1 && in LowerReturn()
2955 assert(VA.getValVT() == MVT::v64i1 && in getv64i1Argument()
2994 return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi); in getv64i1Argument()
3008 if (ValVT == MVT::v64i1) { in lowerRegToMasks()
3094 assert(VA.getValVT() == MVT::v64i1 && in LowerCallResult()
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DX86InstrAVX512.td170 def v64i1_info : X86KVectorVTInfo<VK64, VK64WM, v64i1>;
2809 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
2850 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))),
2852 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))),
2898 defm : operation_gpr_mask_copy_lowering<VK64, v64i1>;
3272 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
3304 defm : operation_subvector_mask_lowering<VK1, v1i1, VK64, v64i1>;
3310 defm : operation_subvector_mask_lowering<VK2, v2i1, VK64, v64i1>;
3315 defm : operation_subvector_mask_lowering<VK4, v4i1, VK64, v64i1>;
3319 defm : operation_subvector_mask_lowering<VK8, v8i1, VK64, v64i1>;
[all …]
DX86InstrCompiler.td581 defm _VK64 : CMOVrr_PSEUDO<VK64, v64i1>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td28 def : Pat <(v64i1 (bitconvert (v16i32 HvxVR:$src1))),
29 (v64i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
31 def : Pat <(v64i1 (bitconvert (v32i16 HvxVR:$src1))),
32 (v64i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
34 def : Pat <(v64i1 (bitconvert (v64i8 HvxVR:$src1))),
35 (v64i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
37 def : Pat <(v16i32 (bitconvert (v64i1 HvxQR:$src1))),
38 (v16i32 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
40 def : Pat <(v32i16 (bitconvert (v64i1 HvxQR:$src1))),
41 (v32i16 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
DHexagonRegisterInfo.td322 [v64i1, v128i1, v64i1]>;
338 [v64i1, v128i1, v64i1]>;
340 [v32i1, v64i1, v32i1]>;
DHexagonISelDAGToDAGHVX.cpp2474 SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v64i1); in SelectHVXDualOutput()
2488 SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v64i1); in SelectHVXDualOutput()
DHexagonISelLoweringHVX.cpp46 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
55 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h70 v64i1 = 21, // 64 x i1 enumerator
399 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 || in is64BitVector()
529 case v64i1: in getVectorElementType()
716 case v64i1: in getVectorMinNumElements()
925 case v64i1: in getSizeInBits()
1188 if (NumElements == 64) return MVT::v64i1; in getVectorVT()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td43 def v64i1 : ValueType<64, 21>; // 64 x i1 vector value
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp219 case MVT::v64i1: in getTypeForEVT()
/freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp89 case MVT::v64i1: return "MVT::v64i1"; in getEnumName()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/IR/
DIntrinsics.td269 def llvm_v64i1_ty : LLVMType<v64i1>; // 64 x i1