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Searched refs:v4i32 (Results 1 – 25 of 94) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td408 [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
420 [(set v4i32:$vD, (int_ppc_altivec_lvewx ForceXForm:$src))]>;
423 [(set v4i32:$vD, (int_ppc_altivec_lvx ForceXForm:$src))]>;
426 [(set v4i32:$vD, (int_ppc_altivec_lvxl ForceXForm:$src))]>;
447 [(int_ppc_altivec_stvewx v4i32:$rS, ForceXForm:$dst)]>;
450 [(int_ppc_altivec_stvx v4i32:$rS, ForceXForm:$dst)]>;
453 [(int_ppc_altivec_stvxl v4i32:$rS, ForceXForm:$dst)]>;
478 v4i32, v4i32, v16i8>;
479 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
501 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
[all …]
DPPCInstrVSX.td702 int_ppc_vsx_xvcmpeqsp, v4i32, v4f32>;
708 int_ppc_vsx_xvcmpgesp, v4i32, v4f32>;
714 int_ppc_vsx_xvcmpgtsp, v4i32, v4f32>;
836 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>;
844 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpuxws v2f64:$XB))]>;
857 [(set v4i32:$XT, (any_fp_to_sint v4f32:$XB))]>;
865 [(set v4i32:$XT, (any_fp_to_uint v4f32:$XB))]>;
877 [(set v4f32:$XT, (any_sint_to_fp v4i32:$XB))]>;
889 [(set v4f32:$XT, (any_uint_to_fp v4i32:$XB))]>;
895 [(set v2f64:$XT, (int_ppc_vsx_xvcvsxwdp v4i32:$XB))]>;
[all …]
DPPCInstrPrefix.td17 SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>,
18 SDTCisVT<3, v4i32>, SDTCisVT<4, v4i32>
21 SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>
24 SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2>
27 SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2>
1601 dag Vec0 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx0));
1602 dag Vec1 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx1));
1603 dag Vec2 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx0));
1604 dag Vec3 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx1));
1608 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
[all …]
DREADME_P9.txt16 (set v2i64:$vD, (int_ppc_altivec_vextractuw v4i32:$vA, imm:$UIMM))
25 (set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB))
30 (set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
35 (set v4i32:$vD, (int_ppc_altivec_vinserth v4i32:$vA, imm:$UIMM))
48 (set v4i32:$vD, (cttz v4i32:$vB)) // vctzw
53 (set v4i32:$vD, (sext v4i8:$vB))
61 (set v4i32:$vD, (sext v4i16:$vB))
94 (set v4i32:$rT, (ineg v4i32:$rA)) // vnegw
99 (set v4i32:$rD, (int_ppc_altivec_vprtybw v4i32:$vB))
112 VX1_Int_Ty<389, "vrlwnm", int_ppc_altivec_vrlwnm, v4i32>;
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp222 { ISD::MUL, MVT::v4i32, 11 }, // pmulld in getArithmeticInstrCost()
245 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { in getArithmeticInstrCost()
385 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence in getArithmeticInstrCost()
386 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
389 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence in getArithmeticInstrCost()
390 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
484 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence in getArithmeticInstrCost()
485 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
488 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence in getArithmeticInstrCost()
489 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
[all …]
DX86InstrXOP.td127 defm VPROTD : xop3op<0x92, "vprotd", rotl, v4i32, SchedWriteVarVecShift.XMM>;
131 defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32, SchedWriteVarVecShift.XMM>;
135 defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32, SchedWriteVarVecShift.XMM>;
159 defm VPROTD : xop3opimm<0xC2, "vprotd", X86vrotli, v4i32,
220 def : Pat<(v4i32 (add (mul (v4i32 VR128:$src1), (v4i32 VR128:$src2)),
221 (v4i32 VR128:$src3))),
223 def : Pat<(v2i64 (add (X86pmuldq (bc_v2i64 (X86PShufd (v4i32 VR128:$src1), (i8 -11))),
224 (bc_v2i64 (X86PShufd (v4i32 VR128:$src2), (i8 -11)))),
230 def : Pat<(v4i32 (add (X86vpmaddwd (v8i16 VR128:$src1), (v8i16 VR128:$src2)),
231 (v4i32 VR128:$src3))),
[all …]
DX86InstrSSE.td141 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
170 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
300 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
301 (VMOVSSrr (v4i32 (V_SET0)), VR128:$src)>;
310 (v4i32 (VMOVSSrr (v4i32 (V_SET0)),
311 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)))), sub_xmm)>;
319 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
320 (MOVSSrr (v4i32 (V_SET0)), VR128:$src)>;
599 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
607 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMInstrMVE.td296 def MVE_v8i16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "i", ?>;
297 def MVE_v4i32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, v4i1, 0b10, "i", ?>;
304 def MVE_v8s16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "s", 0b0>;
305 def MVE_v4s32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, v4i1, 0b10, "s", 0b0>;
308 def MVE_v8u16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "u", 0b1>;
309 def MVE_v4u32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, v4i1, 0b10, "u", 0b1>;
319 def MVE_v8p16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b11, "p", 0b1>;
819 def : Pat<(ARMVADDLV (v4i32 MQPR:$vec)),
820 (InstN (v4i32 MQPR:$vec))>;
821 def : Pat<(ARMVADDLVA tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec)),
[all …]
DARMTargetTransformInfo.cpp464 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
465 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
466 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
467 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
501 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
502 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
533 { ISD::ADD, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
536 { ISD::SUB, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
539 { ISD::MUL, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
542 { ISD::SHL, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
[all …]
DARMInstrNEON.td1074 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1101 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
1410 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load,
2184 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
2234 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
3344 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3347 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4i32 QPR:$Vm), fc)))]>;
3351 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4f32 QPR:$Vm), fc)))]> {
3411 def v4i32 : N3VQ_cmp<op24, op23, 0b10, op11_8, op4, itinQ32,
3413 v4i32, v4i32, fc, Commutable>;
[all …]
DARMCallingConv.td34 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
60 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
75 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
95 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
112 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
169 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
187 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
214 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
237 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DBUFInstructions.td523 (load_vt (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset))),
524 (load_vt (inst v4i32:$srsrc, i32:$soffset, i16:$offset))
530 (load_vt (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset))),
531 (load_vt (inst i64:$vaddr, v4i32:$srsrc, i32:$soffset, i16:$offset))
601 [(st legal_store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
606 [(st legal_store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
774 (atomic (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset),
781 (atomic (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset),
843 "buffer_load_format_d16_xyzw", v4i32
855 "buffer_store_format_d16_xyzw", v4i32
[all …]
DCaymanInstructions.td86 def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>;
191 def : R600Pat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
205 def : R600Pat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
219 def : R600Pat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td615 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v2i64|v4i32)rz$")>;
626 def : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^FCVTZ(S|U)(v2i64|v4i32)(_shift)?$")>;
645 (instregex "^ML(A|S)(v16i8|v8i16|v4i32|v2i64)(_indexed)?$")>;
719 …6cyc], (instregex "^(SQR?SHRN|UQR?SHRN|SQR?SHRUN)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32)_shift?$")>;
722 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^ADD(v16i8|v8i16|v4i32|v2i64)$")>;
725 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(BIC|ORR)(v8i16|v4i32)$")>;
726 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(NEG|SUB)(v16i8|v8i16|v4i32|v2i64)$")>;
729 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v16i8|v2i64|v4i32|v8i…
730 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SHLL(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)(_s…
731 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SHR(v16i8|v8i16|v4i32|v2i64)_shift$")>;
[all …]
DAArch64SchedKryoDetails.td26 (instregex "(S|U)R?SRA(v2i64|v4i32|v8i16|v16i8)_shift")>;
39 (instregex "(S|U)ABA(v16i8|v8i16|v4i32)")>;
51 (instregex "(S|U)(ABD|QSUB|RHADD)(v16i8|v8i16|v4i32|v2i64)")>;
75 (instregex "(S|U)ADALP(v16i8|v8i16|v4i32)_v.*")>;
93 (instregex "((S|U)ADDLP|ABS)(v2i64|v4i32|v8i16|v16i8)(_v.*)?")>;
153 (instregex "(S|U)CVTF(v2i64|v4i32|v2f64|v4f32)(_shift)?")>;
165 (instregex "(S|U)H(ADD|SUB)(v16i8|v8i16|v4i32)")>;
207 (instregex "^(S|U)QADD(v16i8|v8i16|v4i32|v2i64)")>;
225 (instregex "(S|U)(QSHLU?|RSHR)(v16i8|v8i16|v4i32|v2i64)_shift$")>;
237 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v16i8|v8i16|v4i32|v2i64)$")>;
[all …]
DAArch64SchedA57.td348 // Q form - v16i8, v8i16, v4i32
350 // Q form - v16i8, v8i16, v4i32, v2i64
361 def : InstRW<[A57Write_5cyc_2X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABA(v16i8|v8i16|v4i32…
368 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
373 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>;
387 def : InstRW<[A57Write_6cyc_2W_Mul_Forward], (instregex "^MUL(v16i8|v8i16|v4i32)(_indexed)?$")>;
389 def : InstRW<[A57Write_6cyc_2W], (instregex "^(PMUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>;
398 def : InstRW<[A57Write_6cyc_2W_Mul_Forward, A57ReadIVMA4], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_…
422 def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
428 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>;
[all …]
DAArch64InstrInfo.td284 def SDT_AArch64stnp : SDTypeProfile<0, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
878 (v4i32 (bitconvert
908 (AArch64duplane32 (v4i32 V128:$Rm),
915 def v16i8 : BaseSIMDSUDOTIndex<1, ".4s", ".16b", ".4b", V128, v4i32, v16i8>;
958 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v4i32>;
963 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v4i32>;
968 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v4i32>;
973 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxs, v4i32>;
996 def : Pat<(v4i32 (int_aarch64_crypto_sm3ss1 (v4i32 V128:$Vn), (v4i32 V128:$Vm), (v4i32 V128:$Va))),
997 (SM3SS1 (v4i32 V128:$Vn), (v4i32 V128:$Vm), (v4i32 V128:$Va))>;
[all …]
DAArch64InstrFormats.td118 UnOpFrag<(extract_subvector (v4i32 node:$LHS), (i64 2))>;
5382 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
5383 (v4i32 V128:$RHS))),
5410 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
5412 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5430 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
5431 (!cast<Instruction>(inst#"v4i32") V128:$LHS, V128:$RHS)>;
5454 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
5456 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
5481 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b101, opc, V128,
[all …]
DAArch64TargetTransformInfo.cpp234 MVT::v8i16, MVT::v2i32, MVT::v4i32}; in getIntrinsicInstrCost()
245 MVT::v8i16, MVT::v2i32, MVT::v4i32, in getIntrinsicInstrCost()
258 MVT::v8i16, MVT::v2i32, MVT::v4i32, in getIntrinsicInstrCost()
287 {Intrinsic::bitreverse, MVT::v4i32, 2}, in getIntrinsicInstrCost()
306 {ISD::CTPOP, MVT::v4i32, 3}, in getIntrinsicInstrCost()
949 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
950 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
975 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
976 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
992 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
[all …]
DAArch64ISelDAGToDAG.cpp710 case MVT::v4i32: in tryMLAV64LaneV128()
739 case MVT::v4i32: in tryMULLV64LaneV128()
750 case MVT::v4i32: in tryMULLV64LaneV128()
3614 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3641 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3668 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3695 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3722 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3749 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
3776 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZCallingConv.td60 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
80 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
124 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
131 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
136 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
199 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
246 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
249 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
275 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
284 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
DSystemZInstrVector.td51 def : VectorExtractSubreg<v4i32, VLGVF>;
203 defm : ReplicatePeephole<VLREPF, v4i32, load, i32>;
418 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>;
464 defm : GenericVectorOps<v4i32, v4i32>;
466 defm : GenericVectorOps<v4f32, v4i32>;
899 defm : BitwiseVectorOps<v4i32>;
935 defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>;
960 defm : IntegerMinMaxVectorOps<v4i32, z_vicmph, VMNF, VMXF>;
966 defm : IntegerMinMaxVectorOps<v4i32, z_vicmphl, VMNLF, VMXLF>;
1528 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td96 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
105 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
114 def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>;
116 def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>;
118 def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>;
120 def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>;
122 def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>;
124 def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>;
126 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
128 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp65 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
84 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
145 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
183 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
187 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
192 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
198 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
203 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
211 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
218 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
DWebAssemblyTypeUtilities.cpp74 .Case("v4i32", MVT::v4i32) in parseMVT()
143 case MVT::v4i32: in toValType()

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