Home
last modified time | relevance | path

Searched refs:v1i32 (Results 1 – 14 of 14) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedA57.td349 // D form - v1i8, v1i16, v1i32, v1i64
381 def : InstRW<[A57Write_5cyc_1W_Mul_Forward], (instregex "^MUL(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i…
383 def : InstRW<[A57Write_5cyc_1W], (instregex "^(PMUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1…
425 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
438 // D form - v1i32, v1i64
453 …yc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
460 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i6…
491 def : InstRW<[A57Write_5cyc_1V_FP_Forward], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
505 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
520 // D form - v1i8, v1i16, v1i32, v1i64
[all …]
DAArch64SchedFalkorDetails.td591 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64|v2i32)rz$")>;
598 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVT(N|M|P|Z|A)(S|U)(v1i32|v1i64|v2f32)$")>;
681 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
683 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2…
685 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
690 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v…
694 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$"…
695 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>;
703 … (instregex "^SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
707 … (instregex "^SQRDML(A|S)H(i16|i32|v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
[all …]
DAArch64SchedKryoDetails.td147 (instregex "(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>;
213 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>;
231 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;
261 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>;
273 (instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>;
693 (instregex "FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64)rz")>;
735 (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v1i32|v1i64|v2f32)$")>;
771 (instregex "FCVTZ(S|U)(v2f32|v1i32|v1i64|v2i32(_shift)?)$")>;
1818 (instregex "SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?")>;
1824 (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>;
DAArch64SchedTSV110.td523 // D form - v1i8, v1i16, v1i32, v1i64
553 …0Wr_4cyc_1FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)")>;
574 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16…
601 // D form - v1i32, v1i64
DAArch64SchedThunderX2T99.td1307 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1336 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
1422 (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
1459 (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
1469 (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
DAArch64SchedThunderX3T110.td1414 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1443 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
1529 (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
1567 (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
1578 (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
DAArch64SchedA64FX.td1682 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1723 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
1814 (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
1851 (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
1861 (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
DAArch64InstrFormats.td6801 def v1i32 : BaseSIMDThreeScalar<U, 0b101, opc, FPR32, asm, []>;
6808 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>;
6813 def v1i32 : BaseSIMDThreeScalar<U, 0b101, opc, FPR32, asm,
6820 def v1i32: BaseSIMDThreeScalarTied<U, 0b10, R, opc, (outs FPR32:$dst),
7030 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,[]>;
7040 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,
7053 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR32, asm,
7068 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
7083 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR64, asm,
8680 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an
[all …]
DAArch64ISelLowering.cpp17382 if (VT == MVT::v1i8 || VT == MVT::v1i16 || VT == MVT::v1i32 || in getPreferredVectorAction()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h100 v1i32 = 48, // 1 x i32 enumerator
392 SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 || in is32BitVector()
576 case v1i32: in getVectorElementType()
828 case v1i32: in getVectorMinNumElements()
911 case v1i32: return TypeSize::Fixed(32); in getSizeInBits()
1221 if (NumElements == 1) return MVT::v1i32; in getVectorVT()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td73 def v1i32 : ValueType<32, 48>; // 1 x i32 vector value
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp273 case MVT::v1i32: in getTypeForEVT()
/freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp116 case MVT::v1i32: return "MVT::v1i32"; in getEnumName()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/IR/
DIntrinsics.td294 def llvm_v1i32_ty : LLVMType<v1i32>; // 1 x i32