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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td74 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
78 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
82 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
86 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
90 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
94 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
100 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
128 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
414 [(set v16i8:$vD, (int_ppc_altivec_lvebx ForceXForm:$src))]>;
431 [(set v16i8:$vD, (int_ppc_altivec_lvsl ForceXForm:$src))]>,
[all …]
DPPCInstrPrefix.td1370 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8 v16i8:$XA, v16i8:$XB)),
1372 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1375 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4 v16i8:$XA, v16i8:$XB)),
1377 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1380 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2s v16i8:$XA, v16i8:$XB)),
1382 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1385 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2 v16i8:$XA, v16i8:$XB)),
1387 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1389 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1391 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
[all …]
DPPCInstrVSX.td1109 [(set v4i32:$XT, (bitconvert (v16i8 immAllOnesV)))]>;
1992 dag LE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDC8 (LI8 8), $Idx)));
1996 dag LE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, LE_VBYTE_PERM_VEC));
2025 (v16i8 (LVSL ZERO8, (RLDICR (ANDC8 (LI8 4), $Idx), 1, 62)));
2029 dag LE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, LE_VHALF_PERM_VEC));
2054 dag LE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
2059 dag LE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VWORD_PERM_VEC));
2084 dag LE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
2089 dag LE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VDWORD_PERM_VEC));
2103 dag LE_VFLOAT_PERM_VEC = (v16i8 (LVSL ZERO8,
[all …]
DREADME_P9.txt14 (set v2i64:$vD, (int_ppc_altivec_vextractub v16i8:$vA, imm:$UIMM))
23 (set i64:$rD, (int_ppc_altivec_vextublx i64:$rA, v16i8:$vB))
28 (set i64:$rD, (int_ppc_altivec_vextubrx i64:$rA, v16i8:$vB))
33 (set v16i8:$vD, (int_ppc_altivec_vinsertb v16i8:$vA, imm:$UIMM))
41 (set i64:$rD, (int_ppc_altivec_vclzlsbb v16i8:$vB))
42 (set i64:$rD, (int_ppc_altivec_vctzlsbb v16i8:$vB))
46 (set v16i8:$vD, (cttz v16i8:$vB)) // vctzb
108 VA1a_Int_Ty3<59, "vpermr", int_ppc_altivec_vpermr, v16i8, v16i8, v16i8>;
128 . VX1_Int_Ty<1860, "vslv", int_ppc_altivec_vslv, v16i8>;
129 VX1_Int_Ty<1796, "vsrv", int_ppc_altivec_vsrv, v16i8>;
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp375 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
376 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
377 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
468 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
469 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
472 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
473 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
510 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. in getArithmeticInstrCost()
511 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. in getArithmeticInstrCost()
512 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. in getArithmeticInstrCost()
[all …]
DX86InstrXOP.td126 defm VPROTB : xop3op<0x90, "vprotb", rotl, v16i8, SchedWriteVarVecShift.XMM>;
130 defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8, SchedWriteVarVecShift.XMM>;
134 defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8, SchedWriteVarVecShift.XMM>;
157 defm VPROTB : xop3opimm<0xC0, "vprotb", X86vrotli, v16i8,
273 defm VPCOMB : xopvpcom<0xCC, "b", X86vpcom, v16i8, SchedWriteVecALU.XMM>;
277 defm VPCOMUB : xopvpcom<0xEC, "ub", X86vpcomu, v16i8, SchedWriteVecALU.XMM>;
305 (v16i8 (OpNode (vt128 VR128:$src1), (vt128 (load addr:$src2)),
323 defm VPPERM : xop4op<0xA3, "vpperm", X86vpperm, v16i8,
375 def : Pat<(v16i8 (or (and VR128:$src3, VR128:$src1),
DX86CallingConv.td110 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
142 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
187 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
229 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
236 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
550 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
555 CCIfType<[f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
583 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
638 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
701 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMInstrCDE.td586 def : Pat<(v16i8 (int_arm_cde_vcx1q timm:$coproc, timm:$imm)),
587 (v16i8 (CDE_VCX1_vec p_imm:$coproc, imm_12b:$imm))>;
588 def : Pat<(v16i8 (int_arm_cde_vcx1qa timm:$coproc, (v16i8 MQPR:$acc),
590 (v16i8 (CDE_VCX1A_vec p_imm:$coproc, MQPR:$acc, imm_12b:$imm))>;
592 def : Pat<(v16i8 (int_arm_cde_vcx2q timm:$coproc, (v16i8 MQPR:$n), timm:$imm)),
593 (v16i8 (CDE_VCX2_vec p_imm:$coproc, MQPR:$n, imm_7b:$imm))>;
594 def : Pat<(v16i8 (int_arm_cde_vcx2qa timm:$coproc, (v16i8 MQPR:$acc),
595 (v16i8 MQPR:$n), timm:$imm)),
596 (v16i8 (CDE_VCX2A_vec p_imm:$coproc, MQPR:$acc, MQPR:$n,
599 def : Pat<(v16i8 (int_arm_cde_vcx3q timm:$coproc, (v16i8 MQPR:$n),
[all …]
DARMInstrMVE.td295 def MVE_v16i8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "i", ?>;
303 def MVE_v16s8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "s", 0b0>;
307 def MVE_v16u8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "u", 0b1>;
318 def MVE_v16p8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b11, "p", 0b0>;
959 def : Pat<(i32 (vecreduce_smax (v16i8 MQPR:$src))),
965 def : Pat<(i32 (vecreduce_umax (v16i8 MQPR:$src))),
972 def : Pat<(i32 (vecreduce_smin (v16i8 MQPR:$src))),
978 def : Pat<(i32 (vecreduce_umin (v16i8 MQPR:$src))),
985 def : Pat<(i32 (ARMVMINVu (i32 rGPR:$x), (v16i8 MQPR:$src))),
991 def : Pat<(i32 (ARMVMINVs (i32 rGPR:$x), (v16i8 MQPR:$src))),
[all …]
DARMCallingConv.td34 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
60 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
75 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
95 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
112 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
169 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
187 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
214 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
237 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
DARMTargetTransformInfo.cpp475 {ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 3}, in getCastInstrCost()
476 {ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 3}, in getCastInstrCost()
477 {ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1}, in getCastInstrCost()
478 {ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1}, in getCastInstrCost()
506 {ISD::TRUNCATE, MVT::v16i32, MVT::v16i8, 3}, in getCastInstrCost()
507 {ISD::TRUNCATE, MVT::v16i16, MVT::v16i8, 1}, in getCastInstrCost()
600 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
601 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
604 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
1164 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1}}; in getShuffleCost()
[all …]
DARMInstrNEON.td1072 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
1108 def : Pat<(insert_subvector (v16i8 undef), (v8i8 DPR:$src), (i32 0)),
1109 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
1406 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8,
2182 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, ARMvgetlaneu>;
2232 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, ARMvgetlaneu>;
3336 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
3339 [(set QPR:$Vd, (v16i8 (ARMvcmpz (v16i8 QPR:$Vm), fc)))]>;
3405 def v16i8 : N3VQ_cmp<op24, op23, 0b00, op11_8, op4, itinQ16,
3407 v16i8, v16i8, fc, Commutable>;
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td645 (instregex "^ML(A|S)(v16i8|v8i16|v4i32|v2i64)(_indexed)?$")>;
719 def : InstRW<[FalkorWr_2VXVY_6cyc], (instregex "^(SQR?SHRN|UQR?SHRN|SQR?SHRUN)(v8i8|v16i8|v4i16|v…
722 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^ADD(v16i8|v8i16|v4i32|v2i64)$")>;
724 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v16i8$")>;
726 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(NEG|SUB)(v16i8|v8i16|v4i32|v2i64)$")>;
729 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v16i8|v2i64|v4i32|v8i…
730 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SHLL(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)(_s…
731 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SHR(v16i8|v8i16|v4i32|v2i64)_shift$")>;
733 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^((S|U)?(MAX|MIN)P?|ABS)(v16i8|v2i64|v4i32|v8i16)…
734 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^ADDP(v4i32|v8i16|v16i8)$")>; // sz!=11
[all …]
DAArch64SchedKryoDetails.td26 (instregex "(S|U)R?SRA(v2i64|v4i32|v8i16|v16i8)_shift")>;
39 (instregex "(S|U)ABA(v16i8|v8i16|v4i32)")>;
51 (instregex "(S|U)(ABD|QSUB|RHADD)(v16i8|v8i16|v4i32|v2i64)")>;
75 (instregex "(S|U)ADALP(v16i8|v8i16|v4i32)_v.*")>;
93 (instregex "((S|U)ADDLP|ABS)(v2i64|v4i32|v8i16|v16i8)(_v.*)?")>;
165 (instregex "(S|U)H(ADD|SUB)(v16i8|v8i16|v4i32)")>;
207 (instregex "^(S|U)QADD(v16i8|v8i16|v4i32|v2i64)")>;
225 (instregex "(S|U)(QSHLU?|RSHR)(v16i8|v8i16|v4i32|v2i64)_shift$")>;
237 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v16i8|v8i16|v4i32|v2i64)$")>;
243 (instregex "((S|U)QR?SHRN|SQR?SHRUN)(v16i8|v8i16|v4i32)_shift$")>;
[all …]
DAArch64InstrInfo.td915 def v16i8 : BaseSIMDSUDOTIndex<1, ".4s", ".16b", ".4b", V128, v4i32, v16i8>;
956 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v16i8>;
961 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v16i8>;
966 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v16i8>;
971 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxs, v16i8>;
2446 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
2511 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
2605 def : Pat <(v16i8 (scalar_to_vector (i32
2607 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
2661 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
[all …]
DAArch64TargetTransformInfo.cpp233 static const auto ValidMinMaxTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
244 static const auto ValidSatTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
257 static const auto ValidAbsTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
283 {Intrinsic::bitreverse, MVT::v16i8, 1}, in getIntrinsicInstrCost()
308 {ISD::CTPOP, MVT::v16i8, 1}, in getIntrinsicInstrCost()
952 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
985 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
986 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
987 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
988 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
[all …]
DAArch64ISelDAGToDAG.cpp3602 } else if (VT == MVT::v16i8) { in Select()
3629 } else if (VT == MVT::v16i8) { in Select()
3656 } else if (VT == MVT::v16i8) { in Select()
3683 } else if (VT == MVT::v16i8) { in Select()
3710 } else if (VT == MVT::v16i8) { in Select()
3737 } else if (VT == MVT::v16i8) { in Select()
3764 } else if (VT == MVT::v16i8) { in Select()
3791 } else if (VT == MVT::v16i8) { in Select()
3818 } else if (VT == MVT::v16i8) { in Select()
3842 if (VT == MVT::v16i8 || VT == MVT::v8i8) { in Select()
[all …]
DAArch64SchedA57.td348 // Q form - v16i8, v8i16, v4i32
350 // Q form - v16i8, v8i16, v4i32, v2i64
361 def : InstRW<[A57Write_5cyc_2X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABA(v16i8|v8i16|v4i32…
387 def : InstRW<[A57Write_6cyc_2W_Mul_Forward], (instregex "^MUL(v16i8|v8i16|v4i32)(_indexed)?$")>;
389 def : InstRW<[A57Write_6cyc_2W], (instregex "^(PMUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>;
398 def : InstRW<[A57Write_6cyc_2W_Mul_Forward, A57ReadIVMA4], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_…
408 def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>;
422 def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
428 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>;
519 // Q form - v16i8, v8i16, v4i32
[all …]
DAArch64CallingConvention.td35 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
115 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
123 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
140 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
159 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
241 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
257 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
278 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
300 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
361 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, f128], CCBitConvertToType<v2f64>>,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZCallingConv.td60 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
80 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
124 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
131 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
136 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
199 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
246 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
249 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
275 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
284 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
DSystemZInstrVector.td49 def : VectorExtractSubreg<v16i8, VLGVB>;
201 defm : ReplicatePeephole<VLREPB, v16i8, anyextloadi8, i32>;
280 def : Pat<(v16i8 (z_loadeswap bdxaddr12only:$addr)),
321 def : Pat<(z_storeeswap (v16i8 VR128:$val), bdxaddr12only:$addr),
416 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>;
462 defm : GenericVectorOps<v16i8, v16i8>;
725 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>;
897 defm : BitwiseVectorOps<v16i8>;
933 defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>;
958 defm : IntegerMinMaxVectorOps<v16i8, z_vicmph, VMNB, VMXB>;
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td92 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
101 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
162 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
166 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
170 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
174 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
178 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
184 (v16i8 (build_vector node:$e0, node:$e0,
251 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
255 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
DWebAssemblyTypeUtilities.cpp72 .Case("v16i8", MVT::v16i8) in parseMVT()
141 case MVT::v16i8: in toValType()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp63 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
84 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
145 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
179 for (auto T : {MVT::v16i8, MVT::v8i16}) in WebAssemblyTargetLowering()
183 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
187 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
192 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
198 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
203 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
208 setOperationAction(ISD::MUL, MVT::v16i8, Expand); in WebAssemblyTargetLowering()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h80 v16i8 = 30, // 16 x i8 enumerator
408 return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8 || in is128BitVector()
545 case v16i8: in getVectorElementType()
743 case v16i8: in getVectorMinNumElements()
950 case v16i8: in getSizeInBits()
1199 if (NumElements == 16) return MVT::v16i8; in getVectorVT()

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