| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 122 v16i64 = 69, // 16 x i64 enumerator
437 SimpleTy == MVT::v16i64 || SimpleTy == MVT::v64f16 || in is1024BitVector()
603 case v16i64: in getVectorElementType()
746 case v16i64: in getVectorMinNumElements()
1012 case v16i64: in getSizeInBits()
1244 if (NumElements == 16) return MVT::v16i64; in getVectorVT()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 749 defm "" : SRegClass<32, 21, [v32i32, v32f32, v16i64, v16f64], SGPR_1024Regs>;
787 defm VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>;
808 defm AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)>;
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| D | AMDGPUISelLowering.cpp | 126 setOperationAction(ISD::LOAD, MVT::v16i64, Promote); in AMDGPUTargetLowering()
127 AddPromotedToType(ISD::LOAD, MVT::v16i64, MVT::v32i32); in AMDGPUTargetLowering()
260 setOperationAction(ISD::STORE, MVT::v16i64, Promote); in AMDGPUTargetLowering()
261 AddPromotedToType(ISD::STORE, MVT::v16i64, MVT::v32i32); in AMDGPUTargetLowering()
305 setTruncStoreAction(MVT::v16i64, MVT::v16i16, Expand); in AMDGPUTargetLowering()
306 setTruncStoreAction(MVT::v16i64, MVT::v16i16, Expand); in AMDGPUTargetLowering()
307 setTruncStoreAction(MVT::v16i64, MVT::v16i8, Expand); in AMDGPUTargetLowering()
308 setTruncStoreAction(MVT::v16i64, MVT::v16i8, Expand); in AMDGPUTargetLowering()
309 setTruncStoreAction(MVT::v16i64, MVT::v16i1, Expand); in AMDGPUTargetLowering()
394 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i64, Custom); in AMDGPUTargetLowering()
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| D | SIInstructions.td | 1327 def : BitConvert <v16i64, v16f64, VReg_1024>;
1328 def : BitConvert <v16f64, v16i64, VReg_1024>;
1329 def : BitConvert <v16i64, v32i32, VReg_1024>;
1330 def : BitConvert <v32i32, v16i64, VReg_1024>;
1333 def : BitConvert <v16i64, v32f32, VReg_1024>;
1336 def : BitConvert <v32f32, v16i64, VReg_1024>;
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| D | SIISelLowering.cpp | 126 addRegisterClass(MVT::v16i64, &AMDGPU::SGPR_1024RegClass); in SITargetLowering()
198 setTruncStoreAction(MVT::v16i64, MVT::v16i32, Expand); in SITargetLowering()
273 MVT::v16i64, MVT::v16f64, MVT::v32i32, MVT::v32f32 }) { in SITargetLowering()
359 for (MVT Vec64 : { MVT::v16i64, MVT::v16f64 }) { in SITargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 95 def v16i64 : ValueType<1024, 69>; // 16 x i64 vector value
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | ValueTypes.cpp | 315 case MVT::v16i64: in getTypeForEVT()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 137 case MVT::v16i64: return "MVT::v16i64"; in getEnumName()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 114 case MVT::v16i64: in SelectIndexedLoad()
504 case MVT::v16i64: in SelectIndexedStore()
|
| D | HexagonInstrInfo.cpp | 2695 case MVT::v16i64: in isValidAutoIncImm()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 1469 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost } in getCmpSelInstrCost()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 924 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 } in getCmpSelInstrCost()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 307 def llvm_v16i64_ty : LLVMType<v16i64>; // 16 x i64
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 1616 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb in getCastInstrCost()
1965 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, in getCastInstrCost()
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| D | X86ISelLowering.cpp | 1594 setOperationAction(ISD::TRUNCATE, MVT::v16i64, Custom); in X86TargetLowering()
1926 setOperationAction(ISD::TRUNCATE, MVT::v16i64, Custom); in X86TargetLowering()
21149 if ((InVT == MVT::v8i64 || InVT == MVT::v16i32 || InVT == MVT::v16i64) && in LowerTRUNCATE()
21151 assert((InVT == MVT::v16i64 || Subtarget.hasVLX()) && in LowerTRUNCATE()
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