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Searched refs:uart_setreg (Results 1 – 16 of 16) sorted by relevance

/freebsd-12-stable/sys/dev/uart/
Duart_dev_sab82532.c112 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES); in sab82532_flush()
118 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES); in sab82532_flush()
154 uart_setreg(bas, SAB_BGR, divisor & 0xff); in sab82532_param()
157 uart_setreg(bas, SAB_TCR, divisor & 0xff); in sab82532_param()
162 uart_setreg(bas, SAB_CCR2, ccr2); in sab82532_param()
166 uart_setreg(bas, SAB_DAFO, dafo); in sab82532_param()
211 uart_setreg(bas, SAB_PCR, in sab82532_init()
215 uart_setreg(bas, SAB_PIM, 0xff); in sab82532_init()
218 uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL); in sab82532_init()
230 uart_setreg(bas, SAB_PVR, pvr | SAB_PVR_MAGIC); in sab82532_init()
[all …]
Duart_dev_ns8250.c114 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); in ns8250_delay()
118 uart_setreg(bas, REG_LCR, lcr); in ns8250_delay()
214 uart_setreg(bas, REG_FCR, fcr); in ns8250_flush()
243 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); in ns8250_param()
245 uart_setreg(bas, REG_DLL, divisor & 0xff); in ns8250_param()
246 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); in ns8250_param()
251 uart_setreg(bas, REG_LCR, lcr); in ns8250_param()
281 uart_setreg(bas, REG_FCR, FCR_UART_ON); in ns8250_probe()
318 uart_setreg(bas, REG_IER, ier); in ns8250_init()
326 uart_setreg(bas, REG_FCR, val); in ns8250_init()
[all …]
Duart_dev_mvebu.c184 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST | in uart_mvebu_param()
214 uart_setreg(bas, UART_CCR, ccr | divisor); in uart_mvebu_param()
222 uart_setreg(bas, UART_CTRL, ctrl); in uart_mvebu_param()
236 uart_setreg(bas, UART_CTRL, uart_getreg(bas, UART_CTRL) & in uart_mvebu_init()
248 uart_setreg(bas, UART_TSH, c & 0xff); in uart_mvebu_putc()
346 uart_setreg(bas, UART_CTRL, ctrl); in uart_mvebu_bus_attach()
373 uart_setreg(bas, UART_CTRL, ctrl | CTRL_RX_FIFO_RST); in uart_mvebu_bus_flush()
378 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST); in uart_mvebu_bus_flush()
389 uart_setreg(bas, UART_CTRL, ctrl); in uart_mvebu_bus_flush()
420 uart_setreg(bas, UART_CTRL, ctrl); in uart_mvebu_bus_ioctl()
[all …]
Duart_dev_msm.c123 uart_setreg(bas, UART_DM_MR2, ulcon); in msm_uart_param()
164 uart_setreg(bas, UART_DM_MR1, 0x0); in msm_init()
167 uart_setreg(bas, UART_DM_IMR, 0); in msm_init()
174 uart_setreg(bas, UART_DM_TFWR, UART_DM_TFW_VALUE); in msm_init()
177 uart_setreg(bas, UART_DM_RFWR, UART_DM_RFW_VALUE); in msm_init()
183 uart_setreg(bas, UART_DM_IPR, UART_DM_STALE_TIMEOUT_LSB); in msm_init()
186 uart_setreg(bas, UART_DM_IRDA, 0x0); in msm_init()
193 uart_setreg(bas, UART_DM_HCR, 0x0); in msm_init()
203 uart_setreg(bas, UART_DM_DMEN, UART_DM_DMEN_RX_SC_ENABLE); in msm_init()
206 uart_setreg(bas, UART_DM_CR, UART_DM_CR_RX_ENABLE); in msm_init()
[all …]
Duart_dev_z8530.c60 uart_setreg(bas, REG_CTRL, reg); in uart_setmreg()
62 uart_setreg(bas, REG_CTRL, val); in uart_setmreg()
69 uart_setreg(bas, REG_CTRL, reg); in uart_getmreg()
235 uart_setreg(bas, REG_DATA, c); in z8530_putc()
459 uart_setreg(bas, REG_CTRL, CR_RSTTXI); in z8530_bus_ipend()
468 uart_setreg(bas, REG_CTRL, CR_RSTXSI); in z8530_bus_ipend()
481 uart_setreg(bas, REG_CTRL, CR_RSTERR); in z8530_bus_ipend()
488 uart_setreg(bas, REG_CTRL, CR_RSTIUS); in z8530_bus_ipend()
558 uart_setreg(bas, REG_CTRL, CR_RSTERR); in z8530_bus_receive()
569 uart_setreg(bas, REG_CTRL, CR_RSTERR); in z8530_bus_receive()
[all …]
Duart_dev_ti8250.c94 uart_setreg(&sc->sc_bas, MDR1_REG, MDR1_MODE_DISABLE); in ti8250_bus_probe()
95 uart_setreg(&sc->sc_bas, SYSCC_REG, SYSCC_SOFTRESET); in ti8250_bus_probe()
98 uart_setreg(&sc->sc_bas, MDR1_REG, MDR1_MODE_UART); in ti8250_bus_probe()
Duart.h74 uart_setreg(struct uart_bas *bas, int reg, int value) in uart_setreg() function
/freebsd-12-stable/sys/mips/cavium/
Duart_dev_oct16550.c118 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); in oct16550_delay()
122 uart_setreg(bas, REG_LCR, lcr); in oct16550_delay()
219 uart_setreg(bas, REG_FCR, fcr); in oct16550_flush()
248 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); in oct16550_param()
250 uart_setreg(bas, REG_DLL, divisor & 0xff); in oct16550_param()
251 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); in oct16550_param()
257 uart_setreg(bas, REG_LCR, lcr); in oct16550_param()
309 uart_setreg(bas, REG_IER, ier); in oct16550_init()
317 uart_setreg(bas, REG_MCR, MCR_RTS | MCR_DTR); in oct16550_init()
328 uart_setreg(bas, REG_MCR, 0); in oct16550_term()
[all …]
/freebsd-12-stable/sys/arm/amlogic/aml8726/
Duart_dev_aml8726.c65 #undef uart_setreg
69 #define uart_setreg(bas, reg, value) \ macro
165 uart_setreg(bas, AML_UART_NEW_BAUD_REG, nbr); in aml8726_uart_param()
185 uart_setreg(bas, AML_UART_MISC_REG, mr); in aml8726_uart_param()
188 uart_setreg(bas, AML_UART_CONTROL_REG, cr); in aml8726_uart_param()
221 uart_setreg(bas, AML_UART_CONTROL_REG, cr); in aml8726_uart_init()
227 uart_setreg(bas, AML_UART_MISC_REG, mr); in aml8726_uart_init()
232 uart_setreg(bas, AML_UART_CONTROL_REG, cr); in aml8726_uart_init()
249 uart_setreg(bas, AML_UART_WFIFO_REG, c); in aml8726_uart_putc()
410 uart_setreg(bas, AML_UART_CONTROL_REG, cr); in aml8726_uart_bus_attach()
[all …]
/freebsd-12-stable/sys/arm/freescale/vybrid/
Dvf_uart.c161 uart_setreg(bas, UART_D, c); in vf_uart_putc()
214 uart_setreg(bas, UART_MODEM, 0x00); in uart_reinit()
222 uart_setreg(bas, UART_C2, 0x00); in uart_reinit()
224 uart_setreg(bas, UART_C1, 0x00); in uart_reinit()
232 uart_setreg(bas, UART_BDH, reg); in uart_reinit()
235 uart_setreg(bas, UART_BDL, reg); in uart_reinit()
240 uart_setreg(bas, UART_C4, reg); in uart_reinit()
244 uart_setreg(bas, UART_C2, reg); in uart_reinit()
310 uart_setreg(bas, UART_C2, reg); in vf_uart_bus_attach()
384 uart_setreg(bas, UART_S2, usr2); in vf_uart_bus_ipend()
[all …]
/freebsd-12-stable/sys/mips/mediatek/
Duart_dev_mtk.c126 uart_setreg(bas, UART_CDDL_REG, bas->rclk/16/baudrate); in mtk_uart_init()
130 uart_setreg(bas, UART_LCR_REG, databits | in mtk_uart_init()
139 uart_setreg(bas, UART_MCR_REG, 0); in mtk_uart_term()
150 uart_setreg(bas, UART_TX_REG, c); in mtk_uart_putc()
262 uart_setreg(bas, UART_IER_REG, cr); in mtk_uart_disable_txintr()
277 uart_setreg(bas, UART_IER_REG, cr); in mtk_uart_enable_txintr()
308 uart_setreg(bas, UART_FCR_REG, in mtk_uart_bus_attach()
314 uart_setreg(bas, UART_IER_REG, in mtk_uart_bus_attach()
334 uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_TXRST); in mtk_uart_bus_flush()
338 uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_RXRST); in mtk_uart_bus_flush()
[all …]
Duart_dev_mtk.h37 #undef uart_setreg
40 #define uart_setreg(bas, reg, value) \ macro
/freebsd-12-stable/sys/arm/samsung/exynos/
Dexynos_uart.c122 uart_setreg(bas, SSCOM_ULCON, ulcon); in exynos4210_uart_param()
125 uart_setreg(bas, SSCOM_UBRDIV, brd); in exynos4210_uart_param()
156 uart_setreg(bas, SSCOM_UCON, 0); in exynos4210_init()
157 uart_setreg(bas, SSCOM_UFCON, in exynos4210_init()
164 uart_setreg(bas, SSCOM_UCON, UCON_TXMODE_INT | UCON_RXMODE_INT | in exynos4210_init()
166 uart_setreg(bas, SSCOM_UMCON, UMCON_RTS); in exynos4210_init()
183 uart_setreg(bas, SSCOM_UTXH, c); in exynos4210_putc()
/freebsd-12-stable/sys/arm/nvidia/
Dtegra_uart.c85 uart_setreg(bas, REG_IER, ns8250->ier); in tegra_uart_attach()
104 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); in tegra_uart_grab()
109 uart_setreg(bas, REG_FCR, 0); in tegra_uart_grab()
124 uart_setreg(bas, REG_FCR, ns8250->fcr); in tegra_uart_ungrab()
125 uart_setreg(bas, REG_IER, ns8250->ier); in tegra_uart_ungrab()
/freebsd-12-stable/sys/mips/ingenic/
Djz4780_uart.c81 uart_setreg(bas, REG_IER, ns8250->ier); in jz4780_bus_attach()
/freebsd-12-stable/sys/mips/atheros/
Duart_dev_ar933x.c651 uart_setreg(bas, REG_MCR, ns8250->mcr); in ar933x_bus_setsig()