Searched refs:train_set (Results 1 – 3 of 3) sorted by relevance
300 u8 train_set[4]) in dp_get_adjust_train()332 train_set[lane] = v | p; in dp_get_adjust_train()582 u8 train_set[4]; member593 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()597 dp_info->train_set, dp_info->dp_lane_count, 0); in radeon_dp_update_vs_emph()713 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()736 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()744 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()753 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()756 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr()[all …]
1544 intel_dp->train_set[lane] = v | p; in intel_get_adjust_train()1548 intel_dp_signal_levels(uint8_t train_set) in intel_dp_signal_levels() argument1552 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in intel_dp_signal_levels()1567 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in intel_dp_signal_levels()1587 intel_gen6_edp_signal_levels(uint8_t train_set) in intel_gen6_edp_signal_levels() argument1589 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_gen6_edp_signal_levels()1615 intel_gen7_edp_signal_levels(uint8_t train_set) in intel_gen7_edp_signal_levels() argument1617 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_gen7_edp_signal_levels()1646 intel_dp_signal_levels_hsw(uint8_t train_set) in intel_dp_signal_levels_hsw() argument1648 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_dp_signal_levels_hsw()[all …]
392 uint8_t train_set[4]; member