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Searched refs:subtarget (Results 1 – 25 of 61) sorted by relevance

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/freebsd-12-stable/contrib/gcc/
Dexpmed.c1770 rtx subtarget = (target != 0 && REG_P (target) ? target : 0); in extract_fixed_bit_field() local
1771 if (tmode != mode) subtarget = 0; in extract_fixed_bit_field()
1772 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1); in extract_fixed_bit_field()
1810 rtx subtarget = (target != 0 && REG_P (target) ? target : 0); in extract_fixed_bit_field() local
1811 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1); in extract_fixed_bit_field()
2264 rtx subtarget = target == shifted ? 0 : target; in expand_shift() local
2282 mode, shifted, other_amount, subtarget, 1); in expand_shift()
5109 rtx subtarget; in emit_store_flag() local
5214 subtarget = target; in emit_store_flag()
5226 subtarget = 0; in emit_store_flag()
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Doptabs.c4055 rtx tem, subtarget, comparison, insn; in emit_conditional_move() local
4102 subtarget = target; in emit_conditional_move()
4107 (subtarget, insn_data[icode].operand[0].mode)) in emit_conditional_move()
4108 subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); in emit_conditional_move()
4131 insn = GEN_FCN (icode) (subtarget, comparison, op2, op3); in emit_conditional_move()
4139 if (subtarget != target) in emit_conditional_move()
4140 convert_move (target, subtarget, 0); in emit_conditional_move()
4183 rtx tem, subtarget, comparison, insn; in emit_conditional_add() local
4234 subtarget = gen_reg_rtx (insn_data[icode].operand[0].mode); in emit_conditional_add()
4236 subtarget = target; in emit_conditional_add()
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Dexpr.c5969 rtx subtarget = get_subtarget (target); in force_operand() local
5993 if (!subtarget) in force_operand()
5994 subtarget = gen_reg_rtx (GET_MODE (value)); in force_operand()
5995 emit_move_insn (subtarget, value); in force_operand()
5996 return subtarget; in force_operand()
6002 if (!CONSTANT_P (op2) && !(REG_P (op2) && op2 != subtarget)) in force_operand()
6003 subtarget = 0; in force_operand()
6024 subtarget, 0, OPTAB_LIB_WIDEN); in force_operand()
6031 op1 = force_operand (XEXP (value, 0), subtarget); in force_operand()
6497 rtx result, subtarget; in expand_expr_addr_expr_1() local
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Dbuiltins.c1774 expand_builtin_mathfn (tree exp, rtx target, rtx subtarget) in expand_builtin_mathfn() argument
1865 op0 = expand_expr (arg, subtarget, VOIDmode, 0); in expand_builtin_mathfn()
1945 expand_builtin_mathfn_2 (tree exp, rtx target, rtx subtarget) in expand_builtin_mathfn_2() argument
2020 op0 = expand_expr (arg0, subtarget, VOIDmode, EXPAND_NORMAL); in expand_builtin_mathfn_2()
2058 expand_builtin_mathfn_3 (tree exp, rtx target, rtx subtarget) in expand_builtin_mathfn_3() argument
2114 op0 = expand_expr (arg, subtarget, VOIDmode, 0); in expand_builtin_mathfn_3()
2218 expand_builtin_int_roundingfn (tree exp, rtx target, rtx subtarget) in expand_builtin_int_roundingfn() argument
2271 op0 = expand_expr (arg, subtarget, VOIDmode, 0); in expand_builtin_int_roundingfn()
2521 expand_builtin_pow (tree exp, rtx target, rtx subtarget) in expand_builtin_pow() argument
2553 rtx op = expand_expr (arg0, subtarget, VOIDmode, 0); in expand_builtin_pow()
[all …]
Dtarget.h440 rtx (* expand_builtin) (tree exp, rtx target, rtx subtarget,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZ.td16 // SystemZ subtarget features
22 // SystemZ subtarget scheduling models
DSystemZFeatures.td28 // This feature is added as a subtarget feature whenever the function is
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
DLeonFeatures.td17 //support to casa instruction; for leon3 subtarget only
31 //support to casa instruction; for leon3 subtarget only
DSparc.td65 //==== Features added predmoninantly for LEON subtarget support
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/
DTargetSchedule.td26 // each subtarget, define WriteRes and ReadAdvance to associate
30 // subtarget, define ItinRW entries to map ItineraryClass to
32 // be subtarget specific and can be directly associated with resources
35 // C. In the subtarget, map SchedReadWrite types to specific
38 // subtarget can directly associate resources with SchedReadWrite
41 // D. In either the target or subtarget, define SchedWriteVariant or
92 // and may actually be generated for that subtarget must clear this
273 // defined by the subtarget, and maps the SchedWrite to processor
277 // be used instead to define subtarget specific SchedWrites and map
279 // itinerary classes to the subtarget's SchedWrites.
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DTargetItinerary.td138 // itinerary to be generated in a different automaton. The subtarget will need
DTargetCallingConv.td127 /// is used - these may depend on the target or subtarget.
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DEXPInstructions.td35 class EXP_Real<bit done, string pseudo, int subtarget>
38 SIMCInstr <pseudo, subtarget> {
DAMDGPUCombine.td12 // TODO: GICombineRules should accept subtarget predicates
DR600InstrFormats.td189 XXX: R600 subtarget uses a slightly different encoding than the other
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMSchedule.td11 // Here we define the subtarget independent read/write per-operand resources.
12 // The subtarget schedule definitions will then map these to the subtarget's
40 // Next, the subtarget td file assigns resources to the abstract resources
DARM.td414 // Use the MachineScheduler for instruction scheduling for the subtarget.
581 // ARM Processor subtarget features.
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DRelocation.txt37 to ISel which in turn relies on TableGen patterns to choose subtarget
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedKryo.td124 // subtarget-defined types. As the modeled is refined, this will override most
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td49 // ** output pattern. These are generally guarded by subtarget predicates. **
2496 // Valid for any VSX subtarget, regardless of endianness.
2863 // Any big endian VSX subtarget.
2976 // Any little endian VSX subtarget.
3104 // Any pre-Power9 VSX subtarget.
3134 // Any little endian pre-Power9 VSX subtarget.
3154 // Any VSX subtarget that only has loads and stores that load in big endian
3163 // Big endian VSX subtarget that only has loads and stores that always
3179 // Any Power8 VSX subtarget.
3274 // Any big endian Power8 VSX subtarget.
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DPPCCallingConv.td14 /// CCIfSubtarget - Match if the current subtarget has a feature F.
/freebsd-12-stable/contrib/binutils/
DMakefile.tpl1451 (dep-subtarget var-name)
1462 ;; dep-subtarget extracts everything up to the first dash in the given
1464 (define dep-subtarget (lambda (var-name)
1495 (if (or (= (dep-subtarget "on") "install-")
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86CallingConv.td14 /// CCIfSubtarget - Match if the current subtarget has a feature F.
20 /// CCIfNotSubtarget - Match if the current subtarget doesn't has a feature F.
138 // on the subtarget.
579 // subtarget.
834 // Long doubles get slots whose size depends on the subtarget.
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCV.td12 // RISC-V subtarget features and instruction predicates.
/freebsd-12-stable/contrib/gcc/config/ia64/
Dia64.md4569 rtx subtarget = gen_reg_rtx (DImode);
4571 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
4576 emit_insn (gen_extendsidi2 (subtarget, operands[1]));
4578 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
4580 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
4590 rtx subtarget = gen_reg_rtx (DImode);
4592 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
4597 emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
4599 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
4601 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);

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