1 /*-
2 * Copyright (c) 2017 Broadcom. All rights reserved.
3 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * $FreeBSD: stable/12/sys/dev/ocs_fc/sli4.h 371710 2022-03-07 11:01:34Z ram $
32 */
33
34 /**
35 * @file
36 * Define common SLI-4 structures and function prototypes.
37 */
38
39 #ifndef _SLI4_H
40 #define _SLI4_H
41
42 #include "ocs_os.h"
43
44 #define SLI_PAGE_SIZE (4096)
45 #define SLI_SUB_PAGE_MASK (SLI_PAGE_SIZE - 1)
46 #define SLI_PAGE_SHIFT 12
47 #define SLI_ROUND_PAGE(b) (((b) + SLI_SUB_PAGE_MASK) & ~SLI_SUB_PAGE_MASK)
48
49 #define SLI4_BMBX_TIMEOUT_MSEC 30000
50 #define SLI4_FW_READY_TIMEOUT_MSEC 30000
51
52 static inline uint32_t
sli_page_count(size_t bytes,uint32_t page_size)53 sli_page_count(size_t bytes, uint32_t page_size)
54 {
55 uint32_t mask = page_size - 1;
56 uint32_t shift = 0;
57
58 switch (page_size) {
59 case 4096:
60 shift = 12;
61 break;
62 case 8192:
63 shift = 13;
64 break;
65 case 16384:
66 shift = 14;
67 break;
68 case 32768:
69 shift = 15;
70 break;
71 case 65536:
72 shift = 16;
73 break;
74 default:
75 return 0;
76 }
77
78 return (bytes + mask) >> shift;
79 }
80
81 /*************************************************************************
82 * Common PCI configuration space register definitions
83 */
84
85 #define SLI4_PCI_CLASS_REVISION 0x0008 /** register offset */
86 #define SLI4_PCI_REV_ID_SHIFT 0
87 #define SLI4_PCI_REV_ID_MASK 0xff
88 #define SLI4_PCI_CLASS_SHIFT 8
89 #define SLI4_PCI_CLASS_MASK 0xfff
90
91 #define SLI4_PCI_SOFT_RESET_CSR 0x005c /** register offset */
92 #define SLI4_PCI_SOFT_RESET_MASK 0x0080
93
94 /*************************************************************************
95 * Common SLI-4 register offsets and field definitions
96 */
97
98 /**
99 * @brief SLI_INTF - SLI Interface Definition Register
100 */
101 #define SLI4_INTF_REG 0x0058 /** register offset */
102 #define SLI4_INTF_VALID_SHIFT 29
103 #define SLI4_INTF_VALID_MASK 0x7
104 #define SLI4_INTF_VALID 0x6
105 #define SLI4_INTF_IF_TYPE_SHIFT 12
106 #define SLI4_INTF_IF_TYPE_MASK 0xf
107 #define SLI4_INTF_SLI_FAMILY_SHIFT 8
108 #define SLI4_INTF_SLI_FAMILY_MASK 0xf
109 #define SLI4_INTF_SLI_REVISION_SHIFT 4
110 #define SLI4_INTF_SLI_REVISION_MASK 0xf
111 #define SLI4_FAMILY_CHECK_ASIC_TYPE 0xf
112
113 #define SLI4_IF_TYPE_BE3_SKH_PF 0
114 #define SLI4_IF_TYPE_BE3_SKH_VF 1
115 #define SLI4_IF_TYPE_LANCER_FC_ETH 2
116 #define SLI4_IF_TYPE_LANCER_RDMA 3
117 #define SLI4_IF_TYPE_LANCER_G7 6
118 #define SLI4_MAX_IF_TYPES 7
119
120 /**
121 * @brief ASIC_ID - SLI ASIC Type and Revision Register
122 */
123 #define SLI4_ASIC_ID_REG 0x009c /* register offset */
124 #define SLI4_ASIC_REV_SHIFT 0
125 #define SLI4_ASIC_REV_MASK 0xf
126 #define SLI4_ASIC_VER_SHIFT 4
127 #define SLI4_ASIC_VER_MASK 0xf
128 #define SLI4_ASIC_GEN_SHIFT 8
129 #define SLI4_ASIC_GEN_MASK 0xff
130 #define SLI4_ASIC_GEN_BE2 0x00
131 #define SLI4_ASIC_GEN_BE3 0x03
132 #define SLI4_ASIC_GEN_SKYHAWK 0x04
133 #define SLI4_ASIC_GEN_CORSAIR 0x05
134 #define SLI4_ASIC_GEN_LANCER 0x0b
135
136
137 /**
138 * @brief BMBX - Bootstrap Mailbox Register
139 */
140 #define SLI4_BMBX_REG 0x0160 /* register offset */
141 #define SLI4_BMBX_MASK_HI 0x3
142 #define SLI4_BMBX_MASK_LO 0xf
143 #define SLI4_BMBX_RDY BIT(0)
144 #define SLI4_BMBX_HI BIT(1)
145 #define SLI4_BMBX_WRITE_HI(r) ((ocs_addr32_hi(r) & ~SLI4_BMBX_MASK_HI) | \
146 SLI4_BMBX_HI)
147 #define SLI4_BMBX_WRITE_LO(r) (((ocs_addr32_hi(r) & SLI4_BMBX_MASK_HI) << 30) | \
148 (((r) & ~SLI4_BMBX_MASK_LO) >> 2))
149
150 #define SLI4_BMBX_SIZE 256
151
152
153 /**
154 * @brief EQCQ_DOORBELL - EQ and CQ Doorbell Register
155 */
156 #define SLI4_EQCQ_DOORBELL_REG 0x120
157 #define SLI4_EQCQ_DOORBELL_CI BIT(9)
158 #define SLI4_EQCQ_DOORBELL_QT BIT(10)
159 #define SLI4_EQCQ_DOORBELL_ARM BIT(29)
160 #define SLI4_EQCQ_DOORBELL_SE BIT(31)
161 #define SLI4_EQCQ_NUM_SHIFT 16
162 #define SLI4_EQCQ_NUM_MASK 0x01ff
163 #define SLI4_EQCQ_EQ_ID_MASK 0x3fff
164 #define SLI4_EQCQ_CQ_ID_MASK 0x7fff
165 #define SLI4_EQCQ_EQ_ID_MASK_LO 0x01ff
166 #define SLI4_EQCQ_CQ_ID_MASK_LO 0x03ff
167 #define SLI4_EQCQ_EQCQ_ID_MASK_HI 0xf800
168 #define SLI4_IF6_EQ_DOORBELL_REG 0x120
169 #define SLI4_IF6_CQ_DOORBELL_REG 0xC0
170
171 /**
172 * @brief SLIPORT_CONTROL - SLI Port Control Register
173 */
174 #define SLI4_SLIPORT_CONTROL_REG 0x0408
175 #define SLI4_SLIPORT_CONTROL_END BIT(30)
176 #define SLI4_SLIPORT_CONTROL_LITTLE_ENDIAN (0)
177 #define SLI4_SLIPORT_CONTROL_BIG_ENDIAN BIT(30)
178 #define SLI4_SLIPORT_CONTROL_IP BIT(27)
179 #define SLI4_SLIPORT_CONTROL_IDIS BIT(22)
180 #define SLI4_SLIPORT_CONTROL_FDD BIT(31)
181
182 /**
183 * @brief SLI4_SLIPORT_ERROR1 - SLI Port Error Register
184 */
185 #define SLI4_SLIPORT_ERROR1 0x040c
186
187 /**
188 * @brief SLI4_SLIPORT_ERROR2 - SLI Port Error Register
189 */
190 #define SLI4_SLIPORT_ERROR2 0x0410
191
192 /**
193 * @brief User error registers
194 */
195 #define SLI4_UERR_STATUS_LOW_REG 0xA0
196 #define SLI4_UERR_STATUS_HIGH_REG 0xA4
197 #define SLI4_UERR_MASK_LOW_REG 0xA8
198 #define SLI4_UERR_MASK_HIGH_REG 0xAC
199
200 /**
201 * @brief Registers for generating software UE (BE3)
202 */
203 #define SLI4_SW_UE_CSR1 0x138
204 #define SLI4_SW_UE_CSR2 0x1FFFC
205
206 /**
207 * @brief Registers for generating software UE (Skyhawk)
208 */
209 #define SLI4_SW_UE_REG 0x5C /* register offset */
210
sli_eq_doorbell(uint16_t n_popped,uint16_t id,uint8_t arm)211 static inline uint32_t sli_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
212 {
213 uint32_t reg = 0;
214 #if BYTE_ORDER == LITTLE_ENDIAN
215 struct {
216 uint32_t eq_id_lo:9,
217 ci:1, /* clear interrupt */
218 qt:1, /* queue type */
219 eq_id_hi:5,
220 number_popped:13,
221 arm:1,
222 :1,
223 se:1;
224 } * eq_doorbell = (void *)®
225 #else
226 #error big endian version not defined
227 #endif
228
229 eq_doorbell->eq_id_lo = id & SLI4_EQCQ_EQ_ID_MASK_LO;
230 eq_doorbell->qt = 1; /* EQ is type 1 (section 2.2.3.3 SLI Arch) */
231 eq_doorbell->eq_id_hi = (id >> 9) & 0x1f;
232 eq_doorbell->number_popped = n_popped;
233 eq_doorbell->arm = arm;
234 eq_doorbell->ci = TRUE;
235
236 return reg;
237 }
238
sli_cq_doorbell(uint16_t n_popped,uint16_t id,uint8_t arm)239 static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
240 {
241 uint32_t reg = 0;
242 #if BYTE_ORDER == LITTLE_ENDIAN
243 struct {
244 uint32_t cq_id_lo:10,
245 qt:1, /* queue type */
246 cq_id_hi:5,
247 number_popped:13,
248 arm:1,
249 :1,
250 se:1;
251 } * cq_doorbell = (void *)®
252 #else
253 #error big endian version not defined
254 #endif
255
256 cq_doorbell->cq_id_lo = id & SLI4_EQCQ_CQ_ID_MASK_LO;
257 cq_doorbell->qt = 0; /* CQ is type 0 (section 2.2.3.3 SLI Arch) */
258 cq_doorbell->cq_id_hi = (id >> 10) & 0x1f;
259 cq_doorbell->number_popped = n_popped;
260 cq_doorbell->arm = arm;
261
262 return reg;
263 }
264
sli_iftype6_eq_doorbell(uint16_t n_popped,uint16_t id,uint8_t arm)265 static inline uint32_t sli_iftype6_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
266 {
267 uint32_t reg = 0;
268 #if BYTE_ORDER == LITTLE_ENDIAN
269 struct {
270 uint32_t eq_id:12,
271 :4, /* clear interrupt */
272 number_popped:13,
273 arm:1,
274 :1,
275 io:1;
276 } * eq_doorbell = (void *)®
277 #else
278 #error big endian version not defined
279 #endif
280
281 eq_doorbell->eq_id = id;
282 eq_doorbell->number_popped = n_popped;
283 eq_doorbell->arm = arm;
284
285 return reg;
286 }
287
sli_iftype6_cq_doorbell(uint16_t n_popped,uint16_t id,uint8_t arm)288 static inline uint32_t sli_iftype6_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm)
289 {
290 uint32_t reg = 0;
291 #if BYTE_ORDER == LITTLE_ENDIAN
292 struct {
293 uint32_t cq_id:16,
294 number_popped:13,
295 arm:1,
296 :1,
297 se:1;
298 } * cq_doorbell = (void *)®
299 #else
300 #error big endian version not defined
301 #endif
302
303 cq_doorbell->cq_id = id;
304 cq_doorbell->number_popped = n_popped;
305 cq_doorbell->arm = arm;
306
307 return reg;
308 }
309
310 /**
311 * @brief MQ_DOORBELL - MQ Doorbell Register
312 */
313 #define SLI4_MQ_DOORBELL_REG 0x0140 /* register offset */
314 #define SLI4_IF6_MQ_DOORBELL_REG 0x0160 /* register offset if_type = 6 */
315 #define SLI4_MQ_DOORBELL_NUM_SHIFT 16
316 #define SLI4_MQ_DOORBELL_NUM_MASK 0x3fff
317 #define SLI4_MQ_DOORBELL_ID_MASK 0xffff
318 #define SLI4_MQ_DOORBELL(n, i) ((((n) & SLI4_MQ_DOORBELL_NUM_MASK) << SLI4_MQ_DOORBELL_NUM_SHIFT) | \
319 ((i) & SLI4_MQ_DOORBELL_ID_MASK))
320
321 /**
322 * @brief RQ_DOORBELL - RQ Doorbell Register
323 */
324 #define SLI4_RQ_DOORBELL_REG 0x0a0 /* register offset */
325 #define SLI4_IF6_RQ_DOORBELL_REG 0x0080 /* register offset of if_type = 6 */
326 #define SLI4_RQ_DOORBELL_NUM_SHIFT 16
327 #define SLI4_RQ_DOORBELL_NUM_MASK 0x3fff
328 #define SLI4_RQ_DOORBELL_ID_MASK 0xffff
329 #define SLI4_RQ_DOORBELL(n, i) ((((n) & SLI4_RQ_DOORBELL_NUM_MASK) << SLI4_RQ_DOORBELL_NUM_SHIFT) | \
330 ((i) & SLI4_RQ_DOORBELL_ID_MASK))
331
332 /**
333 * @brief WQ_DOORBELL - WQ Doorbell Register
334 */
335 #define SLI4_IO_WQ_DOORBELL_REG 0x040 /* register offset */
336 #define SLI4_IF6_WQ_DOORBELL_REG 0x040 /* register offset for if_type = 6 */
337 #define SLI4_WQ_DOORBELL_IDX_SHIFT 16
338 #define SLI4_WQ_DOORBELL_IDX_MASK 0x00ff
339 #define SLI4_WQ_DOORBELL_NUM_SHIFT 24
340 #define SLI4_WQ_DOORBELL_NUM_MASK 0x00ff
341 #define SLI4_WQ_DOORBELL_ID_MASK 0xffff
342 #define SLI4_WQ_DOORBELL(n, x, i) ((((n) & SLI4_WQ_DOORBELL_NUM_MASK) << SLI4_WQ_DOORBELL_NUM_SHIFT) | \
343 (((x) & SLI4_WQ_DOORBELL_IDX_MASK) << SLI4_WQ_DOORBELL_IDX_SHIFT) | \
344 ((i) & SLI4_WQ_DOORBELL_ID_MASK))
345
346 /**
347 * @brief SLIPORT_SEMAPHORE - SLI Port Host and Port Status Register
348 */
349 #define SLI4_PORT_SEMAPHORE_REG_0 0x00ac /** register offset Interface Type 0 + 1 */
350 #define SLI4_PORT_SEMAPHORE_REG_1 0x0180 /** register offset Interface Type 0 + 1 */
351 #define SLI4_PORT_SEMAPHORE_REG_236 0x0400 /** register offset Interface Type 2 + 3 + 6*/
352 #define SLI4_PORT_SEMAPHORE_PORT_MASK 0x0000ffff
353 #define SLI4_PORT_SEMAPHORE_PORT(r) ((r) & SLI4_PORT_SEMAPHORE_PORT_MASK)
354 #define SLI4_PORT_SEMAPHORE_HOST_MASK 0x00ff0000
355 #define SLI4_PORT_SEMAPHORE_HOST_SHIFT 16
356 #define SLI4_PORT_SEMAPHORE_HOST(r) (((r) & SLI4_PORT_SEMAPHORE_HOST_MASK) >> \
357 SLI4_PORT_SEMAPHORE_HOST_SHIFT)
358 #define SLI4_PORT_SEMAPHORE_SCR2 BIT(26) /** scratch area 2 */
359 #define SLI4_PORT_SEMAPHORE_SCR1 BIT(27) /** scratch area 1 */
360 #define SLI4_PORT_SEMAPHORE_IPC BIT(28) /** IP conflict */
361 #define SLI4_PORT_SEMAPHORE_NIP BIT(29) /** no IP address */
362 #define SLI4_PORT_SEMAPHORE_SFI BIT(30) /** secondary firmware image used */
363 #define SLI4_PORT_SEMAPHORE_PERR BIT(31) /** POST fatal error */
364
365 #define SLI4_PORT_SEMAPHORE_STATUS_POST_READY 0xc000
366 #define SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR 0xf000
367 #define SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK 0xf000
368 #define SLI4_PORT_SEMAPHORE_IN_ERR(r) (SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR == ((r) & \
369 SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK))
370
371 /**
372 * @brief SLIPORT_STATUS - SLI Port Status Register
373 */
374
375 #define SLI4_PORT_STATUS_REG_236 0x0404 /** register offset Interface Type 2 + 3 + 6*/
376 #define SLI4_PORT_STATUS_FDP BIT(21) /** function specific dump present */
377 #define SLI4_PORT_STATUS_RDY BIT(23) /** ready */
378 #define SLI4_PORT_STATUS_RN BIT(24) /** reset needed */
379 #define SLI4_PORT_STATUS_DIP BIT(25) /** dump present */
380 #define SLI4_PORT_STATUS_OTI BIT(29) /** over temp indicator */
381 #define SLI4_PORT_STATUS_END BIT(30) /** endianness */
382 #define SLI4_PORT_STATUS_ERR BIT(31) /** SLI port error */
383 #define SLI4_PORT_STATUS_READY(r) ((r) & SLI4_PORT_STATUS_RDY)
384 #define SLI4_PORT_STATUS_ERROR(r) ((r) & SLI4_PORT_STATUS_ERR)
385 #define SLI4_PORT_STATUS_DUMP_PRESENT(r) ((r) & SLI4_PORT_STATUS_DIP)
386 #define SLI4_PORT_STATUS_FDP_PRESENT(r) ((r) & SLI4_PORT_STATUS_FDP)
387
388 #define SLI4_PHSDEV_CONTROL_REG_236 0x0414 /** register offset Interface Type 2 + 3 + 6*/
389 #define SLI4_PHYDEV_CONTROL_DRST BIT(0) /** physical device reset */
390 #define SLI4_PHYDEV_CONTROL_FRST BIT(1) /** firmware reset */
391 #define SLI4_PHYDEV_CONTROL_DD BIT(2) /** diagnostic dump */
392 #define SLI4_PHYDEV_CONTROL_FRL_MASK 0x000000f0
393 #define SLI4_PHYDEV_CONTROL_FRL_SHIFT 4
394 #define SLI4_PHYDEV_CONTROL_FRL(r) (((r) & SLI4_PHYDEV_CONTROL_FRL_MASK) >> \
395 SLI4_PHYDEV_CONTROL_FRL_SHIFT_SHIFT)
396
397 /*************************************************************************
398 * SLI-4 mailbox command formats and definitions
399 */
400
401 typedef struct sli4_mbox_command_header_s {
402 #if BYTE_ORDER == LITTLE_ENDIAN
403 uint32_t :8,
404 command:8,
405 status:16; /** Port writes to indicate success / fail */
406 #else
407 #error big endian version not defined
408 #endif
409 } sli4_mbox_command_header_t;
410
411 #define SLI4_MBOX_COMMAND_CONFIG_LINK 0x07
412 #define SLI4_MBOX_COMMAND_DUMP 0x17
413 #define SLI4_MBOX_COMMAND_DOWN_LINK 0x06
414 #define SLI4_MBOX_COMMAND_INIT_LINK 0x05
415 #define SLI4_MBOX_COMMAND_INIT_VFI 0xa3
416 #define SLI4_MBOX_COMMAND_INIT_VPI 0xa4
417 #define SLI4_MBOX_COMMAND_POST_XRI 0xa7
418 #define SLI4_MBOX_COMMAND_RELEASE_XRI 0xac
419 #define SLI4_MBOX_COMMAND_READ_CONFIG 0x0b
420 #define SLI4_MBOX_COMMAND_READ_STATUS 0x0e
421 #define SLI4_MBOX_COMMAND_READ_NVPARMS 0x02
422 #define SLI4_MBOX_COMMAND_READ_REV 0x11
423 #define SLI4_MBOX_COMMAND_READ_LNK_STAT 0x12
424 #define SLI4_MBOX_COMMAND_READ_SPARM64 0x8d
425 #define SLI4_MBOX_COMMAND_READ_TOPOLOGY 0x95
426 #define SLI4_MBOX_COMMAND_REG_FCFI 0xa0
427 #define SLI4_MBOX_COMMAND_REG_FCFI_MRQ 0xaf
428 #define SLI4_MBOX_COMMAND_REG_RPI 0x93
429 #define SLI4_MBOX_COMMAND_REG_RX_RQ 0xa6
430 #define SLI4_MBOX_COMMAND_REG_VFI 0x9f
431 #define SLI4_MBOX_COMMAND_REG_VPI 0x96
432 #define SLI4_MBOX_COMMAND_REQUEST_FEATURES 0x9d
433 #define SLI4_MBOX_COMMAND_SLI_CONFIG 0x9b
434 #define SLI4_MBOX_COMMAND_UNREG_FCFI 0xa2
435 #define SLI4_MBOX_COMMAND_UNREG_RPI 0x14
436 #define SLI4_MBOX_COMMAND_UNREG_VFI 0xa1
437 #define SLI4_MBOX_COMMAND_UNREG_VPI 0x97
438 #define SLI4_MBOX_COMMAND_WRITE_NVPARMS 0x03
439 #define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY 0xAD
440 #define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY_HP 0xAE
441
442 #define SLI4_MBOX_STATUS_SUCCESS 0x0000
443 #define SLI4_MBOX_STATUS_FAILURE 0x0001
444 #define SLI4_MBOX_STATUS_RPI_NOT_REG 0x1400
445
446 /**
447 * @brief Buffer Descriptor Entry (BDE)
448 */
449 typedef struct sli4_bde_s {
450 #if BYTE_ORDER == LITTLE_ENDIAN
451 uint32_t buffer_length:24,
452 bde_type:8;
453 union {
454 struct {
455 uint32_t buffer_address_low;
456 uint32_t buffer_address_high;
457 } data;
458 struct {
459 uint32_t offset;
460 uint32_t rsvd2;
461 } imm;
462 struct {
463 uint32_t sgl_segment_address_low;
464 uint32_t sgl_segment_address_high;
465 } blp;
466 } u;
467 #else
468 #error big endian version not defined
469 #endif
470 } sli4_bde_t;
471
472 #define SLI4_BDE_TYPE_BDE_64 0x00 /** Generic 64-bit data */
473 #define SLI4_BDE_TYPE_BDE_IMM 0x01 /** Immediate data */
474 #define SLI4_BDE_TYPE_BLP 0x40 /** Buffer List Pointer */
475
476 /**
477 * @brief Scatter-Gather Entry (SGE)
478 */
479 typedef struct sli4_sge_s {
480 #if BYTE_ORDER == LITTLE_ENDIAN
481 uint32_t buffer_address_high;
482 uint32_t buffer_address_low;
483 uint32_t data_offset:27,
484 sge_type:4,
485 last:1;
486 uint32_t buffer_length;
487 #else
488 #error big endian version not defined
489 #endif
490 } sli4_sge_t;
491
492 /**
493 * @brief T10 DIF Scatter-Gather Entry (SGE)
494 */
495 typedef struct sli4_dif_sge_s {
496 #if BYTE_ORDER == LITTLE_ENDIAN
497 uint32_t buffer_address_high;
498 uint32_t buffer_address_low;
499 uint32_t :27,
500 sge_type:4,
501 last:1;
502 uint32_t :32;
503 #else
504 #error big endian version not defined
505 #endif
506 } sli4_dif_sge_t;
507
508 /**
509 * @brief T10 DIF Seed Scatter-Gather Entry (SGE)
510 */
511 typedef struct sli4_diseed_sge_s {
512 #if BYTE_ORDER == LITTLE_ENDIAN
513 uint32_t ref_tag_cmp;
514 uint32_t ref_tag_repl;
515 uint32_t app_tag_repl:16,
516 :2,
517 hs:1,
518 ws:1,
519 ic:1,
520 ics:1,
521 atrt:1,
522 at:1,
523 fwd_app_tag:1,
524 repl_app_tag:1,
525 head_insert:1,
526 sge_type:4,
527 last:1;
528 uint32_t app_tag_cmp:16,
529 dif_blk_size:3,
530 auto_incr_ref_tag:1,
531 check_app_tag:1,
532 check_ref_tag:1,
533 check_crc:1,
534 new_ref_tag:1,
535 dif_op_rx:4,
536 dif_op_tx:4;
537 #else
538 #error big endian version not defined
539 #endif
540 } sli4_diseed_sge_t;
541
542 /**
543 * @brief List Segment Pointer Scatter-Gather Entry (SGE)
544 */
545 typedef struct sli4_lsp_sge_s {
546 #if BYTE_ORDER == LITTLE_ENDIAN
547 uint32_t buffer_address_high;
548 uint32_t buffer_address_low;
549 uint32_t :27,
550 sge_type:4,
551 last:1;
552 uint32_t segment_length:24,
553 :8;
554 #else
555 #error big endian version not defined
556 #endif
557 } sli4_lsp_sge_t;
558
559 #define SLI4_SGE_MAX_RESERVED 3
560
561 #define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CRC 0x00
562 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_NODIF 0x01
563 #define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CHKSUM 0x02
564 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_NODIF 0x03
565 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_CRC 0x04
566 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CHKSUM 0x05
567 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_CHKSUM 0x06
568 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CRC 0x07
569 #define SLI4_SGE_DIF_OP_IN_RAW_OUT_RAW 0x08
570
571 #define SLI4_SGE_TYPE_DATA 0x00
572 #define SLI4_SGE_TYPE_CHAIN 0x03 /** Skyhawk only */
573 #define SLI4_SGE_TYPE_DIF 0x04 /** Data Integrity Field */
574 #define SLI4_SGE_TYPE_LSP 0x05 /** List Segment Pointer */
575 #define SLI4_SGE_TYPE_PEDIF 0x06 /** Post Encryption Engine DIF */
576 #define SLI4_SGE_TYPE_PESEED 0x07 /** Post Encryption Engine DIF Seed */
577 #define SLI4_SGE_TYPE_DISEED 0x08 /** DIF Seed */
578 #define SLI4_SGE_TYPE_ENC 0x09 /** Encryption */
579 #define SLI4_SGE_TYPE_ATM 0x0a /** DIF Application Tag Mask */
580 #define SLI4_SGE_TYPE_SKIP 0x0c /** SKIP */
581
582 #define OCS_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */
583
584 /**
585 * @brief CONFIG_LINK
586 */
587 typedef struct sli4_cmd_config_link_s {
588 sli4_mbox_command_header_t hdr;
589 #if BYTE_ORDER == LITTLE_ENDIAN
590 uint32_t maxbbc:8, /** Max buffer-to-buffer credit */
591 :24;
592 uint32_t alpa:8,
593 n_port_id:16,
594 :8;
595 uint32_t rsvd3;
596 uint32_t e_d_tov;
597 uint32_t lp_tov;
598 uint32_t r_a_tov;
599 uint32_t r_t_tov;
600 uint32_t al_tov;
601 uint32_t rsvd9;
602 uint32_t :8,
603 bbscn:4, /** buffer-to-buffer state change number */
604 cscn:1, /** configure BBSCN */
605 :19;
606 #else
607 #error big endian version not defined
608 #endif
609 } sli4_cmd_config_link_t;
610
611 /**
612 * @brief DUMP Type 4
613 */
614 #define SLI4_WKI_TAG_SAT_TEM 0x1040
615 typedef struct sli4_cmd_dump4_s {
616 sli4_mbox_command_header_t hdr;
617 #if BYTE_ORDER == LITTLE_ENDIAN
618 uint32_t type:4,
619 :28;
620 uint32_t wki_selection:16,
621 :16;
622 uint32_t resv;
623 uint32_t returned_byte_cnt;
624 uint32_t resp_data[59];
625 #else
626 #error big endian version not defined
627 #endif
628 } sli4_cmd_dump4_t;
629
630 /**
631 * @brief FW_INITIALIZE - initialize a SLI port
632 *
633 * @note This command uses a different format than all others.
634 */
635
636 extern const uint8_t sli4_fw_initialize[8];
637
638 /**
639 * @brief FW_DEINITIALIZE - deinitialize a SLI port
640 *
641 * @note This command uses a different format than all others.
642 */
643
644 extern const uint8_t sli4_fw_deinitialize[8];
645
646 /**
647 * @brief INIT_LINK - initialize the link for a FC/FCoE port
648 */
649 typedef struct sli4_cmd_init_link_flags_s {
650 uint32_t loopback:1,
651 topology:2,
652 #define FC_TOPOLOGY_FCAL 0
653 #define FC_TOPOLOGY_P2P 1
654 :3,
655 unfair:1,
656 skip_lirp_lilp:1,
657 gen_loop_validity_check:1,
658 skip_lisa:1,
659 enable_topology_failover:1,
660 fixed_speed:1,
661 :3,
662 select_hightest_al_pa:1,
663 :16; /* pad to 32 bits */
664 } sli4_cmd_init_link_flags_t;
665
666 #define SLI4_INIT_LINK_F_LOOP_BACK BIT(0)
667 #define SLI4_INIT_LINK_F_UNFAIR BIT(6)
668 #define SLI4_INIT_LINK_F_NO_LIRP BIT(7)
669 #define SLI4_INIT_LINK_F_LOOP_VALID_CHK BIT(8)
670 #define SLI4_INIT_LINK_F_NO_LISA BIT(9)
671 #define SLI4_INIT_LINK_F_FAIL_OVER BIT(10)
672 #define SLI4_INIT_LINK_F_NO_AUTOSPEED BIT(11)
673 #define SLI4_INIT_LINK_F_PICK_HI_ALPA BIT(15)
674
675 #define SLI4_INIT_LINK_F_P2P_ONLY 1
676 #define SLI4_INIT_LINK_F_FCAL_ONLY 2
677
678 #define SLI4_INIT_LINK_F_FCAL_FAIL_OVER 0
679 #define SLI4_INIT_LINK_F_P2P_FAIL_OVER 1
680
681 typedef struct sli4_cmd_init_link_s {
682 sli4_mbox_command_header_t hdr;
683 #if BYTE_ORDER == LITTLE_ENDIAN
684 uint32_t selective_reset_al_pa:8,
685 :24;
686 sli4_cmd_init_link_flags_t link_flags;
687 uint32_t link_speed_selection_code;
688 #define FC_LINK_SPEED_1G 1
689 #define FC_LINK_SPEED_2G 2
690 #define FC_LINK_SPEED_AUTO_1_2 3
691 #define FC_LINK_SPEED_4G 4
692 #define FC_LINK_SPEED_AUTO_4_1 5
693 #define FC_LINK_SPEED_AUTO_4_2 6
694 #define FC_LINK_SPEED_AUTO_4_2_1 7
695 #define FC_LINK_SPEED_8G 8
696 #define FC_LINK_SPEED_AUTO_8_1 9
697 #define FC_LINK_SPEED_AUTO_8_2 10
698 #define FC_LINK_SPEED_AUTO_8_2_1 11
699 #define FC_LINK_SPEED_AUTO_8_4 12
700 #define FC_LINK_SPEED_AUTO_8_4_1 13
701 #define FC_LINK_SPEED_AUTO_8_4_2 14
702 #define FC_LINK_SPEED_10G 16
703 #define FC_LINK_SPEED_16G 17
704 #define FC_LINK_SPEED_AUTO_16_8_4 18
705 #define FC_LINK_SPEED_AUTO_16_8 19
706 #define FC_LINK_SPEED_32G 20
707 #define FC_LINK_SPEED_AUTO_32_16_8 21
708 #define FC_LINK_SPEED_AUTO_32_16 22
709 #else
710 #error big endian version not defined
711 #endif
712 } sli4_cmd_init_link_t;
713
714 /**
715 * @brief INIT_VFI - initialize the VFI resource
716 */
717 typedef struct sli4_cmd_init_vfi_s {
718 sli4_mbox_command_header_t hdr;
719 #if BYTE_ORDER == LITTLE_ENDIAN
720 uint32_t vfi:16,
721 :12,
722 vp:1,
723 vf:1,
724 vt:1,
725 vr:1;
726 uint32_t fcfi:16,
727 vpi:16;
728 uint32_t vf_id:13,
729 pri:3,
730 :16;
731 uint32_t :24,
732 hop_count:8;
733 #else
734 #error big endian version not defined
735 #endif
736 } sli4_cmd_init_vfi_t;
737
738 /**
739 * @brief INIT_VPI - initialize the VPI resource
740 */
741 typedef struct sli4_cmd_init_vpi_s {
742 sli4_mbox_command_header_t hdr;
743 #if BYTE_ORDER == LITTLE_ENDIAN
744 uint32_t vpi:16,
745 vfi:16;
746 #else
747 #error big endian version not defined
748 #endif
749 } sli4_cmd_init_vpi_t;
750
751 /**
752 * @brief POST_XRI - post XRI resources to the SLI Port
753 */
754 typedef struct sli4_cmd_post_xri_s {
755 sli4_mbox_command_header_t hdr;
756 #if BYTE_ORDER == LITTLE_ENDIAN
757 uint32_t xri_base:16,
758 xri_count:12,
759 enx:1,
760 dl:1,
761 di:1,
762 val:1;
763 #else
764 #error big endian version not defined
765 #endif
766 } sli4_cmd_post_xri_t;
767
768 /**
769 * @brief RELEASE_XRI - Release XRI resources from the SLI Port
770 */
771 typedef struct sli4_cmd_release_xri_s {
772 sli4_mbox_command_header_t hdr;
773 #if BYTE_ORDER == LITTLE_ENDIAN
774 uint32_t released_xri_count:5,
775 :11,
776 xri_count:5,
777 :11;
778 struct {
779 uint32_t xri_tag0:16,
780 xri_tag1:16;
781 } xri_tbl[62];
782 #else
783 #error big endian version not defined
784 #endif
785 } sli4_cmd_release_xri_t;
786
787 /**
788 * @brief READ_CONFIG - read SLI port configuration parameters
789 */
790 typedef struct sli4_cmd_read_config_s {
791 sli4_mbox_command_header_t hdr;
792 } sli4_cmd_read_config_t;
793
794 typedef struct sli4_res_read_config_s {
795 sli4_mbox_command_header_t hdr;
796 #if BYTE_ORDER == LITTLE_ENDIAN
797 uint32_t :31,
798 ext:1; /** Resource Extents */
799 uint32_t :20,
800 pt:2,
801 tf:1,
802 ptv:1,
803 topology:8;
804 uint32_t rsvd3;
805 uint32_t e_d_tov:16,
806 :16;
807 uint32_t rsvd5;
808 uint32_t r_a_tov:16,
809 :16;
810 uint32_t rsvd7;
811 uint32_t rsvd8;
812 uint32_t lmt:16, /** Link Module Type */
813 :16;
814 uint32_t rsvd10;
815 uint32_t rsvd11;
816 uint32_t xri_base:16,
817 xri_count:16;
818 uint32_t rpi_base:16,
819 rpi_count:16;
820 uint32_t vpi_base:16,
821 vpi_count:16;
822 uint32_t vfi_base:16,
823 vfi_count:16;
824 uint32_t :16,
825 fcfi_count:16;
826 uint32_t rq_count:16,
827 eq_count:16;
828 uint32_t wq_count:16,
829 cq_count:16;
830 uint32_t pad[45];
831 #else
832 #error big endian version not defined
833 #endif
834 } sli4_res_read_config_t;
835
836 #define SLI4_READ_CFG_TOPO_FCOE 0x0 /** FCoE topology */
837 #define SLI4_READ_CFG_TOPO_FC 0x1 /** FC topology unknown */
838 #define SLI4_READ_CFG_TOPO_FC_DA 0x2 /** FC Direct Attach (non FC-AL) topology */
839 #define SLI4_READ_CFG_TOPO_FC_AL 0x3 /** FC-AL topology */
840
841 /**
842 * @brief READ_NVPARMS - read SLI port configuration parameters
843 */
844 typedef struct sli4_cmd_read_nvparms_s {
845 sli4_mbox_command_header_t hdr;
846 #if BYTE_ORDER == LITTLE_ENDIAN
847 uint32_t rsvd1;
848 uint32_t rsvd2;
849 uint32_t rsvd3;
850 uint32_t rsvd4;
851 uint8_t wwpn[8];
852 uint8_t wwnn[8];
853 uint32_t hard_alpa:8,
854 preferred_d_id:24;
855 #else
856 #error big endian version not defined
857 #endif
858 } sli4_cmd_read_nvparms_t;
859
860 /**
861 * @brief WRITE_NVPARMS - write SLI port configuration parameters
862 */
863 typedef struct sli4_cmd_write_nvparms_s {
864 sli4_mbox_command_header_t hdr;
865 #if BYTE_ORDER == LITTLE_ENDIAN
866 uint32_t rsvd1;
867 uint32_t rsvd2;
868 uint32_t rsvd3;
869 uint32_t rsvd4;
870 uint8_t wwpn[8];
871 uint8_t wwnn[8];
872 uint32_t hard_alpa:8,
873 preferred_d_id:24;
874 #else
875 #error big endian version not defined
876 #endif
877 } sli4_cmd_write_nvparms_t;
878
879 /**
880 * @brief READ_REV - read the Port revision levels
881 */
882 typedef struct sli4_cmd_read_rev_s {
883 sli4_mbox_command_header_t hdr;
884 #if BYTE_ORDER == LITTLE_ENDIAN
885 uint32_t :16,
886 sli_level:4,
887 fcoem:1,
888 ceev:2,
889 :6,
890 vpd:1,
891 :2;
892 uint32_t first_hw_revision;
893 uint32_t second_hw_revision;
894 uint32_t rsvd4;
895 uint32_t third_hw_revision;
896 uint32_t fc_ph_low:8,
897 fc_ph_high:8,
898 feature_level_low:8,
899 feature_level_high:8;
900 uint32_t rsvd7;
901 uint32_t first_fw_id;
902 char first_fw_name[16];
903 uint32_t second_fw_id;
904 char second_fw_name[16];
905 uint32_t rsvd18[30];
906 uint32_t available_length:24,
907 :8;
908 uint32_t physical_address_low;
909 uint32_t physical_address_high;
910 uint32_t returned_vpd_length;
911 uint32_t actual_vpd_length;
912 #else
913 #error big endian version not defined
914 #endif
915 } sli4_cmd_read_rev_t;
916
917 /**
918 * @brief READ_SPARM64 - read the Port service parameters
919 */
920 typedef struct sli4_cmd_read_sparm64_s {
921 sli4_mbox_command_header_t hdr;
922 #if BYTE_ORDER == LITTLE_ENDIAN
923 uint32_t rsvd1;
924 uint32_t rsvd2;
925 sli4_bde_t bde_64;
926 uint32_t vpi:16,
927 :16;
928 uint32_t port_name_start:16,
929 port_name_length:16;
930 uint32_t node_name_start:16,
931 node_name_length:16;
932 #else
933 #error big endian version not defined
934 #endif
935 } sli4_cmd_read_sparm64_t;
936
937 #define SLI4_READ_SPARM64_VPI_DEFAULT 0
938 #define SLI4_READ_SPARM64_VPI_SPECIAL UINT16_MAX
939
940 #define SLI4_READ_SPARM64_WWPN_OFFSET (4 * sizeof(uint32_t))
941 #define SLI4_READ_SPARM64_WWNN_OFFSET (SLI4_READ_SPARM64_WWPN_OFFSET + sizeof(uint64_t))
942
943 typedef struct sli4_port_state_s {
944 #if BYTE_ORDER == LITTLE_ENDIAN
945 uint32_t nx_port_recv_state:2,
946 nx_port_trans_state:2,
947 nx_port_state_machine:4,
948 link_speed:8,
949 :14,
950 tf:1,
951 lu:1;
952 #else
953 #error big endian version not defined
954 #endif
955 } sli4_port_state_t;
956
957 /**
958 * @brief READ_TOPOLOGY - read the link event information
959 */
960 typedef struct sli4_cmd_read_topology_s {
961 sli4_mbox_command_header_t hdr;
962 #if BYTE_ORDER == LITTLE_ENDIAN
963 uint32_t event_tag;
964 uint32_t attention_type:8,
965 il:1,
966 pb_recvd:1,
967 :22;
968 uint32_t topology:8,
969 lip_type:8,
970 lip_al_ps:8,
971 al_pa_granted:8;
972 sli4_bde_t bde_loop_map;
973 sli4_port_state_t link_down;
974 sli4_port_state_t link_current;
975 uint32_t max_bbc:8,
976 init_bbc:8,
977 bbscn:4,
978 cbbscn:4,
979 :8;
980 uint32_t r_t_tov:9,
981 :3,
982 al_tov:4,
983 lp_tov:16;
984 uint32_t acquired_al_pa:8,
985 :7,
986 pb:1,
987 specified_al_pa:16;
988 uint32_t initial_n_port_id:24,
989 :8;
990 #else
991 #error big endian version not defined
992 #endif
993 } sli4_cmd_read_topology_t;
994
995 #define SLI4_MIN_LOOP_MAP_BYTES 128
996
997 #define SLI4_READ_TOPOLOGY_LINK_UP 0x1
998 #define SLI4_READ_TOPOLOGY_LINK_DOWN 0x2
999 #define SLI4_READ_TOPOLOGY_LINK_NO_ALPA 0x3
1000
1001 #define SLI4_READ_TOPOLOGY_UNKNOWN 0x0
1002 #define SLI4_READ_TOPOLOGY_NPORT 0x1
1003 #define SLI4_READ_TOPOLOGY_FC_AL 0x2
1004
1005 #define SLI4_READ_TOPOLOGY_SPEED_NONE 0x00
1006 #define SLI4_READ_TOPOLOGY_SPEED_1G 0x04
1007 #define SLI4_READ_TOPOLOGY_SPEED_2G 0x08
1008 #define SLI4_READ_TOPOLOGY_SPEED_4G 0x10
1009 #define SLI4_READ_TOPOLOGY_SPEED_8G 0x20
1010 #define SLI4_READ_TOPOLOGY_SPEED_10G 0x40
1011 #define SLI4_READ_TOPOLOGY_SPEED_16G 0x80
1012 #define SLI4_READ_TOPOLOGY_SPEED_32G 0x90
1013
1014 /**
1015 * @brief REG_FCFI - activate a FC Forwarder
1016 */
1017 #define SLI4_CMD_REG_FCFI_NUM_RQ_CFG 4
1018 typedef struct sli4_cmd_reg_fcfi_s {
1019 sli4_mbox_command_header_t hdr;
1020 #if BYTE_ORDER == LITTLE_ENDIAN
1021 uint32_t fcf_index:16,
1022 fcfi:16;
1023 uint32_t rq_id_1:16,
1024 rq_id_0:16;
1025 uint32_t rq_id_3:16,
1026 rq_id_2:16;
1027 struct {
1028 uint32_t r_ctl_mask:8,
1029 r_ctl_match:8,
1030 type_mask:8,
1031 type_match:8;
1032 } rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];
1033 uint32_t vlan_tag:12,
1034 vv:1,
1035 :19;
1036 #else
1037 #error big endian version not defined
1038 #endif
1039 } sli4_cmd_reg_fcfi_t;
1040
1041 #define SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG 4
1042 #define SLI4_CMD_REG_FCFI_MRQ_MAX_NUM_RQ 32
1043 #define SLI4_CMD_REG_FCFI_SET_FCFI_MODE 0
1044 #define SLI4_CMD_REG_FCFI_SET_MRQ_MODE 1
1045
1046 typedef struct sli4_cmd_reg_fcfi_mrq_s {
1047 sli4_mbox_command_header_t hdr;
1048 #if BYTE_ORDER == LITTLE_ENDIAN
1049 uint32_t fcf_index:16,
1050 fcfi:16;
1051
1052 uint32_t rq_id_1:16,
1053 rq_id_0:16;
1054
1055 uint32_t rq_id_3:16,
1056 rq_id_2:16;
1057
1058 struct {
1059 uint32_t r_ctl_mask:8,
1060 r_ctl_match:8,
1061 type_mask:8,
1062 type_match:8;
1063 } rq_cfg[SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG];
1064
1065 uint32_t vlan_tag:12,
1066 vv:1,
1067 mode:1,
1068 :18;
1069
1070 uint32_t num_mrq_pairs:8,
1071 mrq_filter_bitmask:4,
1072 rq_selection_policy:4,
1073 :16;
1074 #endif
1075 } sli4_cmd_reg_fcfi_mrq_t;
1076
1077 /**
1078 * @brief REG_RPI - register a Remote Port Indicator
1079 */
1080 typedef struct sli4_cmd_reg_rpi_s {
1081 sli4_mbox_command_header_t hdr;
1082 #if BYTE_ORDER == LITTLE_ENDIAN
1083 uint32_t rpi:16,
1084 :16;
1085 uint32_t remote_n_port_id:24,
1086 upd:1,
1087 :2,
1088 etow:1,
1089 :1,
1090 terp:1,
1091 :1,
1092 ci:1;
1093 sli4_bde_t bde_64;
1094 uint32_t vpi:16,
1095 :16;
1096 #else
1097 #error big endian version not defined
1098 #endif
1099 } sli4_cmd_reg_rpi_t;
1100 #define SLI4_REG_RPI_BUF_LEN 0x70
1101
1102
1103 /**
1104 * @brief REG_VFI - register a Virtual Fabric Indicator
1105 */
1106 typedef struct sli4_cmd_reg_vfi_s {
1107 sli4_mbox_command_header_t hdr;
1108 #if BYTE_ORDER == LITTLE_ENDIAN
1109 uint32_t vfi:16,
1110 :12,
1111 vp:1,
1112 upd:1,
1113 :2;
1114 uint32_t fcfi:16,
1115 vpi:16; /* vp=TRUE */
1116 uint8_t wwpn[8]; /* vp=TRUE */
1117 sli4_bde_t sparm; /* either FLOGI or PLOGI */
1118 uint32_t e_d_tov;
1119 uint32_t r_a_tov;
1120 uint32_t local_n_port_id:24, /* vp=TRUE */
1121 :8;
1122 #else
1123 #error big endian version not defined
1124 #endif
1125 } sli4_cmd_reg_vfi_t;
1126
1127 /**
1128 * @brief REG_VPI - register a Virtual Port Indicator
1129 */
1130 typedef struct sli4_cmd_reg_vpi_s {
1131 sli4_mbox_command_header_t hdr;
1132 #if BYTE_ORDER == LITTLE_ENDIAN
1133 uint32_t rsvd1;
1134 uint32_t local_n_port_id:24,
1135 upd:1,
1136 :7;
1137 uint8_t wwpn[8];
1138 uint32_t rsvd5;
1139 uint32_t vpi:16,
1140 vfi:16;
1141 #else
1142 #error big endian version not defined
1143 #endif
1144 } sli4_cmd_reg_vpi_t;
1145
1146 /**
1147 * @brief REQUEST_FEATURES - request / query SLI features
1148 */
1149 typedef union {
1150 #if BYTE_ORDER == LITTLE_ENDIAN
1151 struct {
1152 uint32_t iaab:1, /** inhibit auto-ABTS originator */
1153 npiv:1, /** NPIV support */
1154 dif:1, /** DIF/DIX support */
1155 vf:1, /** virtual fabric support */
1156 fcpi:1, /** FCP initiator support */
1157 fcpt:1, /** FCP target support */
1158 fcpc:1, /** combined FCP initiator/target */
1159 :1,
1160 rqd:1, /** recovery qualified delay */
1161 iaar:1, /** inhibit auto-ABTS responder */
1162 hlm:1, /** High Login Mode */
1163 perfh:1, /** performance hints */
1164 rxseq:1, /** RX Sequence Coalescing */
1165 rxri:1, /** Release XRI variant of Coalescing */
1166 dcl2:1, /** Disable Class 2 */
1167 rsco:1, /** Receive Sequence Coalescing Optimizations */
1168 mrqp:1, /** Multi RQ Pair Mode Support */
1169 :15;
1170 } flag;
1171 uint32_t dword;
1172 #else
1173 #error big endian version not defined
1174 #endif
1175 } sli4_features_t;
1176
1177 typedef struct sli4_cmd_request_features_s {
1178 sli4_mbox_command_header_t hdr;
1179 #if BYTE_ORDER == LITTLE_ENDIAN
1180 uint32_t qry:1,
1181 :31;
1182 #else
1183 #error big endian version not defined
1184 #endif
1185 sli4_features_t command;
1186 sli4_features_t response;
1187 } sli4_cmd_request_features_t;
1188
1189 /**
1190 * @brief SLI_CONFIG - submit a configuration command to Port
1191 *
1192 * Command is either embedded as part of the payload (embed) or located
1193 * in a separate memory buffer (mem)
1194 */
1195
1196
1197 typedef struct sli4_sli_config_pmd_s {
1198 uint32_t address_low;
1199 uint32_t address_high;
1200 uint32_t length:24,
1201 :8;
1202 } sli4_sli_config_pmd_t;
1203
1204 typedef struct sli4_cmd_sli_config_s {
1205 sli4_mbox_command_header_t hdr;
1206 #if BYTE_ORDER == LITTLE_ENDIAN
1207 uint32_t emb:1,
1208 :2,
1209 pmd_count:5,
1210 :24;
1211 uint32_t payload_length;
1212 uint32_t rsvd3;
1213 uint32_t rsvd4;
1214 uint32_t rsvd5;
1215 union {
1216 uint8_t embed[58 * sizeof(uint32_t)];
1217 sli4_sli_config_pmd_t mem;
1218 } payload;
1219 #else
1220 #error big endian version not defined
1221 #endif
1222 } sli4_cmd_sli_config_t;
1223
1224 /**
1225 * @brief READ_STATUS - read tx/rx status of a particular port
1226 *
1227 */
1228
1229 typedef struct sli4_cmd_read_status_s {
1230 sli4_mbox_command_header_t hdr;
1231 #if BYTE_ORDER == LITTLE_ENDIAN
1232 uint32_t cc:1,
1233 :31;
1234 uint32_t rsvd2;
1235 uint32_t transmit_kbyte_count;
1236 uint32_t receive_kbyte_count;
1237 uint32_t transmit_frame_count;
1238 uint32_t receive_frame_count;
1239 uint32_t transmit_sequence_count;
1240 uint32_t receive_sequence_count;
1241 uint32_t total_exchanges_originator;
1242 uint32_t total_exchanges_responder;
1243 uint32_t receive_p_bsy_count;
1244 uint32_t receive_f_bsy_count;
1245 uint32_t dropped_frames_due_to_no_rq_buffer_count;
1246 uint32_t empty_rq_timeout_count;
1247 uint32_t dropped_frames_due_to_no_xri_count;
1248 uint32_t empty_xri_pool_count;
1249
1250 #else
1251 #error big endian version not defined
1252 #endif
1253 } sli4_cmd_read_status_t;
1254
1255 /**
1256 * @brief READ_LNK_STAT - read link status of a particular port
1257 *
1258 */
1259
1260 typedef struct sli4_cmd_read_link_stats_s {
1261 sli4_mbox_command_header_t hdr;
1262 #if BYTE_ORDER == LITTLE_ENDIAN
1263 uint32_t rec:1,
1264 gec:1,
1265 w02of:1,
1266 w03of:1,
1267 w04of:1,
1268 w05of:1,
1269 w06of:1,
1270 w07of:1,
1271 w08of:1,
1272 w09of:1,
1273 w10of:1,
1274 w11of:1,
1275 w12of:1,
1276 w13of:1,
1277 w14of:1,
1278 w15of:1,
1279 w16of:1,
1280 w17of:1,
1281 w18of:1,
1282 w19of:1,
1283 w20of:1,
1284 w21of:1,
1285 resv0:8,
1286 clrc:1,
1287 clof:1;
1288 uint32_t link_failure_error_count;
1289 uint32_t loss_of_sync_error_count;
1290 uint32_t loss_of_signal_error_count;
1291 uint32_t primitive_sequence_error_count;
1292 uint32_t invalid_transmission_word_error_count;
1293 uint32_t crc_error_count;
1294 uint32_t primitive_sequence_event_timeout_count;
1295 uint32_t elastic_buffer_overrun_error_count;
1296 uint32_t arbitration_fc_al_timout_count;
1297 uint32_t advertised_receive_bufftor_to_buffer_credit;
1298 uint32_t current_receive_buffer_to_buffer_credit;
1299 uint32_t advertised_transmit_buffer_to_buffer_credit;
1300 uint32_t current_transmit_buffer_to_buffer_credit;
1301 uint32_t received_eofa_count;
1302 uint32_t received_eofdti_count;
1303 uint32_t received_eofni_count;
1304 uint32_t received_soff_count;
1305 uint32_t received_dropped_no_aer_count;
1306 uint32_t received_dropped_no_available_rpi_resources_count;
1307 uint32_t received_dropped_no_available_xri_resources_count;
1308
1309 #else
1310 #error big endian version not defined
1311 #endif
1312 } sli4_cmd_read_link_stats_t;
1313
1314 /**
1315 * @brief Format a WQE with WQ_ID Association performance hint
1316 *
1317 * @par Description
1318 * PHWQ works by over-writing part of Word 10 in the WQE with the WQ ID.
1319 *
1320 * @param entry Pointer to the WQE.
1321 * @param q_id Queue ID.
1322 *
1323 * @return None.
1324 */
1325 static inline void
sli_set_wq_id_association(void * entry,uint16_t q_id)1326 sli_set_wq_id_association(void *entry, uint16_t q_id)
1327 {
1328 uint32_t *wqe = entry;
1329
1330 /*
1331 * Set Word 10, bit 0 to zero
1332 * Set Word 10, bits 15:1 to the WQ ID
1333 */
1334 #if BYTE_ORDER == LITTLE_ENDIAN
1335 wqe[10] &= ~0xffff;
1336 wqe[10] |= q_id << 1;
1337 #else
1338 #error big endian version not defined
1339 #endif
1340 }
1341
1342 /**
1343 * @brief UNREG_FCFI - unregister a FCFI
1344 */
1345 typedef struct sli4_cmd_unreg_fcfi_s {
1346 sli4_mbox_command_header_t hdr;
1347 uint32_t rsvd1;
1348 #if BYTE_ORDER == LITTLE_ENDIAN
1349 uint32_t fcfi:16,
1350 :16;
1351 #else
1352 #error big endian version not defined
1353 #endif
1354 } sli4_cmd_unreg_fcfi_t;
1355
1356 /**
1357 * @brief UNREG_RPI - unregister one or more RPI
1358 */
1359 typedef struct sli4_cmd_unreg_rpi_s {
1360 sli4_mbox_command_header_t hdr;
1361 #if BYTE_ORDER == LITTLE_ENDIAN
1362 uint32_t index:16,
1363 :13,
1364 dp:1,
1365 ii:2;
1366 uint32_t destination_n_port_id:24,
1367 :8;
1368 #else
1369 #error big endian version not defined
1370 #endif
1371 } sli4_cmd_unreg_rpi_t;
1372
1373 #define SLI4_UNREG_RPI_II_RPI 0x0
1374 #define SLI4_UNREG_RPI_II_VPI 0x1
1375 #define SLI4_UNREG_RPI_II_VFI 0x2
1376 #define SLI4_UNREG_RPI_II_FCFI 0x3
1377
1378 /**
1379 * @brief UNREG_VFI - unregister one or more VFI
1380 */
1381 typedef struct sli4_cmd_unreg_vfi_s {
1382 sli4_mbox_command_header_t hdr;
1383 #if BYTE_ORDER == LITTLE_ENDIAN
1384 uint32_t rsvd1;
1385 uint32_t index:16,
1386 :14,
1387 ii:2;
1388 #else
1389 #error big endian version not defined
1390 #endif
1391 } sli4_cmd_unreg_vfi_t;
1392
1393 #define SLI4_UNREG_VFI_II_VFI 0x0
1394 #define SLI4_UNREG_VFI_II_FCFI 0x3
1395
1396 enum {
1397 SLI4_UNREG_TYPE_PORT,
1398 SLI4_UNREG_TYPE_DOMAIN,
1399 SLI4_UNREG_TYPE_FCF,
1400 SLI4_UNREG_TYPE_ALL
1401 };
1402
1403 /**
1404 * @brief UNREG_VPI - unregister one or more VPI
1405 */
1406 typedef struct sli4_cmd_unreg_vpi_s {
1407 sli4_mbox_command_header_t hdr;
1408 #if BYTE_ORDER == LITTLE_ENDIAN
1409 uint32_t rsvd1;
1410 uint32_t index:16,
1411 :14,
1412 ii:2;
1413 #else
1414 #error big endian version not defined
1415 #endif
1416 } sli4_cmd_unreg_vpi_t;
1417
1418 #define SLI4_UNREG_VPI_II_VPI 0x0
1419 #define SLI4_UNREG_VPI_II_VFI 0x2
1420 #define SLI4_UNREG_VPI_II_FCFI 0x3
1421
1422
1423 /**
1424 * @brief AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature.
1425 */
1426 typedef struct sli4_cmd_config_auto_xfer_rdy_s {
1427 sli4_mbox_command_header_t hdr;
1428 #if BYTE_ORDER == LITTLE_ENDIAN
1429 uint32_t resv;
1430 uint32_t max_burst_len;
1431 #else
1432 #error big endian version not defined
1433 #endif
1434 } sli4_cmd_config_auto_xfer_rdy_t;
1435
1436 typedef struct sli4_cmd_config_auto_xfer_rdy_hp_s {
1437 sli4_mbox_command_header_t hdr;
1438 #if BYTE_ORDER == LITTLE_ENDIAN
1439 uint32_t resv;
1440 uint32_t max_burst_len;
1441 uint32_t esoc:1,
1442 :31;
1443 uint32_t block_size:16,
1444 :16;
1445 #else
1446 #error big endian version not defined
1447 #endif
1448 } sli4_cmd_config_auto_xfer_rdy_hp_t;
1449
1450
1451 /*************************************************************************
1452 * SLI-4 common configuration command formats and definitions
1453 */
1454
1455 #define SLI4_CFG_STATUS_SUCCESS 0x00
1456 #define SLI4_CFG_STATUS_FAILED 0x01
1457 #define SLI4_CFG_STATUS_ILLEGAL_REQUEST 0x02
1458 #define SLI4_CFG_STATUS_ILLEGAL_FIELD 0x03
1459
1460 #define SLI4_MGMT_STATUS_FLASHROM_READ_FAILED 0xcb
1461
1462 #define SLI4_CFG_ADD_STATUS_NO_STATUS 0x00
1463 #define SLI4_CFG_ADD_STATUS_INVALID_OPCODE 0x1e
1464
1465 /**
1466 * Subsystem values.
1467 */
1468 #define SLI4_SUBSYSTEM_COMMON 0x01
1469 #define SLI4_SUBSYSTEM_LOWLEVEL 0x0B
1470 #define SLI4_SUBSYSTEM_FCFCOE 0x0c
1471 #define SLI4_SUBSYSTEM_DMTF 0x11
1472
1473 #define SLI4_OPC_LOWLEVEL_SET_WATCHDOG 0X36
1474
1475 /**
1476 * Common opcode (OPC) values.
1477 */
1478 #define SLI4_OPC_COMMON_FUNCTION_RESET 0x3d
1479 #define SLI4_OPC_COMMON_CREATE_CQ 0x0c
1480 #define SLI4_OPC_COMMON_CREATE_CQ_SET 0x1d
1481 #define SLI4_OPC_COMMON_DESTROY_CQ 0x36
1482 #define SLI4_OPC_COMMON_MODIFY_EQ_DELAY 0x29
1483 #define SLI4_OPC_COMMON_CREATE_EQ 0x0d
1484 #define SLI4_OPC_COMMON_DESTROY_EQ 0x37
1485 #define SLI4_OPC_COMMON_CREATE_MQ_EXT 0x5a
1486 #define SLI4_OPC_COMMON_DESTROY_MQ 0x35
1487 #define SLI4_OPC_COMMON_GET_CNTL_ATTRIBUTES 0x20
1488 #define SLI4_OPC_COMMON_NOP 0x21
1489 #define SLI4_OPC_COMMON_GET_RESOURCE_EXTENT_INFO 0x9a
1490 #define SLI4_OPC_COMMON_GET_SLI4_PARAMETERS 0xb5
1491 #define SLI4_OPC_COMMON_QUERY_FW_CONFIG 0x3a
1492 #define SLI4_OPC_COMMON_GET_PORT_NAME 0x4d
1493
1494 #define SLI4_OPC_COMMON_WRITE_FLASHROM 0x07
1495 #define SLI4_OPC_COMMON_MANAGE_FAT 0x44
1496 #define SLI4_OPC_COMMON_READ_TRANSCEIVER_DATA 0x49
1497 #define SLI4_OPC_COMMON_GET_CNTL_ADDL_ATTRIBUTES 0x79
1498 #define SLI4_OPC_COMMON_GET_EXT_FAT_CAPABILITIES 0x7d
1499 #define SLI4_OPC_COMMON_SET_EXT_FAT_CAPABILITIES 0x7e
1500 #define SLI4_OPC_COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 0x7f
1501 #define SLI4_OPC_COMMON_EXT_FAT_RETRIEVE_SNAPSHOT 0x80
1502 #define SLI4_OPC_COMMON_EXT_FAT_READ_STRING_TABLE 0x82
1503 #define SLI4_OPC_COMMON_GET_FUNCTION_CONFIG 0xa0
1504 #define SLI4_OPC_COMMON_GET_PROFILE_CONFIG 0xa4
1505 #define SLI4_OPC_COMMON_SET_PROFILE_CONFIG 0xa5
1506 #define SLI4_OPC_COMMON_GET_PROFILE_LIST 0xa6
1507 #define SLI4_OPC_COMMON_GET_ACTIVE_PROFILE 0xa7
1508 #define SLI4_OPC_COMMON_SET_ACTIVE_PROFILE 0xa8
1509 #define SLI4_OPC_COMMON_READ_OBJECT 0xab
1510 #define SLI4_OPC_COMMON_WRITE_OBJECT 0xac
1511 #define SLI4_OPC_COMMON_DELETE_OBJECT 0xae
1512 #define SLI4_OPC_COMMON_READ_OBJECT_LIST 0xad
1513 #define SLI4_OPC_COMMON_SET_DUMP_LOCATION 0xb8
1514 #define SLI4_OPC_COMMON_SET_FEATURES 0xbf
1515 #define SLI4_OPC_COMMON_GET_RECONFIG_LINK_INFO 0xc9
1516 #define SLI4_OPC_COMMON_SET_RECONFIG_LINK_ID 0xca
1517
1518 /**
1519 * DMTF opcode (OPC) values.
1520 */
1521 #define SLI4_OPC_DMTF_EXEC_CLP_CMD 0x01
1522
1523 /**
1524 * @brief Generic Command Request header
1525 */
1526 typedef struct sli4_req_hdr_s {
1527 #if BYTE_ORDER == LITTLE_ENDIAN
1528 uint32_t opcode:8,
1529 subsystem:8,
1530 :16;
1531 uint32_t timeout;
1532 uint32_t request_length;
1533 uint32_t version:8,
1534 :24;
1535 #else
1536 #error big endian version not defined
1537 #endif
1538 } sli4_req_hdr_t;
1539
1540 /**
1541 * @brief Generic Command Response header
1542 */
1543 typedef struct sli4_res_hdr_s {
1544 #if BYTE_ORDER == LITTLE_ENDIAN
1545 uint32_t opcode:8,
1546 subsystem:8,
1547 :16;
1548 uint32_t status:8,
1549 additional_status:8,
1550 :16;
1551 uint32_t response_length;
1552 uint32_t actual_response_length;
1553 #else
1554 #error big endian version not defined
1555 #endif
1556 } sli4_res_hdr_t;
1557
1558 /**
1559 * @brief COMMON_FUNCTION_RESET
1560 *
1561 * Resets the Port, returning it to a power-on state. This configuration
1562 * command does not have a payload and should set/expect the lengths to
1563 * be zero.
1564 */
1565 typedef struct sli4_req_common_function_reset_s {
1566 sli4_req_hdr_t hdr;
1567 } sli4_req_common_function_reset_t;
1568
1569
1570 typedef struct sli4_res_common_function_reset_s {
1571 sli4_res_hdr_t hdr;
1572 } sli4_res_common_function_reset_t;
1573
1574 /**
1575 * @brief COMMON_CREATE_CQ_V0
1576 *
1577 * Create a Completion Queue.
1578 */
1579 typedef struct sli4_req_common_create_cq_v0_s {
1580 sli4_req_hdr_t hdr;
1581 #if BYTE_ORDER == LITTLE_ENDIAN
1582 uint32_t num_pages:16,
1583 :16;
1584 uint32_t :12,
1585 clswm:2,
1586 nodelay:1,
1587 :12,
1588 cqecnt:2,
1589 valid:1,
1590 :1,
1591 evt:1;
1592 uint32_t :22,
1593 eq_id:8,
1594 :1,
1595 arm:1;
1596 uint32_t rsvd[2];
1597 struct {
1598 uint32_t low;
1599 uint32_t high;
1600 } page_physical_address[0];
1601 #else
1602 #error big endian version not defined
1603 #endif
1604 } sli4_req_common_create_cq_v0_t;
1605
1606 /**
1607 * @brief COMMON_CREATE_CQ_V2
1608 *
1609 * Create a Completion Queue.
1610 */
1611 typedef struct sli4_req_common_create_cq_v2_s {
1612 sli4_req_hdr_t hdr;
1613 #if BYTE_ORDER == LITTLE_ENDIAN
1614 uint32_t num_pages:16,
1615 page_size:8,
1616 :8,
1617 uint32_t :12,
1618 clswm:2,
1619 nodelay:1,
1620 autovalid:1,
1621 :9,
1622 cqe_size:2,
1623 cqecnt:2,
1624 valid:1,
1625 :1,
1626 evt:1;
1627 uint32_t eq_id:16,
1628 :15,
1629 arm:1;
1630 uint32_t cqe_count:16,
1631 :16;
1632 uint32_t rsvd[1];
1633 struct {
1634 uint32_t low;
1635 uint32_t high;
1636 } page_physical_address[0];
1637 #else
1638 #error big endian version not defined
1639 #endif
1640 } sli4_req_common_create_cq_v2_t;
1641
1642
1643
1644 /**
1645 * @brief COMMON_CREATE_CQ_SET_V0
1646 *
1647 * Create a set of Completion Queues.
1648 */
1649 typedef struct sli4_req_common_create_cq_set_v0_s {
1650 sli4_req_hdr_t hdr;
1651 #if BYTE_ORDER == LITTLE_ENDIAN
1652 uint32_t num_pages:16,
1653 page_size:8,
1654 :8;
1655 uint32_t :12,
1656 clswm:2,
1657 nodelay:1,
1658 autovalid:1,
1659 rsvd:11,
1660 cqecnt:2,
1661 valid:1,
1662 :1,
1663 evt:1;
1664 uint32_t num_cq_req:16,
1665 cqe_count:15,
1666 arm:1;
1667 uint16_t eq_id[16];
1668 struct {
1669 uint32_t low;
1670 uint32_t high;
1671 } page_physical_address[0];
1672 #else
1673 #error big endian version not defined
1674 #endif
1675 } sli4_req_common_create_cq_set_v0_t;
1676
1677 /**
1678 * CQE count.
1679 */
1680 #define SLI4_CQ_CNT_256 0
1681 #define SLI4_CQ_CNT_512 1
1682 #define SLI4_CQ_CNT_1024 2
1683 #define SLI4_CQ_CNT_LARGE 3
1684
1685 #define SLI4_CQE_BYTES (4 * sizeof(uint32_t))
1686
1687 #define SLI4_COMMON_CREATE_CQ_V2_MAX_PAGES 8
1688
1689 /**
1690 * @brief Generic Common Create EQ/CQ/MQ/WQ/RQ Queue completion
1691 */
1692 typedef struct sli4_res_common_create_queue_s {
1693 sli4_res_hdr_t hdr;
1694 #if BYTE_ORDER == LITTLE_ENDIAN
1695 uint32_t q_id:16,
1696 :8,
1697 ulp:8;
1698 uint32_t db_offset;
1699 uint32_t db_rs:16,
1700 db_fmt:16;
1701 #else
1702 #error big endian version not defined
1703 #endif
1704 } sli4_res_common_create_queue_t;
1705
1706
1707 typedef struct sli4_res_common_create_queue_set_s {
1708 sli4_res_hdr_t hdr;
1709 #if BYTE_ORDER == LITTLE_ENDIAN
1710 uint32_t q_id:16,
1711 num_q_allocated:16;
1712 #else
1713 #error big endian version not defined
1714 #endif
1715 } sli4_res_common_create_queue_set_t;
1716
1717
1718 /**
1719 * @brief Common Destroy CQ
1720 */
1721 typedef struct sli4_req_common_destroy_cq_s {
1722 sli4_req_hdr_t hdr;
1723 #if BYTE_ORDER == LITTLE_ENDIAN
1724 uint32_t cq_id:16,
1725 :16;
1726 #else
1727 #error big endian version not defined
1728 #endif
1729 } sli4_req_common_destroy_cq_t;
1730
1731 /**
1732 * @brief COMMON_MODIFY_EQ_DELAY
1733 *
1734 * Modify the delay multiplier for EQs
1735 */
1736 typedef struct sli4_req_common_modify_eq_delay_s {
1737 sli4_req_hdr_t hdr;
1738 #if BYTE_ORDER == LITTLE_ENDIAN
1739 uint32_t num_eq;
1740 struct {
1741 uint32_t eq_id;
1742 uint32_t phase;
1743 uint32_t delay_multiplier;
1744 } eq_delay_record[8];
1745 #else
1746 #error big endian version not defined
1747 #endif
1748 } sli4_req_common_modify_eq_delay_t;
1749
1750 /**
1751 * @brief COMMON_CREATE_EQ
1752 *
1753 * Create an Event Queue.
1754 */
1755 typedef struct sli4_req_common_create_eq_s {
1756 sli4_req_hdr_t hdr;
1757 #if BYTE_ORDER == LITTLE_ENDIAN
1758 uint32_t num_pages:16,
1759 :16;
1760 uint32_t :28,
1761 autovalid:1,
1762 valid:1,
1763 :1,
1764 eqesz:1;
1765 uint32_t :26,
1766 count:3,
1767 :2,
1768 arm:1;
1769 uint32_t :13,
1770 delay_multiplier:10,
1771 :9;
1772 uint32_t rsvd;
1773 struct {
1774 uint32_t low;
1775 uint32_t high;
1776 } page_address[8];
1777 #else
1778 #error big endian version not defined
1779 #endif
1780 } sli4_req_common_create_eq_t;
1781
1782 #define SLI4_EQ_CNT_256 0
1783 #define SLI4_EQ_CNT_512 1
1784 #define SLI4_EQ_CNT_1024 2
1785 #define SLI4_EQ_CNT_2048 3
1786 #define SLI4_EQ_CNT_4096 4
1787
1788 #define SLI4_EQE_SIZE_4 0
1789 #define SLI4_EQE_SIZE_16 1
1790
1791 /**
1792 * @brief Common Destroy EQ
1793 */
1794 typedef struct sli4_req_common_destroy_eq_s {
1795 sli4_req_hdr_t hdr;
1796 #if BYTE_ORDER == LITTLE_ENDIAN
1797 uint32_t eq_id:16,
1798 :16;
1799 #else
1800 #error big endian version not defined
1801 #endif
1802 } sli4_req_common_destroy_eq_t;
1803
1804 /**
1805 * @brief COMMON_CREATE_MQ_EXT
1806 *
1807 * Create a Mailbox Queue; accommodate v0 and v1 forms.
1808 */
1809 typedef struct sli4_req_common_create_mq_ext_s {
1810 sli4_req_hdr_t hdr;
1811 #if BYTE_ORDER == LITTLE_ENDIAN
1812 uint32_t num_pages:16,
1813 cq_id_v1:16;
1814 uint32_t async_event_bitmap;
1815 uint32_t async_cq_id_v1:16,
1816 ring_size:4,
1817 :2,
1818 cq_id_v0:10;
1819 uint32_t :31,
1820 val:1;
1821 uint32_t acqv:1,
1822 async_cq_id_v0:10,
1823 :21;
1824 uint32_t rsvd9;
1825 struct {
1826 uint32_t low;
1827 uint32_t high;
1828 } page_physical_address[8];
1829 #else
1830 #error big endian version not defined
1831 #endif
1832 } sli4_req_common_create_mq_ext_t;
1833
1834 #define SLI4_MQE_SIZE_16 0x05
1835 #define SLI4_MQE_SIZE_32 0x06
1836 #define SLI4_MQE_SIZE_64 0x07
1837 #define SLI4_MQE_SIZE_128 0x08
1838
1839 #define SLI4_ASYNC_EVT_LINK_STATE BIT(1)
1840 #define SLI4_ASYNC_EVT_FCOE_FIP BIT(2)
1841 #define SLI4_ASYNC_EVT_DCBX BIT(3)
1842 #define SLI4_ASYNC_EVT_ISCSI BIT(4)
1843 #define SLI4_ASYNC_EVT_GRP5 BIT(5)
1844 #define SLI4_ASYNC_EVT_FC BIT(16)
1845 #define SLI4_ASYNC_EVT_SLI_PORT BIT(17)
1846 #define SLI4_ASYNC_EVT_VF BIT(18)
1847 #define SLI4_ASYNC_EVT_MR BIT(19)
1848
1849 #define SLI4_ASYNC_EVT_ALL \
1850 SLI4_ASYNC_EVT_LINK_STATE | \
1851 SLI4_ASYNC_EVT_FCOE_FIP | \
1852 SLI4_ASYNC_EVT_DCBX | \
1853 SLI4_ASYNC_EVT_ISCSI | \
1854 SLI4_ASYNC_EVT_GRP5 | \
1855 SLI4_ASYNC_EVT_FC | \
1856 SLI4_ASYNC_EVT_SLI_PORT | \
1857 SLI4_ASYNC_EVT_VF |\
1858 SLI4_ASYNC_EVT_MR
1859
1860 #define SLI4_ASYNC_EVT_FC_FCOE \
1861 SLI4_ASYNC_EVT_LINK_STATE | \
1862 SLI4_ASYNC_EVT_FCOE_FIP | \
1863 SLI4_ASYNC_EVT_GRP5 | \
1864 SLI4_ASYNC_EVT_FC | \
1865 SLI4_ASYNC_EVT_SLI_PORT
1866
1867 /**
1868 * @brief Common Destroy MQ
1869 */
1870 typedef struct sli4_req_common_destroy_mq_s {
1871 sli4_req_hdr_t hdr;
1872 #if BYTE_ORDER == LITTLE_ENDIAN
1873 uint32_t mq_id:16,
1874 :16;
1875 #else
1876 #error big endian version not defined
1877 #endif
1878 } sli4_req_common_destroy_mq_t;
1879
1880 /**
1881 * @brief COMMON_GET_CNTL_ATTRIBUTES
1882 *
1883 * Query for information about the SLI Port
1884 */
1885 typedef struct sli4_res_common_get_cntl_attributes_s {
1886 sli4_res_hdr_t hdr;
1887 #if BYTE_ORDER == LITTLE_ENDIAN
1888 uint8_t version_string[32];
1889 uint8_t manufacturer_name[32];
1890 uint32_t supported_modes;
1891 uint32_t eprom_version_lo:8,
1892 eprom_version_hi:8,
1893 :16;
1894 uint32_t mbx_data_structure_version;
1895 uint32_t ep_firmware_data_structure_version;
1896 uint8_t ncsi_version_string[12];
1897 uint32_t default_extended_timeout;
1898 uint8_t model_number[32];
1899 uint8_t description[64];
1900 uint8_t serial_number[32];
1901 uint8_t ip_version_string[32];
1902 uint8_t fw_version_string[32];
1903 uint8_t bios_version_string[32];
1904 uint8_t redboot_version_string[32];
1905 uint8_t driver_version_string[32];
1906 uint8_t fw_on_flash_version_string[32];
1907 uint32_t functionalities_supported;
1908 uint32_t max_cdb_length:16,
1909 asic_revision:8,
1910 generational_guid0:8;
1911 uint32_t generational_guid1_12[3];
1912 uint32_t generational_guid13:24,
1913 hba_port_count:8;
1914 uint32_t default_link_down_timeout:16,
1915 iscsi_version_min_max:8,
1916 multifunctional_device:8;
1917 uint32_t cache_valid:8,
1918 hba_status:8,
1919 max_domains_supported:8,
1920 port_number:6,
1921 port_type:2;
1922 uint32_t firmware_post_status;
1923 uint32_t hba_mtu;
1924 uint32_t iscsi_features:8,
1925 rsvd121:24;
1926 uint32_t pci_vendor_id:16,
1927 pci_device_id:16;
1928 uint32_t pci_sub_vendor_id:16,
1929 pci_sub_system_id:16;
1930 uint32_t pci_bus_number:8,
1931 pci_device_number:8,
1932 pci_function_number:8,
1933 interface_type:8;
1934 uint64_t unique_identifier;
1935 uint32_t number_of_netfilters:8,
1936 rsvd130:24;
1937 #else
1938 #error big endian version not defined
1939 #endif
1940 } sli4_res_common_get_cntl_attributes_t;
1941
1942 /**
1943 * @brief COMMON_GET_CNTL_ATTRIBUTES
1944 *
1945 * This command queries the controller information from the Flash ROM.
1946 */
1947 typedef struct sli4_req_common_get_cntl_addl_attributes_s {
1948 sli4_req_hdr_t hdr;
1949 } sli4_req_common_get_cntl_addl_attributes_t;
1950
1951
1952 typedef struct sli4_res_common_get_cntl_addl_attributes_s {
1953 sli4_res_hdr_t hdr;
1954 uint16_t ipl_file_number;
1955 uint8_t ipl_file_version;
1956 uint8_t rsvd0;
1957 uint8_t on_die_temperature;
1958 uint8_t rsvd1[3];
1959 uint32_t driver_advanced_features_supported;
1960 uint32_t rsvd2[4];
1961 char fcoe_universal_bios_version[32];
1962 char fcoe_x86_bios_version[32];
1963 char fcoe_efi_bios_version[32];
1964 char fcoe_fcode_version[32];
1965 char uefi_bios_version[32];
1966 char uefi_nic_version[32];
1967 char uefi_fcode_version[32];
1968 char uefi_iscsi_version[32];
1969 char iscsi_x86_bios_version[32];
1970 char pxe_x86_bios_version[32];
1971 uint8_t fcoe_default_wwpn[8];
1972 uint8_t ext_phy_version[32];
1973 uint8_t fc_universal_bios_version[32];
1974 uint8_t fc_x86_bios_version[32];
1975 uint8_t fc_efi_bios_version[32];
1976 uint8_t fc_fcode_version[32];
1977 uint8_t ext_phy_crc_label[8];
1978 uint8_t ipl_file_name[16];
1979 uint8_t rsvd3[72];
1980 } sli4_res_common_get_cntl_addl_attributes_t;
1981
1982 /**
1983 * @brief COMMON_NOP
1984 *
1985 * This command does not do anything; it only returns the payload in the completion.
1986 */
1987 typedef struct sli4_req_common_nop_s {
1988 sli4_req_hdr_t hdr;
1989 #if BYTE_ORDER == LITTLE_ENDIAN
1990 uint32_t context[2];
1991 #else
1992 #error big endian version not defined
1993 #endif
1994 } sli4_req_common_nop_t;
1995
1996 typedef struct sli4_res_common_nop_s {
1997 sli4_res_hdr_t hdr;
1998 #if BYTE_ORDER == LITTLE_ENDIAN
1999 uint32_t context[2];
2000 #else
2001 #error big endian version not defined
2002 #endif
2003 } sli4_res_common_nop_t;
2004
2005 /**
2006 * @brief COMMON_GET_RESOURCE_EXTENT_INFO
2007 */
2008 typedef struct sli4_req_common_get_resource_extent_info_s {
2009 sli4_req_hdr_t hdr;
2010 #if BYTE_ORDER == LITTLE_ENDIAN
2011 uint32_t resource_type:16,
2012 :16;
2013 #else
2014 #error big endian version not defined
2015 #endif
2016 } sli4_req_common_get_resource_extent_info_t;
2017
2018 #define SLI4_RSC_TYPE_ISCSI_INI_XRI 0x0c
2019 #define SLI4_RSC_TYPE_FCOE_VFI 0x20
2020 #define SLI4_RSC_TYPE_FCOE_VPI 0x21
2021 #define SLI4_RSC_TYPE_FCOE_RPI 0x22
2022 #define SLI4_RSC_TYPE_FCOE_XRI 0x23
2023
2024 typedef struct sli4_res_common_get_resource_extent_info_s {
2025 sli4_res_hdr_t hdr;
2026 #if BYTE_ORDER == LITTLE_ENDIAN
2027 uint32_t resource_extent_count:16,
2028 resource_extent_size:16;
2029 #else
2030 #error big endian version not defined
2031 #endif
2032 } sli4_res_common_get_resource_extent_info_t;
2033
2034
2035 #define SLI4_128BYTE_WQE_SUPPORT 0x02
2036 /**
2037 * @brief COMMON_GET_SLI4_PARAMETERS
2038 */
2039 typedef struct sli4_res_common_get_sli4_parameters_s {
2040 sli4_res_hdr_t hdr;
2041 #if BYTE_ORDER == LITTLE_ENDIAN
2042 uint32_t protocol_type:8,
2043 :24;
2044 uint32_t ft:1,
2045 :3,
2046 sli_revision:4,
2047 sli_family:4,
2048 if_type:4,
2049 sli_hint_1:8,
2050 sli_hint_2:5,
2051 :3;
2052 uint32_t eq_page_cnt:4,
2053 :4,
2054 eqe_sizes:4,
2055 :4,
2056 eq_page_sizes:8,
2057 eqe_count_method:4,
2058 :4;
2059 uint32_t eqe_count_mask:16,
2060 :16;
2061 uint32_t cq_page_cnt:4,
2062 :4,
2063 cqe_sizes:4,
2064 :2,
2065 cqv:2,
2066 cq_page_sizes:8,
2067 cqe_count_method:4,
2068 :4;
2069 uint32_t cqe_count_mask:16,
2070 :16;
2071 uint32_t mq_page_cnt:4,
2072 :10,
2073 mqv:2,
2074 mq_page_sizes:8,
2075 mqe_count_method:4,
2076 :4;
2077 uint32_t mqe_count_mask:16,
2078 :16;
2079 uint32_t wq_page_cnt:4,
2080 :4,
2081 wqe_sizes:4,
2082 :2,
2083 wqv:2,
2084 wq_page_sizes:8,
2085 wqe_count_method:4,
2086 :4;
2087 uint32_t wqe_count_mask:16,
2088 :16;
2089 uint32_t rq_page_cnt:4,
2090 :4,
2091 rqe_sizes:4,
2092 :2,
2093 rqv:2,
2094 rq_page_sizes:8,
2095 rqe_count_method:4,
2096 :4;
2097 uint32_t rqe_count_mask:16,
2098 :12,
2099 rq_db_window:4;
2100 uint32_t fcoe:1,
2101 ext:1,
2102 hdrr:1,
2103 sglr:1,
2104 fbrr:1,
2105 areg:1,
2106 tgt:1,
2107 terp:1,
2108 assi:1,
2109 wchn:1,
2110 tcca:1,
2111 trty:1,
2112 trir:1,
2113 phoff:1,
2114 phon:1,
2115 phwq:1, /** Performance Hint WQ_ID Association */
2116 boundary_4ga:1,
2117 rxc:1,
2118 hlm:1,
2119 ipr:1,
2120 rxri:1,
2121 sglc:1,
2122 timm:1,
2123 tsmm:1,
2124 :1,
2125 oas:1,
2126 lc:1,
2127 agxf:1,
2128 loopback_scope:4;
2129 uint32_t sge_supported_length;
2130 uint32_t sgl_page_cnt:4,
2131 :4,
2132 sgl_page_sizes:8,
2133 sgl_pp_align:8,
2134 :8;
2135 uint32_t min_rq_buffer_size:16,
2136 :16;
2137 uint32_t max_rq_buffer_size;
2138 uint32_t physical_xri_max:16,
2139 physical_rpi_max:16;
2140 uint32_t physical_vpi_max:16,
2141 physical_vfi_max:16;
2142 uint32_t rsvd19;
2143 uint32_t frag_num_field_offset:16, /* dword 20 */
2144 frag_num_field_size:16;
2145 uint32_t sgl_index_field_offset:16, /* dword 21 */
2146 sgl_index_field_size:16;
2147 uint32_t chain_sge_initial_value_lo; /* dword 22 */
2148 uint32_t chain_sge_initial_value_hi; /* dword 23 */
2149 #else
2150 #error big endian version not defined
2151 #endif
2152 } sli4_res_common_get_sli4_parameters_t;
2153
2154
2155 /**
2156 * @brief COMMON_QUERY_FW_CONFIG
2157 *
2158 * This command retrieves firmware configuration parameters and adapter
2159 * resources available to the driver.
2160 */
2161 typedef struct sli4_req_common_query_fw_config_s {
2162 sli4_req_hdr_t hdr;
2163 } sli4_req_common_query_fw_config_t;
2164
2165
2166 #define SLI4_FUNCTION_MODE_FCOE_INI_MODE 0x40
2167 #define SLI4_FUNCTION_MODE_FCOE_TGT_MODE 0x80
2168 #define SLI4_FUNCTION_MODE_DUA_MODE 0x800
2169
2170 #define SLI4_ULP_MODE_FCOE_INI 0x40
2171 #define SLI4_ULP_MODE_FCOE_TGT 0x80
2172
2173 typedef struct sli4_res_common_query_fw_config_s {
2174 sli4_res_hdr_t hdr;
2175 uint32_t config_number;
2176 uint32_t asic_rev;
2177 uint32_t physical_port;
2178 uint32_t function_mode;
2179 uint32_t ulp0_mode;
2180 uint32_t ulp0_nic_wqid_base;
2181 uint32_t ulp0_nic_wq_total; /* Dword 10 */
2182 uint32_t ulp0_toe_wqid_base;
2183 uint32_t ulp0_toe_wq_total;
2184 uint32_t ulp0_toe_rqid_base;
2185 uint32_t ulp0_toe_rq_total;
2186 uint32_t ulp0_toe_defrqid_base;
2187 uint32_t ulp0_toe_defrq_total;
2188 uint32_t ulp0_lro_rqid_base;
2189 uint32_t ulp0_lro_rq_total;
2190 uint32_t ulp0_iscsi_icd_base;
2191 uint32_t ulp0_iscsi_icd_total; /* Dword 20 */
2192 uint32_t ulp1_mode;
2193 uint32_t ulp1_nic_wqid_base;
2194 uint32_t ulp1_nic_wq_total;
2195 uint32_t ulp1_toe_wqid_base;
2196 uint32_t ulp1_toe_wq_total;
2197 uint32_t ulp1_toe_rqid_base;
2198 uint32_t ulp1_toe_rq_total;
2199 uint32_t ulp1_toe_defrqid_base;
2200 uint32_t ulp1_toe_defrq_total;
2201 uint32_t ulp1_lro_rqid_base; /* Dword 30 */
2202 uint32_t ulp1_lro_rq_total;
2203 uint32_t ulp1_iscsi_icd_base;
2204 uint32_t ulp1_iscsi_icd_total;
2205 uint32_t function_capabilities;
2206 uint32_t ulp0_cq_base;
2207 uint32_t ulp0_cq_total;
2208 uint32_t ulp0_eq_base;
2209 uint32_t ulp0_eq_total;
2210 uint32_t ulp0_iscsi_chain_icd_base;
2211 uint32_t ulp0_iscsi_chain_icd_total; /* Dword 40 */
2212 uint32_t ulp1_iscsi_chain_icd_base;
2213 uint32_t ulp1_iscsi_chain_icd_total;
2214 } sli4_res_common_query_fw_config_t;
2215
2216 /**
2217 * @brief COMMON_GET_PORT_NAME
2218 */
2219 typedef struct sli4_req_common_get_port_name_s {
2220 sli4_req_hdr_t hdr;
2221 #if BYTE_ORDER == LITTLE_ENDIAN
2222 uint32_t pt:2, /* only COMMON_GET_PORT_NAME_V1 */
2223 :30;
2224 #else
2225 #error big endian version not defined
2226 #endif
2227 } sli4_req_common_get_port_name_t;
2228
2229 typedef struct sli4_res_common_get_port_name_s {
2230 sli4_res_hdr_t hdr;
2231 char port_name[4];
2232 } sli4_res_common_get_port_name_t;
2233
2234 /**
2235 * @brief COMMON_WRITE_FLASHROM
2236 */
2237 typedef struct sli4_req_common_write_flashrom_s {
2238 sli4_req_hdr_t hdr;
2239 #if BYTE_ORDER == LITTLE_ENDIAN
2240 uint32_t flash_rom_access_opcode;
2241 uint32_t flash_rom_access_operation_type;
2242 uint32_t data_buffer_size;
2243 uint32_t offset;
2244 uint8_t data_buffer[4];
2245 #else
2246 #error big endian version not defined
2247 #endif
2248 } sli4_req_common_write_flashrom_t;
2249
2250 #define SLI4_MGMT_FLASHROM_OPCODE_FLASH 0x01
2251 #define SLI4_MGMT_FLASHROM_OPCODE_SAVE 0x02
2252 #define SLI4_MGMT_FLASHROM_OPCODE_CLEAR 0x03
2253 #define SLI4_MGMT_FLASHROM_OPCODE_REPORT 0x04
2254 #define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_INFO 0x05
2255 #define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_CRC 0x06
2256 #define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_FLASH 0x07
2257 #define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_SAVE 0x08
2258 #define SLI4_MGMT_PHY_FLASHROM_OPCODE_FLASH 0x09
2259 #define SLI4_MGMT_PHY_FLASHROM_OPCODE_SAVE 0x0a
2260
2261 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI 0x00
2262 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_REDBOOT 0x01
2263 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_BIOS 0x02
2264 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS 0x03
2265 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CONTROL 0x04
2266 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_IPSEC_CFG 0x05
2267 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_INIT_DATA 0x06
2268 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ROM_OFFSET 0x07
2269 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BIOS 0x08
2270 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI_BAK 0x09
2271 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_ACT 0x0a
2272 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BAK 0x0b
2273 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CTRL_P 0x0c
2274 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NCSI 0x0d
2275 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NIC 0x0e
2276 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_DCBX 0x0f
2277 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS_CFG 0x10
2278 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ALL_CFG_DATA 0x11
2279
2280 /**
2281 * @brief COMMON_MANAGE_FAT
2282 */
2283 typedef struct sli4_req_common_manage_fat_s {
2284 sli4_req_hdr_t hdr;
2285 #if BYTE_ORDER == LITTLE_ENDIAN
2286 uint32_t fat_operation;
2287 uint32_t read_log_offset;
2288 uint32_t read_log_length;
2289 uint32_t data_buffer_size;
2290 uint32_t data_buffer; /* response only */
2291 #else
2292 #error big endian version not defined
2293 #endif
2294 } sli4_req_common_manage_fat_t;
2295
2296 /**
2297 * @brief COMMON_GET_EXT_FAT_CAPABILITIES
2298 */
2299 typedef struct sli4_req_common_get_ext_fat_capabilities_s {
2300 sli4_req_hdr_t hdr;
2301 #if BYTE_ORDER == LITTLE_ENDIAN
2302 uint32_t parameter_type;
2303 #else
2304 #error big endian version not defined
2305 #endif
2306 } sli4_req_common_get_ext_fat_capabilities_t;
2307
2308 /**
2309 * @brief COMMON_SET_EXT_FAT_CAPABILITIES
2310 */
2311 typedef struct sli4_req_common_set_ext_fat_capabilities_s {
2312 sli4_req_hdr_t hdr;
2313 #if BYTE_ORDER == LITTLE_ENDIAN
2314 uint32_t maximum_log_entries;
2315 uint32_t log_entry_size;
2316 uint32_t logging_type:8,
2317 maximum_logging_functions:8,
2318 maximum_logging_ports:8,
2319 :8;
2320 uint32_t supported_modes;
2321 uint32_t number_modules;
2322 uint32_t debug_module[14];
2323 #else
2324 #error big endian version not defined
2325 #endif
2326 } sli4_req_common_set_ext_fat_capabilities_t;
2327
2328 /**
2329 * @brief COMMON_EXT_FAT_CONFIGURE_SNAPSHOT
2330 */
2331 typedef struct sli4_req_common_ext_fat_configure_snapshot_s {
2332 sli4_req_hdr_t hdr;
2333 #if BYTE_ORDER == LITTLE_ENDIAN
2334 uint32_t total_log_entries;
2335 #else
2336 #error big endian version not defined
2337 #endif
2338 } sli4_req_common_ext_fat_configure_snapshot_t;
2339
2340 /**
2341 * @brief COMMON_EXT_FAT_RETRIEVE_SNAPSHOT
2342 */
2343 typedef struct sli4_req_common_ext_fat_retrieve_snapshot_s {
2344 sli4_req_hdr_t hdr;
2345 #if BYTE_ORDER == LITTLE_ENDIAN
2346 uint32_t snapshot_mode;
2347 uint32_t start_index;
2348 uint32_t number_log_entries;
2349 #else
2350 #error big endian version not defined
2351 #endif
2352 } sli4_req_common_ext_fat_retrieve_snapshot_t;
2353
2354 typedef struct sli4_res_common_ext_fat_retrieve_snapshot_s {
2355 sli4_res_hdr_t hdr;
2356 #if BYTE_ORDER == LITTLE_ENDIAN
2357 uint32_t number_log_entries;
2358 uint32_t version:8,
2359 physical_port:8,
2360 function_id:16;
2361 uint32_t trace_level;
2362 uint32_t module_mask[2];
2363 uint32_t trace_table_index;
2364 uint32_t timestamp;
2365 uint8_t string_data[16];
2366 uint32_t data[6];
2367 #else
2368 #error big endian version not defined
2369 #endif
2370 } sli4_res_common_ext_fat_retrieve_snapshot_t;
2371
2372 /**
2373 * @brief COMMON_EXT_FAT_READ_STRING_TABLE
2374 */
2375 typedef struct sli4_req_common_ext_fat_read_string_table_s {
2376 sli4_req_hdr_t hdr;
2377 #if BYTE_ORDER == LITTLE_ENDIAN
2378 uint32_t byte_offset;
2379 uint32_t number_bytes;
2380 #else
2381 #error big endian version not defined
2382 #endif
2383 } sli4_req_common_ext_fat_read_string_table_t;
2384
2385 typedef struct sli4_res_common_ext_fat_read_string_table_s {
2386 sli4_res_hdr_t hdr;
2387 #if BYTE_ORDER == LITTLE_ENDIAN
2388 uint32_t number_returned_bytes;
2389 uint32_t number_remaining_bytes;
2390 uint32_t table_data0:8,
2391 :24;
2392 uint8_t table_data[0];
2393 #else
2394 #error big endian version not defined
2395 #endif
2396 } sli4_res_common_ext_fat_read_string_table_t;
2397
2398 /**
2399 * @brief COMMON_READ_TRANSCEIVER_DATA
2400 *
2401 * This command reads SFF transceiver data(Format is defined
2402 * by the SFF-8472 specification).
2403 */
2404 typedef struct sli4_req_common_read_transceiver_data_s {
2405 sli4_req_hdr_t hdr;
2406 #if BYTE_ORDER == LITTLE_ENDIAN
2407 uint32_t page_number;
2408 uint32_t port;
2409 #else
2410 #error big endian version not defined
2411 #endif
2412 } sli4_req_common_read_transceiver_data_t;
2413
2414 typedef struct sli4_res_common_read_transceiver_data_s {
2415 sli4_res_hdr_t hdr;
2416 #if BYTE_ORDER == LITTLE_ENDIAN
2417 uint32_t page_number;
2418 uint32_t port;
2419 uint32_t page_data[32];
2420 uint32_t page_data_2[32];
2421 #else
2422 #error big endian version not defined
2423 #endif
2424 } sli4_res_common_read_transceiver_data_t;
2425
2426 /**
2427 * @brief COMMON_READ_OBJECT
2428 */
2429 typedef struct sli4_req_common_read_object_s {
2430 sli4_req_hdr_t hdr;
2431 #if BYTE_ORDER == LITTLE_ENDIAN
2432 uint32_t desired_read_length:24,
2433 :8;
2434 uint32_t read_offset;
2435 uint8_t object_name[104];
2436 uint32_t host_buffer_descriptor_count;
2437 sli4_bde_t host_buffer_descriptor[0];
2438 #else
2439 #error big endian version not defined
2440 #endif
2441 } sli4_req_common_read_object_t;
2442
2443 typedef struct sli4_res_common_read_object_s {
2444 sli4_res_hdr_t hdr;
2445 #if BYTE_ORDER == LITTLE_ENDIAN
2446 uint32_t actual_read_length;
2447 uint32_t resv:31,
2448 eof:1;
2449 #else
2450 #error big endian version not defined
2451 #endif
2452 } sli4_res_common_read_object_t;
2453
2454 /**
2455 * @brief COMMON_WRITE_OBJECT
2456 */
2457 typedef struct sli4_req_common_write_object_s {
2458 sli4_req_hdr_t hdr;
2459 #if BYTE_ORDER == LITTLE_ENDIAN
2460 uint32_t desired_write_length:24,
2461 :6,
2462 noc:1,
2463 eof:1;
2464 uint32_t write_offset;
2465 uint8_t object_name[104];
2466 uint32_t host_buffer_descriptor_count;
2467 sli4_bde_t host_buffer_descriptor[0];
2468 #else
2469 #error big endian version not defined
2470 #endif
2471 } sli4_req_common_write_object_t;
2472
2473 typedef struct sli4_res_common_write_object_s {
2474 sli4_res_hdr_t hdr;
2475 #if BYTE_ORDER == LITTLE_ENDIAN
2476 uint32_t actual_write_length;
2477 uint32_t change_status:8,
2478 :24;
2479 #else
2480 #error big endian version not defined
2481 #endif
2482 } sli4_res_common_write_object_t;
2483
2484 /**
2485 * @brief COMMON_DELETE_OBJECT
2486 */
2487 typedef struct sli4_req_common_delete_object_s {
2488 sli4_req_hdr_t hdr;
2489 #if BYTE_ORDER == LITTLE_ENDIAN
2490 uint32_t rsvd4;
2491 uint32_t rsvd5;
2492 uint8_t object_name[104];
2493 #else
2494 #error big endian version not defined
2495 #endif
2496 } sli4_req_common_delete_object_t;
2497
2498 /**
2499 * @brief COMMON_READ_OBJECT_LIST
2500 */
2501 typedef struct sli4_req_common_read_object_list_s {
2502 sli4_req_hdr_t hdr;
2503 #if BYTE_ORDER == LITTLE_ENDIAN
2504 uint32_t desired_read_length:24,
2505 :8;
2506 uint32_t read_offset;
2507 uint8_t object_name[104];
2508 uint32_t host_buffer_descriptor_count;
2509 sli4_bde_t host_buffer_descriptor[0];
2510 #else
2511 #error big endian version not defined
2512 #endif
2513 } sli4_req_common_read_object_list_t;
2514
2515 /**
2516 * @brief COMMON_SET_DUMP_LOCATION
2517 */
2518 typedef struct sli4_req_common_set_dump_location_s {
2519 sli4_req_hdr_t hdr;
2520 #if BYTE_ORDER == LITTLE_ENDIAN
2521 uint32_t buffer_length:24,
2522 :5,
2523 fdb:1,
2524 blp:1,
2525 qry:1;
2526 uint32_t buf_addr_low;
2527 uint32_t buf_addr_high;
2528 #else
2529 #error big endian version not defined
2530 #endif
2531 } sli4_req_common_set_dump_location_t;
2532
2533 typedef struct sli4_res_common_set_dump_location_s {
2534 sli4_res_hdr_t hdr;
2535 #if BYTE_ORDER == LITTLE_ENDIAN
2536 uint32_t buffer_length:24,
2537 :8;
2538 #else
2539 #error big endian version not defined
2540 #endif
2541 }sli4_res_common_set_dump_location_t;
2542
2543 /**
2544 * @brief COMMON_SET_SET_FEATURES
2545 */
2546 #define SLI4_SET_FEATURES_DIF_SEED 0x01
2547 #define SLI4_SET_FEATURES_XRI_TIMER 0x03
2548 #define SLI4_SET_FEATURES_MAX_PCIE_SPEED 0x04
2549 #define SLI4_SET_FEATURES_FCTL_CHECK 0x05
2550 #define SLI4_SET_FEATURES_FEC 0x06
2551 #define SLI4_SET_FEATURES_PCIE_RECV_DETECT 0x07
2552 #define SLI4_SET_FEATURES_DIF_MEMORY_MODE 0x08
2553 #define SLI4_SET_FEATURES_DISABLE_SLI_PORT_PAUSE_STATE 0x09
2554 #define SLI4_SET_FEATURES_ENABLE_PCIE_OPTIONS 0x0A
2555 #define SLI4_SET_FEATURES_SET_CONFIG_AUTO_XFER_RDY_T10PI 0x0C
2556 #define SLI4_SET_FEATURES_ENABLE_MULTI_RECEIVE_QUEUE 0x0D
2557 #define SLI4_SET_FEATURES_SET_FTD_XFER_HINT 0x0F
2558 #define SLI4_SET_FEATURES_SLI_PORT_HEALTH_CHECK 0x11
2559 #define SLI4_SET_FEATURES_PERSISTENT_TOPOLOGY 0x20
2560
2561 typedef struct sli4_req_common_set_features_s {
2562 sli4_req_hdr_t hdr;
2563 #if BYTE_ORDER == LITTLE_ENDIAN
2564 uint32_t feature;
2565 uint32_t param_len;
2566 uint32_t params[8];
2567 #else
2568 #error big endian version not defined
2569 #endif
2570 } sli4_req_common_set_features_t;
2571
2572 typedef struct sli4_req_common_set_features_dif_seed_s {
2573 #if BYTE_ORDER == LITTLE_ENDIAN
2574 uint32_t seed:16,
2575 :16;
2576 #else
2577 #error big endian version not defined
2578 #endif
2579 } sli4_req_common_set_features_dif_seed_t;
2580
2581 typedef struct sli4_req_common_set_features_t10_pi_mem_model_s {
2582 #if BYTE_ORDER == LITTLE_ENDIAN
2583 uint32_t tmm:1,
2584 :31;
2585 #else
2586 #error big endian version not defined
2587 #endif
2588 } sli4_req_common_set_features_t10_pi_mem_model_t;
2589
2590 typedef struct sli4_req_common_set_features_multirq_s {
2591 #if BYTE_ORDER == LITTLE_ENDIAN
2592 uint32_t isr:1, /*<< Include Sequence Reporting */
2593 agxfe:1, /*<< Auto Generate XFER-RDY Feature Enabled */
2594 :30;
2595 uint32_t num_rqs:8,
2596 rq_select_policy:4,
2597 :20;
2598 #else
2599 #error big endian version not defined
2600 #endif
2601 } sli4_req_common_set_features_multirq_t;
2602
2603 typedef struct sli4_req_common_set_features_xfer_rdy_t10pi_s {
2604 #if BYTE_ORDER == LITTLE_ENDIAN
2605 uint32_t rtc:1,
2606 atv:1,
2607 tmm:1,
2608 :1,
2609 p_type:3,
2610 blk_size:3,
2611 :22;
2612 uint32_t app_tag:16,
2613 :16;
2614 #else
2615 #error big endian version not defined
2616 #endif
2617 } sli4_req_common_set_features_xfer_rdy_t10pi_t;
2618
2619 typedef struct sli4_req_common_set_features_health_check_s {
2620 #if BYTE_ORDER == LITTLE_ENDIAN
2621 uint32_t hck:1,
2622 qry:1,
2623 :30;
2624 #else
2625 #error big endian version not defined
2626 #endif
2627 } sli4_req_common_set_features_health_check_t;
2628
2629 typedef struct sli4_req_common_set_features_set_fdt_xfer_hint_s {
2630 #if BYTE_ORDER == LITTLE_ENDIAN
2631 uint32_t fdt_xfer_hint;
2632 #else
2633 #error big endian version not defined
2634 #endif
2635 } sli4_req_common_set_features_set_fdt_xfer_hint_t;
2636
2637 typedef struct sli4_req_common_set_features_persistent_topo_param_s {
2638 #if BYTE_ORDER == LITTLE_ENDIAN
2639 uint32_t persistent_topo:2,
2640 topo_failover:1,
2641 :29;
2642 #else
2643 #error big endian version not defined
2644 #endif
2645 } sli4_req_common_set_features_persistent_topo_param_t;
2646
2647 /**
2648 * @brief DMTF_EXEC_CLP_CMD
2649 */
2650 typedef struct sli4_req_dmtf_exec_clp_cmd_s {
2651 sli4_req_hdr_t hdr;
2652 #if BYTE_ORDER == LITTLE_ENDIAN
2653 uint32_t cmd_buf_length;
2654 uint32_t resp_buf_length;
2655 uint32_t cmd_buf_addr_low;
2656 uint32_t cmd_buf_addr_high;
2657 uint32_t resp_buf_addr_low;
2658 uint32_t resp_buf_addr_high;
2659 #else
2660 #error big endian version not defined
2661 #endif
2662 } sli4_req_dmtf_exec_clp_cmd_t;
2663
2664 typedef struct sli4_res_dmtf_exec_clp_cmd_s {
2665 sli4_res_hdr_t hdr;
2666 #if BYTE_ORDER == LITTLE_ENDIAN
2667 uint32_t :32;
2668 uint32_t resp_length;
2669 uint32_t :32;
2670 uint32_t :32;
2671 uint32_t :32;
2672 uint32_t :32;
2673 uint32_t clp_status;
2674 uint32_t clp_detailed_status;
2675 #else
2676 #error big endian version not defined
2677 #endif
2678 } sli4_res_dmtf_exec_clp_cmd_t;
2679
2680 /**
2681 * @brief Resource descriptor
2682 */
2683
2684 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_PCIE 0x50
2685 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_NIC 0x51
2686 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISCSI 0x52
2687 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_FCFCOE 0x53
2688 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_RDMA 0x54
2689 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_PORT 0x55
2690 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISAP 0x56
2691
2692 #define SLI4_PROTOCOL_NIC_TOE 0x01
2693 #define SLI4_PROTOCOL_ISCSI 0x02
2694 #define SLI4_PROTOCOL_FCOE 0x04
2695 #define SLI4_PROTOCOL_NIC_TOE_RDMA 0x08
2696 #define SLI4_PROTOCOL_FC 0x10
2697 #define SLI4_PROTOCOL_DEFAULT 0xff
2698
2699 typedef struct sli4_resource_descriptor_v1_s {
2700 uint32_t descriptor_type:8,
2701 descriptor_length:8,
2702 :16;
2703 uint32_t type_specific[0];
2704 } sli4_resource_descriptor_v1_t;
2705
2706 typedef struct sli4_pcie_resource_descriptor_v1_s {
2707 uint32_t descriptor_type:8,
2708 descriptor_length:8,
2709 :14,
2710 imm:1,
2711 nosv:1;
2712 uint32_t :16,
2713 pf_number:10,
2714 :6;
2715 uint32_t rsvd1;
2716 uint32_t sriov_state:8,
2717 pf_state:8,
2718 pf_type:8,
2719 :8;
2720 uint32_t number_of_vfs:16,
2721 :16;
2722 uint32_t mission_roles:8,
2723 :19,
2724 pchg:1,
2725 schg:1,
2726 xchg:1,
2727 xrom:2;
2728 uint32_t rsvd2[16];
2729 } sli4_pcie_resource_descriptor_v1_t;
2730
2731 typedef struct sli4_isap_resource_descriptor_v1_s {
2732 uint32_t descriptor_type:8,
2733 descriptor_length:8,
2734 :16;
2735 uint32_t iscsi_tgt:1,
2736 iscsi_ini:1,
2737 iscsi_dif:1,
2738 :29;
2739 uint32_t rsvd1[3];
2740 uint32_t fcoe_tgt:1,
2741 fcoe_ini:1,
2742 fcoe_dif:1,
2743 :29;
2744 uint32_t rsvd2[7];
2745 uint32_t mc_type0:8,
2746 mc_type1:8,
2747 mc_type2:8,
2748 mc_type3:8;
2749 uint32_t rsvd3[3];
2750 } sli4_isap_resouce_descriptor_v1_t;
2751
2752 /**
2753 * @brief COMMON_GET_FUNCTION_CONFIG
2754 */
2755 typedef struct sli4_req_common_get_function_config_s {
2756 sli4_req_hdr_t hdr;
2757 } sli4_req_common_get_function_config_t;
2758
2759 typedef struct sli4_res_common_get_function_config_s {
2760 sli4_res_hdr_t hdr;
2761 #if BYTE_ORDER == LITTLE_ENDIAN
2762 uint32_t desc_count;
2763 uint32_t desc[54];
2764 #else
2765 #error big endian version not defined
2766 #endif
2767 } sli4_res_common_get_function_config_t;
2768
2769 /**
2770 * @brief COMMON_GET_PROFILE_CONFIG
2771 */
2772 typedef struct sli4_req_common_get_profile_config_s {
2773 sli4_req_hdr_t hdr;
2774 uint32_t profile_id:8,
2775 typ:2,
2776 :22;
2777 } sli4_req_common_get_profile_config_t;
2778
2779 typedef struct sli4_res_common_get_profile_config_s {
2780 sli4_res_hdr_t hdr;
2781 #if BYTE_ORDER == LITTLE_ENDIAN
2782 uint32_t desc_count;
2783 uint32_t desc[0];
2784 #else
2785 #error big endian version not defined
2786 #endif
2787 } sli4_res_common_get_profile_config_t;
2788
2789 /**
2790 * @brief COMMON_SET_PROFILE_CONFIG
2791 */
2792 typedef struct sli4_req_common_set_profile_config_s {
2793 sli4_req_hdr_t hdr;
2794 uint32_t profile_id:8,
2795 :23,
2796 isap:1;
2797 uint32_t desc_count;
2798 uint32_t desc[0];
2799 } sli4_req_common_set_profile_config_t;
2800
2801 typedef struct sli4_res_common_set_profile_config_s {
2802 sli4_res_hdr_t hdr;
2803 #if BYTE_ORDER == LITTLE_ENDIAN
2804 #else
2805 #error big endian version not defined
2806 #endif
2807 } sli4_res_common_set_profile_config_t;
2808
2809 /**
2810 * @brief Profile Descriptor for profile functions
2811 */
2812 typedef struct sli4_profile_descriptor_s {
2813 #if BYTE_ORDER == LITTLE_ENDIAN
2814 uint32_t profile_id:8,
2815 :8,
2816 profile_index:8,
2817 :8;
2818 uint32_t profile_description[128];
2819 #else
2820 #error big endian version not defined
2821 #endif
2822 } sli4_profile_descriptor_t;
2823
2824 /* We don't know in advance how many descriptors there are. We have
2825 to pick a number that we think will be big enough and ask for that
2826 many. */
2827
2828 #define MAX_PRODUCT_DESCRIPTORS 40
2829
2830 /**
2831 * @brief COMMON_GET_PROFILE_LIST
2832 */
2833 typedef struct sli4_req_common_get_profile_list_s {
2834 sli4_req_hdr_t hdr;
2835 #if BYTE_ORDER == LITTLE_ENDIAN
2836 uint32_t start_profile_index:8,
2837 :24;
2838 #else
2839 #error big endian version not defined
2840 #endif
2841 } sli4_req_common_get_profile_list_t;
2842
2843 typedef struct sli4_res_common_get_profile_list_s {
2844 sli4_res_hdr_t hdr;
2845 #if BYTE_ORDER == LITTLE_ENDIAN
2846 uint32_t profile_descriptor_count;
2847 sli4_profile_descriptor_t profile_descriptor[MAX_PRODUCT_DESCRIPTORS];
2848 #else
2849 #error big endian version not defined
2850 #endif
2851 } sli4_res_common_get_profile_list_t;
2852
2853 /**
2854 * @brief COMMON_GET_ACTIVE_PROFILE
2855 */
2856 typedef struct sli4_req_common_get_active_profile_s {
2857 sli4_req_hdr_t hdr;
2858 } sli4_req_common_get_active_profile_t;
2859
2860 typedef struct sli4_res_common_get_active_profile_s {
2861 sli4_res_hdr_t hdr;
2862 #if BYTE_ORDER == LITTLE_ENDIAN
2863 uint32_t active_profile_id:8,
2864 :8,
2865 next_profile_id:8,
2866 :8;
2867 #else
2868 #error big endian version not defined
2869 #endif
2870 } sli4_res_common_get_active_profile_t;
2871
2872 /**
2873 * @brief COMMON_SET_ACTIVE_PROFILE
2874 */
2875 typedef struct sli4_req_common_set_active_profile_s {
2876 sli4_req_hdr_t hdr;
2877 #if BYTE_ORDER == LITTLE_ENDIAN
2878 uint32_t active_profile_id:8,
2879 :23,
2880 fd:1;
2881 #else
2882 #error big endian version not defined
2883 #endif
2884 } sli4_req_common_set_active_profile_t;
2885
2886 typedef struct sli4_res_common_set_active_profile_s {
2887 sli4_res_hdr_t hdr;
2888 } sli4_res_common_set_active_profile_t;
2889
2890 /**
2891 * @brief Link Config Descriptor for link config functions
2892 */
2893 typedef struct sli4_link_config_descriptor_s {
2894 #if BYTE_ORDER == LITTLE_ENDIAN
2895 uint32_t link_config_id:8,
2896 :24;
2897 uint32_t config_description[8];
2898 #else
2899 #error big endian version not defined
2900 #endif
2901 } sli4_link_config_descriptor_t;
2902
2903 #define MAX_LINK_CONFIG_DESCRIPTORS 10
2904
2905 /**
2906 * @brief COMMON_GET_RECONFIG_LINK_INFO
2907 */
2908 typedef struct sli4_req_common_get_reconfig_link_info_s {
2909 sli4_req_hdr_t hdr;
2910 #if BYTE_ORDER == LITTLE_ENDIAN
2911 #else
2912 #error big endian version not defined
2913 #endif
2914 } sli4_req_common_get_reconfig_link_info_t;
2915
2916 typedef struct sli4_res_common_get_reconfig_link_info_s {
2917 sli4_res_hdr_t hdr;
2918 #if BYTE_ORDER == LITTLE_ENDIAN
2919 uint32_t active_link_config_id:8,
2920 :8,
2921 next_link_config_id:8,
2922 :8;
2923 uint32_t link_configuration_descriptor_count;
2924 sli4_link_config_descriptor_t desc[MAX_LINK_CONFIG_DESCRIPTORS];
2925 #else
2926 #error big endian version not defined
2927 #endif
2928 } sli4_res_common_get_reconfig_link_info_t;
2929
2930 /**
2931 * @brief COMMON_SET_RECONFIG_LINK_ID
2932 */
2933 typedef struct sli4_req_common_set_reconfig_link_id_s {
2934 sli4_req_hdr_t hdr;
2935 #if BYTE_ORDER == LITTLE_ENDIAN
2936 uint32_t next_link_config_id:8,
2937 :23,
2938 fd:1;
2939 #else
2940 #error big endian version not defined
2941 #endif
2942 } sli4_req_common_set_reconfig_link_id_t;
2943
2944 typedef struct sli4_res_common_set_reconfig_link_id_s {
2945 sli4_res_hdr_t hdr;
2946 #if BYTE_ORDER == LITTLE_ENDIAN
2947 #else
2948 #error big endian version not defined
2949 #endif
2950 } sli4_res_common_set_reconfig_link_id_t;
2951
2952
2953 typedef struct sli4_req_lowlevel_set_watchdog_s {
2954 sli4_req_hdr_t hdr;
2955 #if BYTE_ORDER == LITTLE_ENDIAN
2956 uint32_t watchdog_timeout:16,
2957 :16;
2958 #else
2959 #error big endian version not defined
2960 #endif
2961
2962 } sli4_req_lowlevel_set_watchdog_t;
2963
2964
2965 typedef struct sli4_res_lowlevel_set_watchdog_s {
2966 sli4_res_hdr_t hdr;
2967 #if BYTE_ORDER == LITTLE_ENDIAN
2968 uint32_t rsvd;
2969 #else
2970 #error big endian version not defined
2971 #endif
2972 } sli4_res_lowlevel_set_watchdog_t;
2973
2974 /**
2975 * @brief Event Queue Entry
2976 */
2977 typedef struct sli4_eqe_s {
2978 #if BYTE_ORDER == LITTLE_ENDIAN
2979 uint32_t vld:1, /** valid */
2980 major_code:3,
2981 minor_code:12,
2982 resource_id:16;
2983 #else
2984 #error big endian version not defined
2985 #endif
2986 } sli4_eqe_t;
2987
2988 #define SLI4_MAJOR_CODE_STANDARD 0
2989 #define SLI4_MAJOR_CODE_SENTINEL 1
2990
2991 /**
2992 * @brief Mailbox Completion Queue Entry
2993 *
2994 * A CQE generated on the completion of a MQE from a MQ.
2995 */
2996 typedef struct sli4_mcqe_s {
2997 #if BYTE_ORDER == LITTLE_ENDIAN
2998 uint32_t completion_status:16, /** values are protocol specific */
2999 extended_status:16;
3000 uint32_t mqe_tag_low;
3001 uint32_t mqe_tag_high;
3002 uint32_t :27,
3003 con:1, /** consumed - command now being executed */
3004 cmp:1, /** completed - command still executing if clear */
3005 :1,
3006 ae:1, /** async event - this is an ACQE */
3007 val:1; /** valid - contents of CQE are valid */
3008 #else
3009 #error big endian version not defined
3010 #endif
3011 } sli4_mcqe_t;
3012
3013
3014 /**
3015 * @brief Asynchronous Completion Queue Entry
3016 *
3017 * A CQE generated asynchronously in response to the link or other internal events.
3018 */
3019 typedef struct sli4_acqe_s {
3020 #if BYTE_ORDER == LITTLE_ENDIAN
3021 uint32_t event_data[3];
3022 uint32_t :8,
3023 event_code:8,
3024 event_type:8, /** values are protocol specific */
3025 :6,
3026 ae:1, /** async event - this is an ACQE */
3027 val:1; /** valid - contents of CQE are valid */
3028 #else
3029 #error big endian version not defined
3030 #endif
3031 } sli4_acqe_t;
3032
3033 #define SLI4_ACQE_EVENT_CODE_LINK_STATE 0x01
3034 #define SLI4_ACQE_EVENT_CODE_FCOE_FIP 0x02
3035 #define SLI4_ACQE_EVENT_CODE_DCBX 0x03
3036 #define SLI4_ACQE_EVENT_CODE_ISCSI 0x04
3037 #define SLI4_ACQE_EVENT_CODE_GRP_5 0x05
3038 #define SLI4_ACQE_EVENT_CODE_FC_LINK_EVENT 0x10
3039 #define SLI4_ACQE_EVENT_CODE_SLI_PORT_EVENT 0x11
3040 #define SLI4_ACQE_EVENT_CODE_VF_EVENT 0x12
3041 #define SLI4_ACQE_EVENT_CODE_MR_EVENT 0x13
3042
3043 /**
3044 * @brief Register name enums
3045 */
3046 typedef enum {
3047 SLI4_REG_BMBX,
3048 SLI4_REG_EQ_DOORBELL,
3049 SLI4_REG_CQ_DOORBELL,
3050 SLI4_REG_FCOE_RQ_DOORBELL,
3051 SLI4_REG_IO_WQ_DOORBELL,
3052 SLI4_REG_MQ_DOORBELL,
3053 SLI4_REG_PHYSDEV_CONTROL,
3054 SLI4_REG_SLIPORT_CONTROL,
3055 SLI4_REG_SLIPORT_ERROR1,
3056 SLI4_REG_SLIPORT_ERROR2,
3057 SLI4_REG_SLIPORT_SEMAPHORE,
3058 SLI4_REG_SLIPORT_STATUS,
3059 SLI4_REG_UERR_MASK_HI,
3060 SLI4_REG_UERR_MASK_LO,
3061 SLI4_REG_UERR_STATUS_HI,
3062 SLI4_REG_UERR_STATUS_LO,
3063 SLI4_REG_SW_UE_CSR1,
3064 SLI4_REG_SW_UE_CSR2,
3065 SLI4_REG_MAX /* must be last */
3066 } sli4_regname_e;
3067
3068 typedef struct sli4_reg_s {
3069 uint32_t rset;
3070 uint32_t off;
3071 } sli4_reg_t;
3072
3073 typedef enum {
3074 SLI_QTYPE_EQ,
3075 SLI_QTYPE_CQ,
3076 SLI_QTYPE_MQ,
3077 SLI_QTYPE_WQ,
3078 SLI_QTYPE_RQ,
3079 SLI_QTYPE_MAX, /* must be last */
3080 } sli4_qtype_e;
3081
3082 #define SLI_USER_MQ_COUNT 1 /** User specified max mail queues */
3083 #define SLI_MAX_CQ_SET_COUNT 16
3084 #define SLI_MAX_RQ_SET_COUNT 16
3085
3086 typedef enum {
3087 SLI_QENTRY_ASYNC,
3088 SLI_QENTRY_MQ,
3089 SLI_QENTRY_RQ,
3090 SLI_QENTRY_WQ,
3091 SLI_QENTRY_WQ_RELEASE,
3092 SLI_QENTRY_OPT_WRITE_CMD,
3093 SLI_QENTRY_OPT_WRITE_DATA,
3094 SLI_QENTRY_XABT,
3095 SLI_QENTRY_MAX /* must be last */
3096 } sli4_qentry_e;
3097
3098 typedef struct sli4_queue_s {
3099 /* Common to all queue types */
3100 ocs_dma_t dma;
3101 ocs_lock_t lock;
3102 uint32_t index; /** current host entry index */
3103 uint16_t size; /** entry size */
3104 uint16_t length; /** number of entries */
3105 uint16_t n_posted; /** number entries posted */
3106 uint16_t id; /** Port assigned xQ_ID */
3107 uint16_t ulp; /** ULP assigned to this queue */
3108 uint32_t doorbell_offset;/** The offset for the doorbell */
3109 uint16_t doorbell_rset; /** register set for the doorbell */
3110 uint8_t type; /** queue type ie EQ, CQ, ... */
3111 uint32_t proc_limit; /** limit number of CQE processed per iteration */
3112 uint32_t posted_limit; /** number of CQE/EQE to process before ringing doorbell */
3113 uint32_t max_num_processed;
3114 time_t max_process_time;
3115
3116 uint16_t phase; /** For if_type = 6, this value toggle for each iteration
3117 of the queue, a queue entry is valid when a cqe valid
3118 bit matches this value */
3119 /* Type specific gunk */
3120 union {
3121 uint32_t r_idx; /** "read" index (MQ only) */
3122 struct {
3123 uint32_t is_mq:1,/** CQ contains MQ/Async completions */
3124 is_hdr:1,/** is a RQ for packet headers */
3125 rq_batch:1;/** RQ index incremented by 8 */
3126 } flag;
3127 } u;
3128 } sli4_queue_t;
3129
3130 static inline void
sli_queue_lock(sli4_queue_t * q)3131 sli_queue_lock(sli4_queue_t *q)
3132 {
3133 ocs_lock(&q->lock);
3134 }
3135
3136 static inline void
sli_queue_unlock(sli4_queue_t * q)3137 sli_queue_unlock(sli4_queue_t *q)
3138 {
3139 ocs_unlock(&q->lock);
3140 }
3141
3142
3143 #define SLI4_QUEUE_DEFAULT_CQ UINT16_MAX /** Use the default CQ */
3144
3145 #define SLI4_QUEUE_RQ_BATCH 8
3146
3147 typedef enum {
3148 SLI4_CB_LINK,
3149 SLI4_CB_FIP,
3150 SLI4_CB_MAX /* must be last */
3151 } sli4_callback_e;
3152
3153 typedef enum {
3154 SLI_LINK_STATUS_UP,
3155 SLI_LINK_STATUS_DOWN,
3156 SLI_LINK_STATUS_NO_ALPA,
3157 SLI_LINK_STATUS_MAX,
3158 } sli4_link_status_e;
3159
3160 typedef enum {
3161 SLI_LINK_TOPO_NPORT = 1, /** fabric or point-to-point */
3162 SLI_LINK_TOPO_LOOP,
3163 SLI_LINK_TOPO_LOOPBACK_INTERNAL,
3164 SLI_LINK_TOPO_LOOPBACK_EXTERNAL,
3165 SLI_LINK_TOPO_NONE,
3166 SLI_LINK_TOPO_MAX,
3167 } sli4_link_topology_e;
3168
3169 /* TODO do we need both sli4_port_type_e & sli4_link_medium_e */
3170 typedef enum {
3171 SLI_LINK_MEDIUM_ETHERNET,
3172 SLI_LINK_MEDIUM_FC,
3173 SLI_LINK_MEDIUM_MAX,
3174 } sli4_link_medium_e;
3175
3176 typedef struct sli4_link_event_s {
3177 sli4_link_status_e status; /* link up/down */
3178 sli4_link_topology_e topology;
3179 sli4_link_medium_e medium; /* Ethernet / FC */
3180 uint32_t speed; /* Mbps */
3181 uint8_t *loop_map;
3182 uint32_t fc_id;
3183 } sli4_link_event_t;
3184
3185 /**
3186 * @brief Fields retrieved from skyhawk that used used to build chained SGL
3187 */
3188 typedef struct sli4_sgl_chaining_params_s {
3189 uint8_t chaining_capable;
3190 uint16_t frag_num_field_offset;
3191 uint16_t sgl_index_field_offset;
3192 uint64_t frag_num_field_mask;
3193 uint64_t sgl_index_field_mask;
3194 uint32_t chain_sge_initial_value_lo;
3195 uint32_t chain_sge_initial_value_hi;
3196 } sli4_sgl_chaining_params_t;
3197
3198 typedef struct sli4_fip_event_s {
3199 uint32_t type;
3200 uint32_t index; /* FCF index or UINT32_MAX if invalid */
3201 } sli4_fip_event_t;
3202
3203 typedef enum {
3204 SLI_RSRC_FCOE_VFI,
3205 SLI_RSRC_FCOE_VPI,
3206 SLI_RSRC_FCOE_RPI,
3207 SLI_RSRC_FCOE_XRI,
3208 SLI_RSRC_FCOE_FCFI,
3209 SLI_RSRC_MAX /* must be last */
3210 } sli4_resource_e;
3211
3212 typedef enum {
3213 SLI4_PORT_TYPE_FC,
3214 SLI4_PORT_TYPE_NIC,
3215 SLI4_PORT_TYPE_MAX /* must be last */
3216 } sli4_port_type_e;
3217
3218 typedef enum {
3219 SLI4_ASIC_TYPE_BE3 = 1,
3220 SLI4_ASIC_TYPE_SKYHAWK,
3221 SLI4_ASIC_TYPE_LANCER,
3222 SLI4_ASIC_TYPE_CORSAIR,
3223 SLI4_ASIC_TYPE_LANCERG6,
3224 SLI4_ASIC_TYPE_LANCERG7
3225 } sli4_asic_type_e;
3226
3227 typedef enum {
3228 SLI4_ASIC_REV_FPGA = 1,
3229 SLI4_ASIC_REV_A0,
3230 SLI4_ASIC_REV_A1,
3231 SLI4_ASIC_REV_A2,
3232 SLI4_ASIC_REV_A3,
3233 SLI4_ASIC_REV_B0,
3234 SLI4_ASIC_REV_B1,
3235 SLI4_ASIC_REV_C0,
3236 SLI4_ASIC_REV_D0,
3237 } sli4_asic_rev_e;
3238
3239 typedef struct sli4_s {
3240 ocs_os_handle_t os;
3241 sli4_port_type_e port_type;
3242
3243 uint32_t sli_rev; /* SLI revision number */
3244 uint32_t sli_family;
3245 uint32_t if_type; /* SLI Interface type */
3246
3247 sli4_asic_type_e asic_type; /*<< ASIC type */
3248 sli4_asic_rev_e asic_rev; /*<< ASIC revision */
3249 uint32_t physical_port;
3250
3251 struct {
3252 uint16_t e_d_tov;
3253 uint16_t r_a_tov;
3254 uint16_t max_qcount[SLI_QTYPE_MAX];
3255 uint32_t max_qentries[SLI_QTYPE_MAX];
3256 uint16_t count_mask[SLI_QTYPE_MAX];
3257 uint16_t count_method[SLI_QTYPE_MAX];
3258 uint32_t qpage_count[SLI_QTYPE_MAX];
3259 uint16_t link_module_type;
3260 uint8_t rq_batch;
3261 uint16_t rq_min_buf_size;
3262 uint32_t rq_max_buf_size;
3263 uint8_t topology;
3264 uint8_t pt:4,
3265 tf:1,
3266 ptv:1,
3267 :2;
3268 uint8_t wwpn[8];
3269 uint8_t wwnn[8];
3270 uint32_t fw_rev[2];
3271 uint8_t fw_name[2][16];
3272 char ipl_name[16];
3273 uint32_t hw_rev[3];
3274 uint8_t port_number;
3275 char port_name[2];
3276 char bios_version_string[32];
3277 uint8_t dual_ulp_capable;
3278 uint8_t is_ulp_fc[2];
3279 /*
3280 * Tracks the port resources using extents metaphor. For
3281 * devices that don't implement extents (i.e.
3282 * has_extents == FALSE), the code models each resource as
3283 * a single large extent.
3284 */
3285 struct {
3286 uint32_t number; /* number of extents */
3287 uint32_t size; /* number of elements in each extent */
3288 uint32_t n_alloc;/* number of elements allocated */
3289 uint32_t *base;
3290 ocs_bitmap_t *use_map;/* bitmap showing resources in use */
3291 uint32_t map_size;/* number of bits in bitmap */
3292 } extent[SLI_RSRC_MAX];
3293 sli4_features_t features;
3294 uint32_t has_extents:1,
3295 auto_reg:1,
3296 auto_xfer_rdy:1,
3297 hdr_template_req:1,
3298 perf_hint:1,
3299 perf_wq_id_association:1,
3300 cq_create_version:2,
3301 mq_create_version:2,
3302 high_login_mode:1,
3303 sgl_pre_registered:1,
3304 sgl_pre_registration_required:1,
3305 t10_dif_inline_capable:1,
3306 t10_dif_separate_capable:1;
3307 uint32_t sge_supported_length;
3308 uint32_t sgl_page_sizes;
3309 uint32_t max_sgl_pages;
3310 sli4_sgl_chaining_params_t sgl_chaining_params;
3311 size_t wqe_size;
3312 } config;
3313
3314 /*
3315 * Callback functions
3316 */
3317 int32_t (*link)(void *, void *);
3318 void *link_arg;
3319 int32_t (*fip)(void *, void *);
3320 void *fip_arg;
3321
3322 ocs_dma_t bmbx;
3323 #if defined(OCS_INCLUDE_DEBUG)
3324 /* Save pointer to physical memory descriptor for non-embedded SLI_CONFIG
3325 * commands for BMBX dumping purposes */
3326 ocs_dma_t *bmbx_non_emb_pmd;
3327 #endif
3328
3329 struct {
3330 ocs_dma_t data;
3331 uint32_t length;
3332 } vpd;
3333 } sli4_t;
3334
3335 /**
3336 * Get / set parameter functions
3337 */
3338 static inline uint32_t
sli_get_max_rsrc(sli4_t * sli4,sli4_resource_e rsrc)3339 sli_get_max_rsrc(sli4_t *sli4, sli4_resource_e rsrc)
3340 {
3341 if (rsrc >= SLI_RSRC_MAX) {
3342 return 0;
3343 }
3344
3345 return sli4->config.extent[rsrc].size;
3346 }
3347
3348 static inline uint32_t
sli_get_max_queue(sli4_t * sli4,sli4_qtype_e qtype)3349 sli_get_max_queue(sli4_t *sli4, sli4_qtype_e qtype)
3350 {
3351 if (qtype >= SLI_QTYPE_MAX) {
3352 return 0;
3353 }
3354 return sli4->config.max_qcount[qtype];
3355 }
3356
3357 static inline uint32_t
sli_get_max_qentries(sli4_t * sli4,sli4_qtype_e qtype)3358 sli_get_max_qentries(sli4_t *sli4, sli4_qtype_e qtype)
3359 {
3360
3361 return sli4->config.max_qentries[qtype];
3362 }
3363
3364 static inline uint32_t
sli_get_max_sge(sli4_t * sli4)3365 sli_get_max_sge(sli4_t *sli4)
3366 {
3367 return sli4->config.sge_supported_length;
3368 }
3369
3370 static inline uint32_t
sli_get_max_sgl(sli4_t * sli4)3371 sli_get_max_sgl(sli4_t *sli4)
3372 {
3373
3374 if (sli4->config.sgl_page_sizes != 1) {
3375 ocs_log_test(sli4->os, "unsupported SGL page sizes %#x\n",
3376 sli4->config.sgl_page_sizes);
3377 return 0;
3378 }
3379
3380 return ((sli4->config.max_sgl_pages * SLI_PAGE_SIZE) / sizeof(sli4_sge_t));
3381 }
3382
3383 static inline sli4_link_medium_e
sli_get_medium(sli4_t * sli4)3384 sli_get_medium(sli4_t *sli4)
3385 {
3386 switch (sli4->config.topology) {
3387 case SLI4_READ_CFG_TOPO_FCOE:
3388 return SLI_LINK_MEDIUM_ETHERNET;
3389 case SLI4_READ_CFG_TOPO_FC:
3390 case SLI4_READ_CFG_TOPO_FC_DA:
3391 case SLI4_READ_CFG_TOPO_FC_AL:
3392 return SLI_LINK_MEDIUM_FC;
3393 default:
3394 return SLI_LINK_MEDIUM_MAX;
3395 }
3396 }
3397
3398 static inline void
sli_skh_chain_sge_build(sli4_t * sli4,sli4_sge_t * sge,uint32_t xri_index,uint32_t frag_num,uint32_t offset)3399 sli_skh_chain_sge_build(sli4_t *sli4, sli4_sge_t *sge, uint32_t xri_index, uint32_t frag_num, uint32_t offset)
3400 {
3401 sli4_sgl_chaining_params_t *cparms = &sli4->config.sgl_chaining_params;
3402
3403
3404 ocs_memset(sge, 0, sizeof(*sge));
3405 sge->sge_type = SLI4_SGE_TYPE_CHAIN;
3406 sge->buffer_address_high = (uint32_t)cparms->chain_sge_initial_value_hi;
3407 sge->buffer_address_low =
3408 (uint32_t)((cparms->chain_sge_initial_value_lo |
3409 (((uintptr_t)(xri_index & cparms->sgl_index_field_mask)) <<
3410 cparms->sgl_index_field_offset) |
3411 (((uintptr_t)(frag_num & cparms->frag_num_field_mask)) <<
3412 cparms->frag_num_field_offset) |
3413 offset) >> 3);
3414 }
3415
3416 static inline uint32_t
sli_get_sli_rev(sli4_t * sli4)3417 sli_get_sli_rev(sli4_t *sli4)
3418 {
3419 return sli4->sli_rev;
3420 }
3421
3422 static inline uint32_t
sli_get_sli_family(sli4_t * sli4)3423 sli_get_sli_family(sli4_t *sli4)
3424 {
3425 return sli4->sli_family;
3426 }
3427
3428 static inline uint32_t
sli_get_if_type(sli4_t * sli4)3429 sli_get_if_type(sli4_t *sli4)
3430 {
3431 return sli4->if_type;
3432 }
3433
3434 static inline void *
sli_get_wwn_port(sli4_t * sli4)3435 sli_get_wwn_port(sli4_t *sli4)
3436 {
3437 return sli4->config.wwpn;
3438 }
3439
3440 static inline void *
sli_get_wwn_node(sli4_t * sli4)3441 sli_get_wwn_node(sli4_t *sli4)
3442 {
3443 return sli4->config.wwnn;
3444 }
3445
3446 static inline void *
sli_get_vpd(sli4_t * sli4)3447 sli_get_vpd(sli4_t *sli4)
3448 {
3449 return sli4->vpd.data.virt;
3450 }
3451
3452 static inline uint32_t
sli_get_vpd_len(sli4_t * sli4)3453 sli_get_vpd_len(sli4_t *sli4)
3454 {
3455 return sli4->vpd.length;
3456 }
3457
3458 static inline uint32_t
sli_get_fw_revision(sli4_t * sli4,uint32_t which)3459 sli_get_fw_revision(sli4_t *sli4, uint32_t which)
3460 {
3461 return sli4->config.fw_rev[which];
3462 }
3463
3464 static inline void *
sli_get_fw_name(sli4_t * sli4,uint32_t which)3465 sli_get_fw_name(sli4_t *sli4, uint32_t which)
3466 {
3467 return sli4->config.fw_name[which];
3468 }
3469
3470 static inline char *
sli_get_ipl_name(sli4_t * sli4)3471 sli_get_ipl_name(sli4_t *sli4)
3472 {
3473 return sli4->config.ipl_name;
3474 }
3475
3476 static inline uint32_t
sli_get_hw_revision(sli4_t * sli4,uint32_t which)3477 sli_get_hw_revision(sli4_t *sli4, uint32_t which)
3478 {
3479 return sli4->config.hw_rev[which];
3480 }
3481
3482 static inline uint32_t
sli_get_auto_xfer_rdy_capable(sli4_t * sli4)3483 sli_get_auto_xfer_rdy_capable(sli4_t *sli4)
3484 {
3485 return sli4->config.auto_xfer_rdy;
3486 }
3487
3488 static inline uint32_t
sli_get_dif_capable(sli4_t * sli4)3489 sli_get_dif_capable(sli4_t *sli4)
3490 {
3491 return sli4->config.features.flag.dif;
3492 }
3493
3494 static inline uint32_t
sli_is_dif_inline_capable(sli4_t * sli4)3495 sli_is_dif_inline_capable(sli4_t *sli4)
3496 {
3497 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_inline_capable;
3498 }
3499
3500 static inline uint32_t
sli_is_dif_separate_capable(sli4_t * sli4)3501 sli_is_dif_separate_capable(sli4_t *sli4)
3502 {
3503 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_separate_capable;
3504 }
3505
3506 static inline uint32_t
sli_get_is_dual_ulp_capable(sli4_t * sli4)3507 sli_get_is_dual_ulp_capable(sli4_t *sli4)
3508 {
3509 return sli4->config.dual_ulp_capable;
3510 }
3511
3512 static inline uint32_t
sli_get_is_sgl_chaining_capable(sli4_t * sli4)3513 sli_get_is_sgl_chaining_capable(sli4_t *sli4)
3514 {
3515 return sli4->config.sgl_chaining_params.chaining_capable;
3516 }
3517
3518 static inline uint32_t
sli_get_is_ulp_enabled(sli4_t * sli4,uint16_t ulp)3519 sli_get_is_ulp_enabled(sli4_t *sli4, uint16_t ulp)
3520 {
3521 return sli4->config.is_ulp_fc[ulp];
3522 }
3523
3524 static inline uint32_t
sli_get_hlm_capable(sli4_t * sli4)3525 sli_get_hlm_capable(sli4_t *sli4)
3526 {
3527 return sli4->config.features.flag.hlm;
3528 }
3529
3530 static inline int32_t
sli_set_hlm(sli4_t * sli4,uint32_t value)3531 sli_set_hlm(sli4_t *sli4, uint32_t value)
3532 {
3533 if (value && !sli4->config.features.flag.hlm) {
3534 ocs_log_test(sli4->os, "HLM not supported\n");
3535 return -1;
3536 }
3537
3538 sli4->config.high_login_mode = value != 0 ? TRUE : FALSE;
3539
3540 return 0;
3541 }
3542
3543 static inline uint32_t
sli_get_hlm(sli4_t * sli4)3544 sli_get_hlm(sli4_t *sli4)
3545 {
3546 return sli4->config.high_login_mode;
3547 }
3548
3549 static inline uint32_t
sli_get_sgl_preregister_required(sli4_t * sli4)3550 sli_get_sgl_preregister_required(sli4_t *sli4)
3551 {
3552 return sli4->config.sgl_pre_registration_required;
3553 }
3554
3555 static inline uint32_t
sli_get_sgl_preregister(sli4_t * sli4)3556 sli_get_sgl_preregister(sli4_t *sli4)
3557 {
3558 return sli4->config.sgl_pre_registered;
3559 }
3560
3561 static inline int32_t
sli_set_sgl_preregister(sli4_t * sli4,uint32_t value)3562 sli_set_sgl_preregister(sli4_t *sli4, uint32_t value)
3563 {
3564 if ((value == 0) && sli4->config.sgl_pre_registration_required) {
3565 ocs_log_test(sli4->os, "SGL pre-registration required\n");
3566 return -1;
3567 }
3568
3569 sli4->config.sgl_pre_registered = value != 0 ? TRUE : FALSE;
3570
3571 return 0;
3572 }
3573
3574 static inline sli4_asic_type_e
sli_get_asic_type(sli4_t * sli4)3575 sli_get_asic_type(sli4_t *sli4)
3576 {
3577 return sli4->asic_type;
3578 }
3579
3580 static inline sli4_asic_rev_e
sli_get_asic_rev(sli4_t * sli4)3581 sli_get_asic_rev(sli4_t *sli4)
3582 {
3583 return sli4->asic_rev;
3584 }
3585
3586 static inline int32_t
sli_set_topology(sli4_t * sli4,uint32_t value)3587 sli_set_topology(sli4_t *sli4, uint32_t value)
3588 {
3589 int32_t rc = 0;
3590
3591 switch (value) {
3592 case SLI4_READ_CFG_TOPO_FCOE:
3593 case SLI4_READ_CFG_TOPO_FC:
3594 case SLI4_READ_CFG_TOPO_FC_DA:
3595 case SLI4_READ_CFG_TOPO_FC_AL:
3596 sli4->config.topology = value;
3597 break;
3598 default:
3599 ocs_log_test(sli4->os, "unsupported topology %#x\n", value);
3600 rc = -1;
3601 }
3602
3603 return rc;
3604 }
3605
3606 static inline void
sli_config_persistent_topology(sli4_t * sli4,sli4_req_common_set_features_persistent_topo_param_t * req)3607 sli_config_persistent_topology(sli4_t *sli4, sli4_req_common_set_features_persistent_topo_param_t *req)
3608 {
3609 sli4->config.pt = req->persistent_topo;
3610 sli4->config.tf = req->topo_failover;
3611 }
3612
3613 static inline uint16_t
sli_get_link_module_type(sli4_t * sli4)3614 sli_get_link_module_type(sli4_t *sli4)
3615 {
3616 return sli4->config.link_module_type;
3617 }
3618
3619 static inline char *
sli_get_portnum(sli4_t * sli4)3620 sli_get_portnum(sli4_t *sli4)
3621 {
3622 return sli4->config.port_name;
3623 }
3624
3625 static inline char *
sli_get_bios_version_string(sli4_t * sli4)3626 sli_get_bios_version_string(sli4_t *sli4)
3627 {
3628 return sli4->config.bios_version_string;
3629 }
3630
3631 static inline uint32_t
sli_convert_mask_to_count(uint32_t method,uint32_t mask)3632 sli_convert_mask_to_count(uint32_t method, uint32_t mask)
3633 {
3634 uint32_t count = 0;
3635
3636 if (method) {
3637 count = 1 << ocs_lg2(mask);
3638 count *= 16;
3639 } else {
3640 count = mask;
3641 }
3642
3643 return count;
3644 }
3645
3646 static inline bool
sli_fcal_is_speed_supported(uint32_t link_speed)3647 sli_fcal_is_speed_supported(uint32_t link_speed)
3648 {
3649 if ((link_speed == FC_LINK_SPEED_16G) ||
3650 (link_speed == FC_LINK_SPEED_32G) ||
3651 (link_speed >= FC_LINK_SPEED_AUTO_32_16)) {
3652 ocs_log_err(NULL, "unsupported FC-AL speed (speed_code: %d)\n", link_speed);
3653 return FALSE;
3654 }
3655
3656 return TRUE;
3657 }
3658
3659 /**
3660 * @brief Common Create Queue function prototype
3661 */
3662 typedef int32_t (*sli4_create_q_fn_t)(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t);
3663
3664 /**
3665 * @brief Common Destroy Queue function prototype
3666 */
3667 typedef int32_t (*sli4_destroy_q_fn_t)(sli4_t *, void *, size_t, uint16_t);
3668
3669
3670 /****************************************************************************
3671 * Function prototypes
3672 */
3673 extern int32_t sli_cmd_config_auto_xfer_rdy(sli4_t *, void *, size_t, uint32_t);
3674 extern int32_t sli_cmd_config_auto_xfer_rdy_hp(sli4_t *, void *, size_t, uint32_t, uint32_t, uint32_t);
3675 extern int32_t sli_cmd_config_link(sli4_t *, void *, size_t);
3676 extern int32_t sli_cmd_down_link(sli4_t *, void *, size_t);
3677 extern int32_t sli_cmd_dump_type4(sli4_t *, void *, size_t, uint16_t);
3678 extern int32_t sli_cmd_common_read_transceiver_data(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *);
3679 extern int32_t sli_cmd_read_link_stats(sli4_t *, void *, size_t,uint8_t, uint8_t, uint8_t);
3680 extern int32_t sli_cmd_read_status(sli4_t *sli4, void *buf, size_t size, uint8_t clear_counters);
3681 extern int32_t sli_cmd_init_link(sli4_t *, void *, size_t, uint32_t, uint8_t);
3682 extern int32_t sli_cmd_init_vfi(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t);
3683 extern int32_t sli_cmd_init_vpi(sli4_t *, void *, size_t, uint16_t, uint16_t);
3684 extern int32_t sli_cmd_post_xri(sli4_t *, void *, size_t, uint16_t, uint16_t);
3685 extern int32_t sli_cmd_release_xri(sli4_t *, void *, size_t, uint8_t);
3686 extern int32_t sli_cmd_read_sparm64(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t);
3687 extern int32_t sli_cmd_read_topology(sli4_t *, void *, size_t, ocs_dma_t *);
3688 extern int32_t sli_cmd_read_nvparms(sli4_t *, void *, size_t);
3689 extern int32_t sli_cmd_write_nvparms(sli4_t *, void *, size_t, uint8_t *, uint8_t *, uint8_t, uint32_t);
3690 typedef struct {
3691 uint16_t rq_id;
3692 uint8_t r_ctl_mask;
3693 uint8_t r_ctl_match;
3694 uint8_t type_mask;
3695 uint8_t type_match;
3696 } sli4_cmd_rq_cfg_t;
3697 extern int32_t sli_cmd_reg_fcfi(sli4_t *, void *, size_t, uint16_t,
3698 sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG], uint16_t);
3699 extern int32_t sli_cmd_reg_fcfi_mrq(sli4_t *, void *, size_t, uint8_t, uint16_t, uint16_t, uint8_t, uint8_t , uint16_t, sli4_cmd_rq_cfg_t *);
3700
3701 extern int32_t sli_cmd_reg_rpi(sli4_t *, void *, size_t, uint32_t, uint16_t, uint16_t, ocs_dma_t *, uint8_t, uint8_t);
3702 extern int32_t sli_cmd_reg_vfi(sli4_t *, void *, size_t, ocs_domain_t *);
3703 extern int32_t sli_cmd_reg_vpi(sli4_t *, void *, size_t, ocs_sli_port_t *, uint8_t);
3704 extern int32_t sli_cmd_sli_config(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *);
3705 extern int32_t sli_cmd_unreg_fcfi(sli4_t *, void *, size_t, uint16_t);
3706 extern int32_t sli_cmd_unreg_rpi(sli4_t *, void *, size_t, uint16_t, sli4_resource_e, uint32_t);
3707 extern int32_t sli_cmd_unreg_vfi(sli4_t *, void *, size_t, ocs_domain_t *, uint32_t);
3708 extern int32_t sli_cmd_unreg_vpi(sli4_t *, void *, size_t, uint16_t, uint32_t);
3709 extern int32_t sli_cmd_common_nop(sli4_t *, void *, size_t, uint64_t);
3710 extern int32_t sli_cmd_common_get_resource_extent_info(sli4_t *, void *, size_t, uint16_t);
3711 extern int32_t sli_cmd_common_get_sli4_parameters(sli4_t *, void *, size_t);
3712 extern int32_t sli_cmd_common_write_object(sli4_t *, void *, size_t,
3713 uint16_t, uint16_t, uint32_t, uint32_t, char *, ocs_dma_t *);
3714 extern int32_t sli_cmd_common_delete_object(sli4_t *, void *, size_t, char *);
3715 extern int32_t sli_cmd_common_read_object(sli4_t *, void *, size_t, uint32_t,
3716 uint32_t, char *, ocs_dma_t *);
3717 extern int32_t sli_cmd_dmtf_exec_clp_cmd(sli4_t *sli4, void *buf, size_t size,
3718 ocs_dma_t *cmd,
3719 ocs_dma_t *resp);
3720 extern int32_t sli_cmd_common_set_dump_location(sli4_t *sli4, void *buf, size_t size,
3721 uint8_t query, uint8_t is_buffer_list,
3722 ocs_dma_t *buffer, uint8_t fdb);
3723 extern int32_t sli_cmd_common_set_features(sli4_t *, void *, size_t, uint32_t, uint32_t, void*);
3724 extern int32_t sli_cmd_common_get_profile_list(sli4_t *sli4, void *buf,
3725 size_t size, uint32_t start_profile_index, ocs_dma_t *dma);
3726 extern int32_t sli_cmd_common_get_active_profile(sli4_t *sli4, void *buf,
3727 size_t size);
3728 extern int32_t sli_cmd_common_set_active_profile(sli4_t *sli4, void *buf,
3729 size_t size,
3730 uint32_t fd,
3731 uint32_t active_profile_id);
3732 extern int32_t sli_cmd_common_get_reconfig_link_info(sli4_t *sli4, void *buf,
3733 size_t size, ocs_dma_t *dma);
3734 extern int32_t sli_cmd_common_set_reconfig_link_id(sli4_t *sli4, void *buf,
3735 size_t size, ocs_dma_t *dma,
3736 uint32_t fd, uint32_t active_link_config_id);
3737 extern int32_t sli_cmd_common_get_function_config(sli4_t *sli4, void *buf,
3738 size_t size);
3739 extern int32_t sli_cmd_common_get_profile_config(sli4_t *sli4, void *buf,
3740 size_t size, ocs_dma_t *dma);
3741 extern int32_t sli_cmd_common_set_profile_config(sli4_t *sli4, void *buf,
3742 size_t size, ocs_dma_t *dma,
3743 uint8_t profile_id, uint32_t descriptor_count,
3744 uint8_t isap);
3745
3746 extern int32_t sli_cqe_mq(void *);
3747 extern int32_t sli_cqe_async(sli4_t *, void *);
3748
3749 extern int32_t sli_setup(sli4_t *, ocs_os_handle_t, sli4_port_type_e);
3750 extern void sli_calc_max_qentries(sli4_t *sli4);
3751 extern int32_t sli_init(sli4_t *);
3752 extern int32_t sli_reset(sli4_t *);
3753 extern int32_t sli_fw_reset(sli4_t *);
3754 extern int32_t sli_teardown(sli4_t *);
3755 extern int32_t sli_callback(sli4_t *, sli4_callback_e, void *, void *);
3756 extern int32_t sli_bmbx_command(sli4_t *);
3757 extern int32_t __sli_queue_init(sli4_t *, sli4_queue_t *, uint32_t, size_t, uint32_t, uint32_t);
3758 extern int32_t __sli_create_queue(sli4_t *, sli4_queue_t *);
3759 extern int32_t sli_eq_modify_delay(sli4_t *sli4, sli4_queue_t *eq, uint32_t num_eq, uint32_t shift, uint32_t delay_mult);
3760 extern int32_t sli_queue_alloc(sli4_t *, uint32_t, sli4_queue_t *, uint32_t, sli4_queue_t *, uint16_t);
3761 extern int32_t sli_cq_alloc_set(sli4_t *, sli4_queue_t *qs[], uint32_t, uint32_t, sli4_queue_t *eqs[]);
3762 extern int32_t sli_get_queue_entry_size(sli4_t *, uint32_t);
3763 extern int32_t sli_queue_free(sli4_t *, sli4_queue_t *, uint32_t, uint32_t);
3764 extern int32_t sli_queue_reset(sli4_t *, sli4_queue_t *);
3765 extern int32_t sli_queue_is_empty(sli4_t *, sli4_queue_t *);
3766 extern int32_t sli_queue_eq_arm(sli4_t *, sli4_queue_t *, uint8_t);
3767 extern int32_t sli_queue_arm(sli4_t *, sli4_queue_t *, uint8_t);
3768 extern int32_t _sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *);
3769 extern int32_t sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *);
3770 extern int32_t sli_queue_read(sli4_t *, sli4_queue_t *, uint8_t *);
3771 extern int32_t sli_queue_index(sli4_t *, sli4_queue_t *);
3772 extern int32_t _sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *);
3773 extern int32_t sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *);
3774 extern int32_t sli_resource_alloc(sli4_t *, sli4_resource_e, uint32_t *, uint32_t *);
3775 extern int32_t sli_resource_free(sli4_t *, sli4_resource_e, uint32_t);
3776 extern int32_t sli_resource_reset(sli4_t *, sli4_resource_e);
3777 extern int32_t sli_eq_parse(sli4_t *, uint8_t *, uint16_t *);
3778 extern int32_t sli_cq_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *);
3779
3780 extern int32_t sli_raise_ue(sli4_t *, uint8_t);
3781 extern int32_t sli_dump_is_ready(sli4_t *);
3782 extern int32_t sli_dump_is_present(sli4_t *);
3783 extern int32_t sli_reset_required(sli4_t *);
3784 extern int32_t sli_fw_error_status(sli4_t *);
3785 extern int32_t sli_fw_ready(sli4_t *);
3786 extern uint32_t sli_reg_read(sli4_t *, sli4_regname_e);
3787 extern void sli_reg_write(sli4_t *, sli4_regname_e, uint32_t);
3788 extern int32_t sli_link_is_configurable(sli4_t *);
3789
3790 #include "ocs_fcp.h"
3791
3792 /**
3793 * @brief Maximum value for a FCFI
3794 *
3795 * Note that although most commands provide a 16 bit field for the FCFI,
3796 * the FC/FCoE Asynchronous Recived CQE format only provides 6 bits for
3797 * the returned FCFI. Then effectively, the FCFI cannot be larger than
3798 * 1 << 6 or 64.
3799 */
3800 #define SLI4_MAX_FCFI 64
3801
3802 /**
3803 * @brief Maximum value for FCF index
3804 *
3805 * The SLI-4 specification uses a 16 bit field in most places for the FCF
3806 * index, but practically, this value will be much smaller. Arbitrarily
3807 * limit the max FCF index to match the max FCFI value.
3808 */
3809 #define SLI4_MAX_FCF_INDEX SLI4_MAX_FCFI
3810
3811 /*************************************************************************
3812 * SLI-4 FC/FCoE mailbox command formats and definitions.
3813 */
3814
3815 /**
3816 * FC/FCoE opcode (OPC) values.
3817 */
3818 #define SLI4_OPC_FCOE_WQ_CREATE 0x1
3819 #define SLI4_OPC_FCOE_WQ_DESTROY 0x2
3820 #define SLI4_OPC_FCOE_POST_SGL_PAGES 0x3
3821 #define SLI4_OPC_FCOE_RQ_CREATE 0x5
3822 #define SLI4_OPC_FCOE_RQ_DESTROY 0x6
3823 #define SLI4_OPC_FCOE_READ_FCF_TABLE 0x8
3824 #define SLI4_OPC_FCOE_POST_HDR_TEMPLATES 0xb
3825 #define SLI4_OPC_FCOE_REDISCOVER_FCF 0x10
3826
3827 /* Use the default CQ associated with the WQ */
3828 #define SLI4_CQ_DEFAULT 0xffff
3829
3830 typedef struct sli4_physical_page_descriptor_s {
3831 uint32_t low;
3832 uint32_t high;
3833 } sli4_physical_page_descriptor_t;
3834
3835 /**
3836 * @brief FCOE_WQ_CREATE
3837 *
3838 * Create a Work Queue for FC/FCoE use.
3839 */
3840 #define SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES 4
3841
3842 typedef struct sli4_req_fcoe_wq_create_s {
3843 sli4_req_hdr_t hdr;
3844 #if BYTE_ORDER == LITTLE_ENDIAN
3845 uint32_t num_pages:8,
3846 dua:1,
3847 :7,
3848 cq_id:16;
3849 sli4_physical_page_descriptor_t page_physical_address[SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES];
3850 uint32_t bqu:1,
3851 :7,
3852 ulp:8,
3853 :16;
3854 #else
3855 #error big endian version not defined
3856 #endif
3857 } sli4_req_fcoe_wq_create_t;
3858
3859 /**
3860 * @brief FCOE_WQ_CREATE_V1
3861 *
3862 * Create a version 1 Work Queue for FC/FCoE use.
3863 */
3864 typedef struct sli4_req_fcoe_wq_create_v1_s {
3865 sli4_req_hdr_t hdr;
3866 #if BYTE_ORDER == LITTLE_ENDIAN
3867 uint32_t num_pages:16,
3868 cq_id:16;
3869 uint32_t page_size:8,
3870 wqe_size:4,
3871 :4,
3872 wqe_count:16;
3873 uint32_t rsvd6;
3874 sli4_physical_page_descriptor_t page_physical_address[8];
3875 #else
3876 #error big endian version not defined
3877 #endif
3878 } sli4_req_fcoe_wq_create_v1_t;
3879
3880 #define SLI4_FCOE_WQ_CREATE_V1_MAX_PAGES 8
3881
3882 /**
3883 * @brief FCOE_WQ_DESTROY
3884 *
3885 * Destroy an FC/FCoE Work Queue.
3886 */
3887 typedef struct sli4_req_fcoe_wq_destroy_s {
3888 sli4_req_hdr_t hdr;
3889 #if BYTE_ORDER == LITTLE_ENDIAN
3890 uint32_t wq_id:16,
3891 :16;
3892 #else
3893 #error big endian version not defined
3894 #endif
3895 } sli4_req_fcoe_wq_destroy_t;
3896
3897 /**
3898 * @brief FCOE_POST_SGL_PAGES
3899 *
3900 * Register the scatter gather list (SGL) memory and associate it with an XRI.
3901 */
3902 typedef struct sli4_req_fcoe_post_sgl_pages_s {
3903 sli4_req_hdr_t hdr;
3904 #if BYTE_ORDER == LITTLE_ENDIAN
3905 uint32_t xri_start:16,
3906 xri_count:16;
3907 struct {
3908 uint32_t page0_low;
3909 uint32_t page0_high;
3910 uint32_t page1_low;
3911 uint32_t page1_high;
3912 } page_set[10];
3913 #else
3914 #error big endian version not defined
3915 #endif
3916 } sli4_req_fcoe_post_sgl_pages_t;
3917
3918 /**
3919 * @brief FCOE_RQ_CREATE
3920 *
3921 * Create a Receive Queue for FC/FCoE use.
3922 */
3923 typedef struct sli4_req_fcoe_rq_create_s {
3924 sli4_req_hdr_t hdr;
3925 #if BYTE_ORDER == LITTLE_ENDIAN
3926 uint32_t num_pages:16,
3927 dua:1,
3928 bqu:1,
3929 :6,
3930 ulp:8;
3931 uint32_t :16,
3932 rqe_count:4,
3933 :12;
3934 uint32_t rsvd6;
3935 uint32_t buffer_size:16,
3936 cq_id:16;
3937 uint32_t rsvd8;
3938 sli4_physical_page_descriptor_t page_physical_address[8];
3939 #else
3940 #error big endian version not defined
3941 #endif
3942 } sli4_req_fcoe_rq_create_t;
3943
3944 #define SLI4_FCOE_RQ_CREATE_V0_MAX_PAGES 8
3945 #define SLI4_FCOE_RQ_CREATE_V0_MIN_BUF_SIZE 128
3946 #define SLI4_FCOE_RQ_CREATE_V0_MAX_BUF_SIZE 2048
3947
3948 /**
3949 * @brief FCOE_RQ_CREATE_V1
3950 *
3951 * Create a version 1 Receive Queue for FC/FCoE use.
3952 */
3953 typedef struct sli4_req_fcoe_rq_create_v1_s {
3954 sli4_req_hdr_t hdr;
3955 #if BYTE_ORDER == LITTLE_ENDIAN
3956 uint32_t num_pages:16,
3957 :13,
3958 dim:1,
3959 dfd:1,
3960 dnb:1;
3961 uint32_t page_size:8,
3962 rqe_size:4,
3963 :4,
3964 rqe_count:16;
3965 uint32_t rsvd6;
3966 uint32_t :16,
3967 cq_id:16;
3968 uint32_t buffer_size;
3969 sli4_physical_page_descriptor_t page_physical_address[8];
3970 #else
3971 #error big endian version not defined
3972 #endif
3973 } sli4_req_fcoe_rq_create_v1_t;
3974
3975
3976 /**
3977 * @brief FCOE_RQ_CREATE_V2
3978 *
3979 * Create a version 2 Receive Queue for FC/FCoE use.
3980 */
3981 typedef struct sli4_req_fcoe_rq_create_v2_s {
3982 sli4_req_hdr_t hdr;
3983 #if BYTE_ORDER == LITTLE_ENDIAN
3984 uint32_t num_pages:16,
3985 rq_count:8,
3986 :5,
3987 dim:1,
3988 dfd:1,
3989 dnb:1;
3990 uint32_t page_size:8,
3991 rqe_size:4,
3992 :4,
3993 rqe_count:16;
3994 uint32_t hdr_buffer_size:16,
3995 payload_buffer_size:16;
3996 uint32_t base_cq_id:16,
3997 :16;
3998 uint32_t rsvd;
3999 sli4_physical_page_descriptor_t page_physical_address[0];
4000 #else
4001 #error big endian version not defined
4002 #endif
4003 } sli4_req_fcoe_rq_create_v2_t;
4004
4005
4006 #define SLI4_FCOE_RQ_CREATE_V1_MAX_PAGES 8
4007 #define SLI4_FCOE_RQ_CREATE_V1_MIN_BUF_SIZE 64
4008 #define SLI4_FCOE_RQ_CREATE_V1_MAX_BUF_SIZE 2048
4009
4010 #define SLI4_FCOE_RQE_SIZE_8 0x2
4011 #define SLI4_FCOE_RQE_SIZE_16 0x3
4012 #define SLI4_FCOE_RQE_SIZE_32 0x4
4013 #define SLI4_FCOE_RQE_SIZE_64 0x5
4014 #define SLI4_FCOE_RQE_SIZE_128 0x6
4015
4016 #define SLI4_FCOE_RQ_PAGE_SIZE_4096 0x1
4017 #define SLI4_FCOE_RQ_PAGE_SIZE_8192 0x2
4018 #define SLI4_FCOE_RQ_PAGE_SIZE_16384 0x4
4019 #define SLI4_FCOE_RQ_PAGE_SIZE_32768 0x8
4020 #define SLI4_FCOE_RQ_PAGE_SIZE_64536 0x10
4021
4022 #define SLI4_FCOE_RQE_SIZE 8
4023
4024 /**
4025 * @brief FCOE_RQ_DESTROY
4026 *
4027 * Destroy an FC/FCoE Receive Queue.
4028 */
4029 typedef struct sli4_req_fcoe_rq_destroy_s {
4030 sli4_req_hdr_t hdr;
4031 #if BYTE_ORDER == LITTLE_ENDIAN
4032 uint32_t rq_id:16,
4033 :16;
4034 #else
4035 #error big endian version not defined
4036 #endif
4037 } sli4_req_fcoe_rq_destroy_t;
4038
4039 /**
4040 * @brief FCOE_READ_FCF_TABLE
4041 *
4042 * Retrieve a FCF database (also known as a table) entry created by the SLI Port
4043 * during FIP discovery.
4044 */
4045 typedef struct sli4_req_fcoe_read_fcf_table_s {
4046 sli4_req_hdr_t hdr;
4047 #if BYTE_ORDER == LITTLE_ENDIAN
4048 uint32_t fcf_index:16,
4049 :16;
4050 #else
4051 #error big endian version not defined
4052 #endif
4053 } sli4_req_fcoe_read_fcf_table_t;
4054
4055 /* A FCF index of -1 on the request means return the first valid entry */
4056 #define SLI4_FCOE_FCF_TABLE_FIRST (UINT16_MAX)
4057
4058 /**
4059 * @brief FCF table entry
4060 *
4061 * This is the information returned by the FCOE_READ_FCF_TABLE command.
4062 */
4063 typedef struct sli4_fcf_entry_s {
4064 #if BYTE_ORDER == LITTLE_ENDIAN
4065 uint32_t max_receive_size;
4066 uint32_t fip_keep_alive;
4067 uint32_t fip_priority;
4068 uint8_t fcf_mac_address[6];
4069 uint8_t fcf_available;
4070 uint8_t mac_address_provider;
4071 uint8_t fabric_name_id[8];
4072 uint8_t fc_map[3];
4073 uint8_t val:1,
4074 fc:1,
4075 :5,
4076 sol:1;
4077 uint32_t fcf_index:16,
4078 fcf_state:16;
4079 uint8_t vlan_bitmap[512];
4080 uint8_t switch_name[8];
4081 #else
4082 #error big endian version not defined
4083 #endif
4084 } sli4_fcf_entry_t;
4085
4086 /**
4087 * @brief FCOE_READ_FCF_TABLE response.
4088 */
4089 typedef struct sli4_res_fcoe_read_fcf_table_s {
4090 sli4_res_hdr_t hdr;
4091 #if BYTE_ORDER == LITTLE_ENDIAN
4092 uint32_t event_tag;
4093 uint32_t next_index:16,
4094 :16;
4095 sli4_fcf_entry_t fcf_entry;
4096 #else
4097 #error big endian version not defined
4098 #endif
4099 } sli4_res_fcoe_read_fcf_table_t;
4100
4101 /* A next FCF index of -1 in the response means this is the last valid entry */
4102 #define SLI4_FCOE_FCF_TABLE_LAST (UINT16_MAX)
4103
4104
4105 /**
4106 * @brief FCOE_POST_HDR_TEMPLATES
4107 */
4108 typedef struct sli4_req_fcoe_post_hdr_templates_s {
4109 sli4_req_hdr_t hdr;
4110 #if BYTE_ORDER == LITTLE_ENDIAN
4111 uint32_t rpi_offset:16,
4112 page_count:16;
4113 sli4_physical_page_descriptor_t page_descriptor[0];
4114 #else
4115 #error big endian version not defined
4116 #endif
4117 } sli4_req_fcoe_post_hdr_templates_t;
4118
4119 #define SLI4_FCOE_HDR_TEMPLATE_SIZE 64
4120
4121 /**
4122 * @brief FCOE_REDISCOVER_FCF
4123 */
4124 typedef struct sli4_req_fcoe_rediscover_fcf_s {
4125 sli4_req_hdr_t hdr;
4126 #if BYTE_ORDER == LITTLE_ENDIAN
4127 uint32_t fcf_count:16,
4128 :16;
4129 uint32_t rsvd5;
4130 uint16_t fcf_index[16];
4131 #else
4132 #error big endian version not defined
4133 #endif
4134 } sli4_req_fcoe_rediscover_fcf_t;
4135
4136
4137 /**
4138 * Work Queue Entry (WQE) types.
4139 */
4140 #define SLI4_WQE_ABORT 0x0f
4141 #define SLI4_WQE_ELS_REQUEST64 0x8a
4142 #define SLI4_WQE_FCP_IBIDIR64 0xac
4143 #define SLI4_WQE_FCP_IREAD64 0x9a
4144 #define SLI4_WQE_FCP_IWRITE64 0x98
4145 #define SLI4_WQE_FCP_ICMND64 0x9c
4146 #define SLI4_WQE_FCP_TRECEIVE64 0xa1
4147 #define SLI4_WQE_FCP_CONT_TRECEIVE64 0xe5
4148 #define SLI4_WQE_FCP_TRSP64 0xa3
4149 #define SLI4_WQE_FCP_TSEND64 0x9f
4150 #define SLI4_WQE_GEN_REQUEST64 0xc2
4151 #define SLI4_WQE_SEND_FRAME 0xe1
4152 #define SLI4_WQE_XMIT_BCAST64 0X84
4153 #define SLI4_WQE_XMIT_BLS_RSP 0x97
4154 #define SLI4_WQE_ELS_RSP64 0x95
4155 #define SLI4_WQE_XMIT_SEQUENCE64 0x82
4156 #define SLI4_WQE_REQUEUE_XRI 0x93
4157
4158 /**
4159 * WQE command types.
4160 */
4161 #define SLI4_CMD_FCP_IREAD64_WQE 0x00
4162 #define SLI4_CMD_FCP_ICMND64_WQE 0x00
4163 #define SLI4_CMD_FCP_IWRITE64_WQE 0x01
4164 #define SLI4_CMD_FCP_TRECEIVE64_WQE 0x02
4165 #define SLI4_CMD_FCP_TRSP64_WQE 0x03
4166 #define SLI4_CMD_FCP_TSEND64_WQE 0x07
4167 #define SLI4_CMD_GEN_REQUEST64_WQE 0x08
4168 #define SLI4_CMD_XMIT_BCAST64_WQE 0x08
4169 #define SLI4_CMD_XMIT_BLS_RSP64_WQE 0x08
4170 #define SLI4_CMD_ABORT_WQE 0x08
4171 #define SLI4_CMD_XMIT_SEQUENCE64_WQE 0x08
4172 #define SLI4_CMD_REQUEUE_XRI_WQE 0x0A
4173 #define SLI4_CMD_SEND_FRAME_WQE 0x0a
4174
4175 #define SLI4_WQE_SIZE 0x05
4176 #define SLI4_WQE_EXT_SIZE 0x06
4177
4178 #define SLI4_WQE_BYTES (16 * sizeof(uint32_t))
4179 #define SLI4_WQE_EXT_BYTES (32 * sizeof(uint32_t))
4180
4181 /* Mask for ccp (CS_CTL) */
4182 #define SLI4_MASK_CCP 0xfe /* Upper 7 bits of CS_CTL is priority */
4183
4184 /**
4185 * @brief Generic WQE
4186 */
4187 typedef struct sli4_generic_wqe_s {
4188 #if BYTE_ORDER == LITTLE_ENDIAN
4189 uint32_t cmd_spec0_5[6];
4190 uint32_t xri_tag:16,
4191 context_tag:16;
4192 uint32_t :2,
4193 ct:2,
4194 :4,
4195 command:8,
4196 class:3,
4197 :1,
4198 pu:2,
4199 :2,
4200 timer:8;
4201 uint32_t abort_tag;
4202 uint32_t request_tag:16,
4203 :16;
4204 uint32_t ebde_cnt:4,
4205 :3,
4206 len_loc:2,
4207 qosd:1,
4208 :1,
4209 xbl:1,
4210 hlm:1,
4211 iod:1,
4212 dbde:1,
4213 wqes:1,
4214 pri:3,
4215 pv:1,
4216 eat:1,
4217 xc:1,
4218 :1,
4219 ccpe:1,
4220 ccp:8;
4221 uint32_t cmd_type:4,
4222 :3,
4223 wqec:1,
4224 :8,
4225 cq_id:16;
4226 #else
4227 #error big endian version not defined
4228 #endif
4229 } sli4_generic_wqe_t;
4230
4231 /**
4232 * @brief WQE used to abort exchanges.
4233 */
4234 typedef struct sli4_abort_wqe_s {
4235 #if BYTE_ORDER == LITTLE_ENDIAN
4236 uint32_t rsvd0;
4237 uint32_t rsvd1;
4238 uint32_t ext_t_tag;
4239 uint32_t ia:1,
4240 ir:1,
4241 :6,
4242 criteria:8,
4243 :16;
4244 uint32_t ext_t_mask;
4245 uint32_t t_mask;
4246 uint32_t xri_tag:16,
4247 context_tag:16;
4248 uint32_t :2,
4249 ct:2,
4250 :4,
4251 command:8,
4252 class:3,
4253 :1,
4254 pu:2,
4255 :2,
4256 timer:8;
4257 uint32_t t_tag;
4258 uint32_t request_tag:16,
4259 :16;
4260 uint32_t ebde_cnt:4,
4261 :3,
4262 len_loc:2,
4263 qosd:1,
4264 :1,
4265 xbl:1,
4266 :1,
4267 iod:1,
4268 dbde:1,
4269 wqes:1,
4270 pri:3,
4271 pv:1,
4272 eat:1,
4273 xc:1,
4274 :1,
4275 ccpe:1,
4276 ccp:8;
4277 uint32_t cmd_type:4,
4278 :3,
4279 wqec:1,
4280 :8,
4281 cq_id:16;
4282 #else
4283 #error big endian version not defined
4284 #endif
4285 } sli4_abort_wqe_t;
4286
4287 #define SLI4_ABORT_CRITERIA_XRI_TAG 0x01
4288 #define SLI4_ABORT_CRITERIA_ABORT_TAG 0x02
4289 #define SLI4_ABORT_CRITERIA_REQUEST_TAG 0x03
4290 #define SLI4_ABORT_CRITERIA_EXT_ABORT_TAG 0x04
4291
4292 typedef enum {
4293 SLI_ABORT_XRI,
4294 SLI_ABORT_ABORT_ID,
4295 SLI_ABORT_REQUEST_ID,
4296 SLI_ABORT_MAX, /* must be last */
4297 } sli4_abort_type_e;
4298
4299 /**
4300 * @brief WQE used to create an ELS request.
4301 */
4302 typedef struct sli4_els_request64_wqe_s {
4303 sli4_bde_t els_request_payload;
4304 #if BYTE_ORDER == LITTLE_ENDIAN
4305 uint32_t els_request_payload_length;
4306 uint32_t sid:24,
4307 sp:1,
4308 :7;
4309 uint32_t remote_id:24,
4310 :8;
4311 uint32_t xri_tag:16,
4312 context_tag:16;
4313 uint32_t :2,
4314 ct:2,
4315 :4,
4316 command:8,
4317 class:3,
4318 ar:1,
4319 pu:2,
4320 :2,
4321 timer:8;
4322 uint32_t abort_tag;
4323 uint32_t request_tag:16,
4324 temporary_rpi:16;
4325 uint32_t ebde_cnt:4,
4326 :3,
4327 len_loc:2,
4328 qosd:1,
4329 :1,
4330 xbl:1,
4331 hlm:1,
4332 iod:1,
4333 dbde:1,
4334 wqes:1,
4335 pri:3,
4336 pv:1,
4337 eat:1,
4338 xc:1,
4339 :1,
4340 ccpe:1,
4341 ccp:8;
4342 uint32_t cmd_type:4,
4343 els_id:3,
4344 wqec:1,
4345 :8,
4346 cq_id:16;
4347 sli4_bde_t els_response_payload_bde;
4348 uint32_t max_response_payload_length;
4349 #else
4350 #error big endian version not defined
4351 #endif
4352 } sli4_els_request64_wqe_t;
4353
4354 #define SLI4_ELS_REQUEST64_CONTEXT_RPI 0x0
4355 #define SLI4_ELS_REQUEST64_CONTEXT_VPI 0x1
4356 #define SLI4_ELS_REQUEST64_CONTEXT_VFI 0x2
4357 #define SLI4_ELS_REQUEST64_CONTEXT_FCFI 0x3
4358
4359 #define SLI4_ELS_REQUEST64_CLASS_2 0x1
4360 #define SLI4_ELS_REQUEST64_CLASS_3 0x2
4361
4362 #define SLI4_ELS_REQUEST64_DIR_WRITE 0x0
4363 #define SLI4_ELS_REQUEST64_DIR_READ 0x1
4364
4365 #define SLI4_ELS_REQUEST64_OTHER 0x0
4366 #define SLI4_ELS_REQUEST64_LOGO 0x1
4367 #define SLI4_ELS_REQUEST64_FDISC 0x2
4368 #define SLI4_ELS_REQUEST64_FLOGIN 0x3
4369 #define SLI4_ELS_REQUEST64_PLOGI 0x4
4370
4371 #define SLI4_ELS_REQUEST64_CMD_GEN 0x08
4372 #define SLI4_ELS_REQUEST64_CMD_NON_FABRIC 0x0c
4373 #define SLI4_ELS_REQUEST64_CMD_FABRIC 0x0d
4374
4375 /**
4376 * @brief WQE used to create an FCP initiator no data command.
4377 */
4378 typedef struct sli4_fcp_icmnd64_wqe_s {
4379 sli4_bde_t bde;
4380 #if BYTE_ORDER == LITTLE_ENDIAN
4381 uint32_t payload_offset_length:16,
4382 fcp_cmd_buffer_length:16;
4383 uint32_t rsvd4;
4384 uint32_t remote_n_port_id:24,
4385 :8;
4386 uint32_t xri_tag:16,
4387 context_tag:16;
4388 uint32_t dif:2,
4389 ct:2,
4390 bs:3,
4391 :1,
4392 command:8,
4393 class:3,
4394 :1,
4395 pu:2,
4396 erp:1,
4397 lnk:1,
4398 timer:8;
4399 uint32_t abort_tag;
4400 uint32_t request_tag:16,
4401 :16;
4402 uint32_t ebde_cnt:4,
4403 :3,
4404 len_loc:2,
4405 qosd:1,
4406 :1,
4407 xbl:1,
4408 hlm:1,
4409 iod:1,
4410 dbde:1,
4411 wqes:1,
4412 pri:3,
4413 pv:1,
4414 eat:1,
4415 xc:1,
4416 :1,
4417 ccpe:1,
4418 ccp:8;
4419 uint32_t cmd_type:4,
4420 :3,
4421 wqec:1,
4422 :8,
4423 cq_id:16;
4424 uint32_t rsvd12;
4425 uint32_t rsvd13;
4426 uint32_t rsvd14;
4427 uint32_t rsvd15;
4428 #else
4429 #error big endian version not defined
4430 #endif
4431 } sli4_fcp_icmnd64_wqe_t;
4432
4433 /**
4434 * @brief WQE used to create an FCP initiator read.
4435 */
4436 typedef struct sli4_fcp_iread64_wqe_s {
4437 sli4_bde_t bde;
4438 #if BYTE_ORDER == LITTLE_ENDIAN
4439 uint32_t payload_offset_length:16,
4440 fcp_cmd_buffer_length:16;
4441 uint32_t total_transfer_length;
4442 uint32_t remote_n_port_id:24,
4443 :8;
4444 uint32_t xri_tag:16,
4445 context_tag:16;
4446 uint32_t dif:2,
4447 ct:2,
4448 bs:3,
4449 :1,
4450 command:8,
4451 class:3,
4452 :1,
4453 pu:2,
4454 erp:1,
4455 lnk:1,
4456 timer:8;
4457 uint32_t abort_tag;
4458 uint32_t request_tag:16,
4459 :16;
4460 uint32_t ebde_cnt:4,
4461 :3,
4462 len_loc:2,
4463 qosd:1,
4464 :1,
4465 xbl:1,
4466 hlm:1,
4467 iod:1,
4468 dbde:1,
4469 wqes:1,
4470 pri:3,
4471 pv:1,
4472 eat:1,
4473 xc:1,
4474 :1,
4475 ccpe:1,
4476 ccp:8;
4477 uint32_t cmd_type:4,
4478 :3,
4479 wqec:1,
4480 :8,
4481 cq_id:16;
4482 uint32_t rsvd12;
4483 #else
4484 #error big endian version not defined
4485 #endif
4486 sli4_bde_t first_data_bde; /* reserved if performance hints disabled */
4487 } sli4_fcp_iread64_wqe_t;
4488
4489 /**
4490 * @brief WQE used to create an FCP initiator write.
4491 */
4492 typedef struct sli4_fcp_iwrite64_wqe_s {
4493 sli4_bde_t bde;
4494 #if BYTE_ORDER == LITTLE_ENDIAN
4495 uint32_t payload_offset_length:16,
4496 fcp_cmd_buffer_length:16;
4497 uint32_t total_transfer_length;
4498 uint32_t initial_transfer_length;
4499 uint32_t xri_tag:16,
4500 context_tag:16;
4501 uint32_t dif:2,
4502 ct:2,
4503 bs:3,
4504 :1,
4505 command:8,
4506 class:3,
4507 :1,
4508 pu:2,
4509 erp:1,
4510 lnk:1,
4511 timer:8;
4512 uint32_t abort_tag;
4513 uint32_t request_tag:16,
4514 :16;
4515 uint32_t ebde_cnt:4,
4516 :3,
4517 len_loc:2,
4518 qosd:1,
4519 :1,
4520 xbl:1,
4521 hlm:1,
4522 iod:1,
4523 dbde:1,
4524 wqes:1,
4525 pri:3,
4526 pv:1,
4527 eat:1,
4528 xc:1,
4529 :1,
4530 ccpe:1,
4531 ccp:8;
4532 uint32_t cmd_type:4,
4533 :3,
4534 wqec:1,
4535 :8,
4536 cq_id:16;
4537 uint32_t remote_n_port_id:24,
4538 :8;
4539 #else
4540 #error big endian version not defined
4541 #endif
4542 sli4_bde_t first_data_bde;
4543 } sli4_fcp_iwrite64_wqe_t;
4544
4545
4546 typedef struct sli4_fcp_128byte_wqe_s {
4547 uint32_t dw[32];
4548 } sli4_fcp_128byte_wqe_t;
4549
4550 /**
4551 * @brief WQE used to create an FCP target receive, and FCP target
4552 * receive continue.
4553 */
4554 typedef struct sli4_fcp_treceive64_wqe_s {
4555 sli4_bde_t bde;
4556 #if BYTE_ORDER == LITTLE_ENDIAN
4557 uint32_t payload_offset_length;
4558 uint32_t relative_offset;
4559 /**
4560 * DWord 5 can either be the task retry identifier (HLM=0) or
4561 * the remote N_Port ID (HLM=1), or if implementing the Skyhawk
4562 * T10-PI workaround, the secondary xri tag
4563 */
4564 union {
4565 uint32_t sec_xri_tag:16,
4566 :16;
4567 uint32_t dword;
4568 } dword5;
4569 uint32_t xri_tag:16,
4570 context_tag:16;
4571 uint32_t dif:2,
4572 ct:2,
4573 bs:3,
4574 :1,
4575 command:8,
4576 class:3,
4577 ar:1,
4578 pu:2,
4579 conf:1,
4580 lnk:1,
4581 timer:8;
4582 uint32_t abort_tag;
4583 uint32_t request_tag:16,
4584 remote_xid:16;
4585 uint32_t ebde_cnt:4,
4586 :1,
4587 app_id_valid:1,
4588 :1,
4589 len_loc:2,
4590 qosd:1,
4591 wchn:1,
4592 xbl:1,
4593 hlm:1,
4594 iod:1,
4595 dbde:1,
4596 wqes:1,
4597 pri:3,
4598 pv:1,
4599 eat:1,
4600 xc:1,
4601 sr:1,
4602 ccpe:1,
4603 ccp:8;
4604 uint32_t cmd_type:4,
4605 :3,
4606 wqec:1,
4607 :8,
4608 cq_id:16;
4609 uint32_t fcp_data_receive_length;
4610
4611 #else
4612 #error big endian version not defined
4613 #endif
4614 sli4_bde_t first_data_bde; /* For performance hints */
4615
4616 } sli4_fcp_treceive64_wqe_t;
4617
4618 /**
4619 * @brief WQE used to create an FCP target response.
4620 */
4621 typedef struct sli4_fcp_trsp64_wqe_s {
4622 sli4_bde_t bde;
4623 #if BYTE_ORDER == LITTLE_ENDIAN
4624 uint32_t fcp_response_length;
4625 uint32_t rsvd4;
4626 /**
4627 * DWord 5 can either be the task retry identifier (HLM=0) or
4628 * the remote N_Port ID (HLM=1)
4629 */
4630 uint32_t dword5;
4631 uint32_t xri_tag:16,
4632 rpi:16;
4633 uint32_t :2,
4634 ct:2,
4635 dnrx:1,
4636 :3,
4637 command:8,
4638 class:3,
4639 ag:1,
4640 pu:2,
4641 conf:1,
4642 lnk:1,
4643 timer:8;
4644 uint32_t abort_tag;
4645 uint32_t request_tag:16,
4646 remote_xid:16;
4647 uint32_t ebde_cnt:4,
4648 :1,
4649 app_id_valid:1,
4650 :1,
4651 len_loc:2,
4652 qosd:1,
4653 wchn:1,
4654 xbl:1,
4655 hlm:1,
4656 iod:1,
4657 dbde:1,
4658 wqes:1,
4659 pri:3,
4660 pv:1,
4661 eat:1,
4662 xc:1,
4663 sr:1,
4664 ccpe:1,
4665 ccp:8;
4666 uint32_t cmd_type:4,
4667 :3,
4668 wqec:1,
4669 :8,
4670 cq_id:16;
4671 uint32_t rsvd12;
4672 uint32_t rsvd13;
4673 uint32_t rsvd14;
4674 uint32_t rsvd15;
4675 #else
4676 #error big endian version not defined
4677 #endif
4678 } sli4_fcp_trsp64_wqe_t;
4679
4680 /**
4681 * @brief WQE used to create an FCP target send (DATA IN).
4682 */
4683 typedef struct sli4_fcp_tsend64_wqe_s {
4684 sli4_bde_t bde;
4685 #if BYTE_ORDER == LITTLE_ENDIAN
4686 uint32_t payload_offset_length;
4687 uint32_t relative_offset;
4688 /**
4689 * DWord 5 can either be the task retry identifier (HLM=0) or
4690 * the remote N_Port ID (HLM=1)
4691 */
4692 uint32_t dword5;
4693 uint32_t xri_tag:16,
4694 rpi:16;
4695 uint32_t dif:2,
4696 ct:2,
4697 bs:3,
4698 :1,
4699 command:8,
4700 class:3,
4701 ar:1,
4702 pu:2,
4703 conf:1,
4704 lnk:1,
4705 timer:8;
4706 uint32_t abort_tag;
4707 uint32_t request_tag:16,
4708 remote_xid:16;
4709 uint32_t ebde_cnt:4,
4710 :1,
4711 app_id_valid:1,
4712 :1,
4713 len_loc:2,
4714 qosd:1,
4715 wchn:1,
4716 xbl:1,
4717 hlm:1,
4718 iod:1,
4719 dbde:1,
4720 wqes:1,
4721 pri:3,
4722 pv:1,
4723 eat:1,
4724 xc:1,
4725 sr:1,
4726 ccpe:1,
4727 ccp:8;
4728 uint32_t cmd_type:4,
4729 :3,
4730 wqec:1,
4731 :8,
4732 cq_id:16;
4733 uint32_t fcp_data_transmit_length;
4734
4735 #else
4736 #error big endian version not defined
4737 #endif
4738 sli4_bde_t first_data_bde; /* For performance hints */
4739 } sli4_fcp_tsend64_wqe_t;
4740
4741 #define SLI4_IO_CONTINUATION BIT(0) /** The XRI associated with this IO is already active */
4742 #define SLI4_IO_AUTO_GOOD_RESPONSE BIT(1) /** Automatically generate a good RSP frame */
4743 #define SLI4_IO_NO_ABORT BIT(2)
4744 #define SLI4_IO_DNRX BIT(3) /** Set the DNRX bit because no auto xref rdy buffer is posted */
4745
4746 /* WQE DIF field contents */
4747 #define SLI4_DIF_DISABLED 0
4748 #define SLI4_DIF_PASS_THROUGH 1
4749 #define SLI4_DIF_STRIP 2
4750 #define SLI4_DIF_INSERT 3
4751
4752 /**
4753 * @brief WQE used to create a general request.
4754 */
4755 typedef struct sli4_gen_request64_wqe_s {
4756 sli4_bde_t bde;
4757 #if BYTE_ORDER == LITTLE_ENDIAN
4758 uint32_t request_payload_length;
4759 uint32_t relative_offset;
4760 uint32_t :8,
4761 df_ctl:8,
4762 type:8,
4763 r_ctl:8;
4764 uint32_t xri_tag:16,
4765 context_tag:16;
4766 uint32_t :2,
4767 ct:2,
4768 :4,
4769 command:8,
4770 class:3,
4771 :1,
4772 pu:2,
4773 :2,
4774 timer:8;
4775 uint32_t abort_tag;
4776 uint32_t request_tag:16,
4777 :16;
4778 uint32_t ebde_cnt:4,
4779 :3,
4780 len_loc:2,
4781 qosd:1,
4782 :1,
4783 xbl:1,
4784 hlm:1,
4785 iod:1,
4786 dbde:1,
4787 wqes:1,
4788 pri:3,
4789 pv:1,
4790 eat:1,
4791 xc:1,
4792 :1,
4793 ccpe:1,
4794 ccp:8;
4795 uint32_t cmd_type:4,
4796 :3,
4797 wqec:1,
4798 :8,
4799 cq_id:16;
4800 uint32_t remote_n_port_id:24,
4801 :8;
4802 uint32_t rsvd13;
4803 uint32_t rsvd14;
4804 uint32_t max_response_payload_length;
4805 #else
4806 #error big endian version not defined
4807 #endif
4808 } sli4_gen_request64_wqe_t;
4809
4810 /**
4811 * @brief WQE used to create a send frame request.
4812 */
4813 typedef struct sli4_send_frame_wqe_s {
4814 sli4_bde_t bde;
4815 #if BYTE_ORDER == LITTLE_ENDIAN
4816 uint32_t frame_length;
4817 uint32_t fc_header_0_1[2];
4818 uint32_t xri_tag:16,
4819 context_tag:16;
4820 uint32_t :2,
4821 ct:2,
4822 :4,
4823 command:8,
4824 class:3,
4825 :1,
4826 pu:2,
4827 :2,
4828 timer:8;
4829 uint32_t abort_tag;
4830 uint32_t request_tag:16,
4831 eof:8,
4832 sof:8;
4833 uint32_t ebde_cnt:4,
4834 :3,
4835 lenloc:2,
4836 qosd:1,
4837 wchn:1,
4838 xbl:1,
4839 hlm:1,
4840 iod:1,
4841 dbde:1,
4842 wqes:1,
4843 pri:3,
4844 pv:1,
4845 eat:1,
4846 xc:1,
4847 :1,
4848 ccpe:1,
4849 ccp:8;
4850 uint32_t cmd_type:4,
4851 :3,
4852 wqec:1,
4853 :8,
4854 cq_id:16;
4855 uint32_t fc_header_2_5[4];
4856 #else
4857 #error big endian version not defined
4858 #endif
4859 } sli4_send_frame_wqe_t;
4860
4861 /**
4862 * @brief WQE used to create a transmit sequence.
4863 */
4864 typedef struct sli4_xmit_sequence64_wqe_s {
4865 sli4_bde_t bde;
4866 #if BYTE_ORDER == LITTLE_ENDIAN
4867 uint32_t remote_n_port_id:24,
4868 :8;
4869 uint32_t relative_offset;
4870 uint32_t :2,
4871 si:1,
4872 ft:1,
4873 :2,
4874 xo:1,
4875 ls:1,
4876 df_ctl:8,
4877 type:8,
4878 r_ctl:8;
4879 uint32_t xri_tag:16,
4880 context_tag:16;
4881 uint32_t dif:2,
4882 ct:2,
4883 bs:3,
4884 :1,
4885 command:8,
4886 class:3,
4887 :1,
4888 pu:2,
4889 :2,
4890 timer:8;
4891 uint32_t abort_tag;
4892 uint32_t request_tag:16,
4893 remote_xid:16;
4894 uint32_t ebde_cnt:4,
4895 :3,
4896 len_loc:2,
4897 qosd:1,
4898 :1,
4899 xbl:1,
4900 hlm:1,
4901 iod:1,
4902 dbde:1,
4903 wqes:1,
4904 pri:3,
4905 pv:1,
4906 eat:1,
4907 xc:1,
4908 sr:1,
4909 ccpe:1,
4910 ccp:8;
4911 uint32_t cmd_type:4,
4912 :3,
4913 wqec:1,
4914 :8,
4915 cq_id:16;
4916 uint32_t sequence_payload_len;
4917 uint32_t rsvd13;
4918 uint32_t rsvd14;
4919 uint32_t rsvd15;
4920 #else
4921 #error big endian version not defined
4922 #endif
4923 } sli4_xmit_sequence64_wqe_t;
4924
4925 /**
4926 * @brief WQE used unblock the specified XRI and to release it to the SLI Port's free pool.
4927 */
4928 typedef struct sli4_requeue_xri_wqe_s {
4929 uint32_t rsvd0;
4930 uint32_t rsvd1;
4931 uint32_t rsvd2;
4932 uint32_t rsvd3;
4933 uint32_t rsvd4;
4934 uint32_t rsvd5;
4935 #if BYTE_ORDER == LITTLE_ENDIAN
4936 uint32_t xri_tag:16,
4937 context_tag:16;
4938 uint32_t :2,
4939 ct:2,
4940 :4,
4941 command:8,
4942 class:3,
4943 :1,
4944 pu:2,
4945 :2,
4946 timer:8;
4947 uint32_t rsvd8;
4948 uint32_t request_tag:16,
4949 :16;
4950 uint32_t ebde_cnt:4,
4951 :3,
4952 len_loc:2,
4953 qosd:1,
4954 wchn:1,
4955 xbl:1,
4956 hlm:1,
4957 iod:1,
4958 dbde:1,
4959 wqes:1,
4960 pri:3,
4961 pv:1,
4962 eat:1,
4963 xc:1,
4964 :1,
4965 ccpe:1,
4966 ccp:8;
4967 uint32_t cmd_type:4,
4968 :3,
4969 wqec:1,
4970 :8,
4971 cq_id:16;
4972 uint32_t rsvd12;
4973 uint32_t rsvd13;
4974 uint32_t rsvd14;
4975 uint32_t rsvd15;
4976 #else
4977 #error big endian version not defined
4978 #endif
4979 } sli4_requeue_xri_wqe_t;
4980
4981 /**
4982 * @brief WQE used to send a single frame sequence to broadcast address
4983 */
4984 typedef struct sli4_xmit_bcast64_wqe_s {
4985 sli4_bde_t sequence_payload;
4986 #if BYTE_ORDER == LITTLE_ENDIAN
4987 uint32_t sequence_payload_length;
4988 uint32_t rsvd4;
4989 uint32_t :8,
4990 df_ctl:8,
4991 type:8,
4992 r_ctl:8;
4993 uint32_t xri_tag:16,
4994 context_tag:16;
4995 uint32_t :2,
4996 ct:2,
4997 :4,
4998 command:8,
4999 class:3,
5000 :1,
5001 pu:2,
5002 :2,
5003 timer:8;
5004 uint32_t abort_tag;
5005 uint32_t request_tag:16,
5006 temporary_rpi:16;
5007 uint32_t ebde_cnt:4,
5008 :3,
5009 len_loc:2,
5010 qosd:1,
5011 :1,
5012 xbl:1,
5013 hlm:1,
5014 iod:1,
5015 dbde:1,
5016 wqes:1,
5017 pri:3,
5018 pv:1,
5019 eat:1,
5020 xc:1,
5021 :1,
5022 ccpe:1,
5023 ccp:8;
5024 uint32_t cmd_type:4,
5025 :3,
5026 wqec:1,
5027 :8,
5028 cq_id:16;
5029 uint32_t rsvd12;
5030 uint32_t rsvd13;
5031 uint32_t rsvd14;
5032 uint32_t rsvd15;
5033 #else
5034 #error big endian version not defined
5035 #endif
5036 } sli4_xmit_bcast64_wqe_t;
5037
5038 /**
5039 * @brief WQE used to create a BLS response.
5040 */
5041 typedef struct sli4_xmit_bls_rsp_wqe_s {
5042 #if BYTE_ORDER == LITTLE_ENDIAN
5043 uint32_t payload_word0;
5044 uint32_t rx_id:16,
5045 ox_id:16;
5046 uint32_t high_seq_cnt:16,
5047 low_seq_cnt:16;
5048 uint32_t rsvd3;
5049 uint32_t local_n_port_id:24,
5050 :8;
5051 uint32_t remote_id:24,
5052 :6,
5053 ar:1,
5054 xo:1;
5055 uint32_t xri_tag:16,
5056 context_tag:16;
5057 uint32_t :2,
5058 ct:2,
5059 :4,
5060 command:8,
5061 class:3,
5062 :1,
5063 pu:2,
5064 :2,
5065 timer:8;
5066 uint32_t abort_tag;
5067 uint32_t request_tag:16,
5068 :16;
5069 uint32_t ebde_cnt:4,
5070 :3,
5071 len_loc:2,
5072 qosd:1,
5073 :1,
5074 xbl:1,
5075 hlm:1,
5076 iod:1,
5077 dbde:1,
5078 wqes:1,
5079 pri:3,
5080 pv:1,
5081 eat:1,
5082 xc:1,
5083 :1,
5084 ccpe:1,
5085 ccp:8;
5086 uint32_t cmd_type:4,
5087 :3,
5088 wqec:1,
5089 :8,
5090 cq_id:16;
5091 uint32_t temporary_rpi:16,
5092 :16;
5093 uint32_t rsvd13;
5094 uint32_t rsvd14;
5095 uint32_t rsvd15;
5096 #else
5097 #error big endian version not defined
5098 #endif
5099 } sli4_xmit_bls_rsp_wqe_t;
5100
5101 typedef enum {
5102 SLI_BLS_ACC,
5103 SLI_BLS_RJT,
5104 SLI_BLS_MAX
5105 } sli_bls_type_e;
5106
5107 typedef struct sli_bls_payload_s {
5108 sli_bls_type_e type;
5109 uint16_t ox_id;
5110 uint16_t rx_id;
5111 union {
5112 struct {
5113 uint32_t seq_id_validity:8,
5114 seq_id_last:8,
5115 :16;
5116 uint16_t ox_id;
5117 uint16_t rx_id;
5118 uint16_t low_seq_cnt;
5119 uint16_t high_seq_cnt;
5120 } acc;
5121 struct {
5122 uint32_t vendor_unique:8,
5123 reason_explanation:8,
5124 reason_code:8,
5125 :8;
5126 } rjt;
5127 } u;
5128 } sli_bls_payload_t;
5129
5130 /**
5131 * @brief WQE used to create an ELS response.
5132 */
5133 typedef struct sli4_xmit_els_rsp64_wqe_s {
5134 sli4_bde_t els_response_payload;
5135 #if BYTE_ORDER == LITTLE_ENDIAN
5136 uint32_t els_response_payload_length;
5137 uint32_t s_id:24,
5138 sp:1,
5139 :7;
5140 uint32_t remote_id:24,
5141 :8;
5142 uint32_t xri_tag:16,
5143 context_tag:16;
5144 uint32_t :2,
5145 ct:2,
5146 :4,
5147 command:8,
5148 class:3,
5149 :1,
5150 pu:2,
5151 :2,
5152 timer:8;
5153 uint32_t abort_tag;
5154 uint32_t request_tag:16,
5155 ox_id:16;
5156 uint32_t ebde_cnt:4,
5157 :3,
5158 len_loc:2,
5159 qosd:1,
5160 :1,
5161 xbl:1,
5162 hlm:1,
5163 iod:1,
5164 dbde:1,
5165 wqes:1,
5166 pri:3,
5167 pv:1,
5168 eat:1,
5169 xc:1,
5170 :1,
5171 ccpe:1,
5172 ccp:8;
5173 uint32_t cmd_type:4,
5174 :3,
5175 wqec:1,
5176 :8,
5177 cq_id:16;
5178 uint32_t temporary_rpi:16,
5179 :16;
5180 uint32_t rsvd13;
5181 uint32_t rsvd14;
5182 uint32_t rsvd15;
5183 #else
5184 #error big endian version not defined
5185 #endif
5186 } sli4_xmit_els_rsp64_wqe_t;
5187
5188 /**
5189 * @brief Asynchronouse Event: Link State ACQE.
5190 */
5191 typedef struct sli4_link_state_s {
5192 #if BYTE_ORDER == LITTLE_ENDIAN
5193 uint32_t link_number:6,
5194 link_type:2,
5195 port_link_status:8,
5196 port_duplex:8,
5197 port_speed:8;
5198 uint32_t port_fault:8,
5199 :8,
5200 logical_link_speed:16;
5201 uint32_t event_tag;
5202 uint32_t :8,
5203 event_code:8,
5204 event_type:8, /** values are protocol specific */
5205 :6,
5206 ae:1, /** async event - this is an ACQE */
5207 val:1; /** valid - contents of CQE are valid */
5208 #else
5209 #error big endian version not defined
5210 #endif
5211 } sli4_link_state_t;
5212
5213
5214 #define SLI4_LINK_ATTN_TYPE_LINK_UP 0x01
5215 #define SLI4_LINK_ATTN_TYPE_LINK_DOWN 0x02
5216 #define SLI4_LINK_ATTN_TYPE_NO_HARD_ALPA 0x03
5217
5218 #define SLI4_LINK_ATTN_P2P 0x01
5219 #define SLI4_LINK_ATTN_FC_AL 0x02
5220 #define SLI4_LINK_ATTN_INTERNAL_LOOPBACK 0x03
5221 #define SLI4_LINK_ATTN_SERDES_LOOPBACK 0x04
5222
5223 #define SLI4_LINK_ATTN_1G 0x01
5224 #define SLI4_LINK_ATTN_2G 0x02
5225 #define SLI4_LINK_ATTN_4G 0x04
5226 #define SLI4_LINK_ATTN_8G 0x08
5227 #define SLI4_LINK_ATTN_10G 0x0a
5228 #define SLI4_LINK_ATTN_16G 0x10
5229
5230 #define SLI4_LINK_TYPE_ETHERNET 0x0
5231 #define SLI4_LINK_TYPE_FC 0x1
5232
5233 /**
5234 * @brief Asynchronouse Event: FC Link Attention Event.
5235 */
5236 typedef struct sli4_link_attention_s {
5237 #if BYTE_ORDER == LITTLE_ENDIAN
5238 uint32_t link_number:8,
5239 attn_type:8,
5240 topology:8,
5241 port_speed:8;
5242 uint32_t port_fault:8,
5243 shared_link_status:8,
5244 logical_link_speed:16;
5245 uint32_t event_tag;
5246 uint32_t :8,
5247 event_code:8,
5248 event_type:8, /** values are protocol specific */
5249 :6,
5250 ae:1, /** async event - this is an ACQE */
5251 val:1; /** valid - contents of CQE are valid */
5252 #else
5253 #error big endian version not defined
5254 #endif
5255 } sli4_link_attention_t;
5256
5257 /**
5258 * @brief FC/FCoE event types.
5259 */
5260 #define SLI4_LINK_STATE_PHYSICAL 0x00
5261 #define SLI4_LINK_STATE_LOGICAL 0x01
5262
5263 #define SLI4_FCOE_FIP_FCF_DISCOVERED 0x01
5264 #define SLI4_FCOE_FIP_FCF_TABLE_FULL 0x02
5265 #define SLI4_FCOE_FIP_FCF_DEAD 0x03
5266 #define SLI4_FCOE_FIP_FCF_CLEAR_VLINK 0x04
5267 #define SLI4_FCOE_FIP_FCF_MODIFIED 0x05
5268
5269 #define SLI4_GRP5_QOS_SPEED 0x01
5270
5271 #define SLI4_FC_EVENT_LINK_ATTENTION 0x01
5272 #define SLI4_FC_EVENT_SHARED_LINK_ATTENTION 0x02
5273
5274 #define SLI4_PORT_SPEED_NO_LINK 0x0
5275 #define SLI4_PORT_SPEED_10_MBPS 0x1
5276 #define SLI4_PORT_SPEED_100_MBPS 0x2
5277 #define SLI4_PORT_SPEED_1_GBPS 0x3
5278 #define SLI4_PORT_SPEED_10_GBPS 0x4
5279
5280 #define SLI4_PORT_DUPLEX_NONE 0x0
5281 #define SLI4_PORT_DUPLEX_HWF 0x1
5282 #define SLI4_PORT_DUPLEX_FULL 0x2
5283
5284 #define SLI4_PORT_LINK_STATUS_PHYSICAL_DOWN 0x0
5285 #define SLI4_PORT_LINK_STATUS_PHYSICAL_UP 0x1
5286 #define SLI4_PORT_LINK_STATUS_LOGICAL_DOWN 0x2
5287 #define SLI4_PORT_LINK_STATUS_LOGICAL_UP 0x3
5288
5289 /**
5290 * @brief Asynchronouse Event: FCoE/FIP ACQE.
5291 */
5292 typedef struct sli4_fcoe_fip_s {
5293 #if BYTE_ORDER == LITTLE_ENDIAN
5294 uint32_t event_information;
5295 uint32_t fcf_count:16,
5296 fcoe_event_type:16;
5297 uint32_t event_tag;
5298 uint32_t :8,
5299 event_code:8,
5300 event_type:8, /** values are protocol specific */
5301 :6,
5302 ae:1, /** async event - this is an ACQE */
5303 val:1; /** valid - contents of CQE are valid */
5304 #else
5305 #error big endian version not defined
5306 #endif
5307 } sli4_fcoe_fip_t;
5308
5309 /**
5310 * @brief FC/FCoE WQ completion queue entry.
5311 */
5312 typedef struct sli4_fc_wcqe_s {
5313 #if BYTE_ORDER == LITTLE_ENDIAN
5314 uint32_t hw_status:8,
5315 status:8,
5316 request_tag:16;
5317 uint32_t wqe_specific_1;
5318 uint32_t wqe_specific_2;
5319 uint32_t :15,
5320 qx:1,
5321 code:8,
5322 pri:3,
5323 pv:1,
5324 xb:1,
5325 :2,
5326 vld:1;
5327 #else
5328 #error big endian version not defined
5329 #endif
5330 } sli4_fc_wcqe_t;
5331
5332 /**
5333 * @brief FC/FCoE WQ consumed CQ queue entry.
5334 */
5335 typedef struct sli4_fc_wqec_s {
5336 #if BYTE_ORDER == LITTLE_ENDIAN
5337 uint32_t :32;
5338 uint32_t :32;
5339 uint32_t wqe_index:16,
5340 wq_id:16;
5341 uint32_t :16,
5342 code:8,
5343 :7,
5344 vld:1;
5345 #else
5346 #error big endian version not defined
5347 #endif
5348 } sli4_fc_wqec_t;
5349
5350 /**
5351 * @brief FC/FCoE Completion Status Codes.
5352 */
5353 #define SLI4_FC_WCQE_STATUS_SUCCESS 0x00
5354 #define SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE 0x01
5355 #define SLI4_FC_WCQE_STATUS_REMOTE_STOP 0x02
5356 #define SLI4_FC_WCQE_STATUS_LOCAL_REJECT 0x03
5357 #define SLI4_FC_WCQE_STATUS_NPORT_RJT 0x04
5358 #define SLI4_FC_WCQE_STATUS_FABRIC_RJT 0x05
5359 #define SLI4_FC_WCQE_STATUS_NPORT_BSY 0x06
5360 #define SLI4_FC_WCQE_STATUS_FABRIC_BSY 0x07
5361 #define SLI4_FC_WCQE_STATUS_LS_RJT 0x09
5362 #define SLI4_FC_WCQE_STATUS_CMD_REJECT 0x0b
5363 #define SLI4_FC_WCQE_STATUS_FCP_TGT_LENCHECK 0x0c
5364 #define SLI4_FC_WCQE_STATUS_RQ_BUF_LEN_EXCEEDED 0x11
5365 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_BUF_NEEDED 0x12
5366 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_FRM_DISC 0x13
5367 #define SLI4_FC_WCQE_STATUS_RQ_DMA_FAILURE 0x14
5368 #define SLI4_FC_WCQE_STATUS_FCP_RSP_TRUNCATE 0x15
5369 #define SLI4_FC_WCQE_STATUS_DI_ERROR 0x16
5370 #define SLI4_FC_WCQE_STATUS_BA_RJT 0x17
5371 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_NEEDED 0x18
5372 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_DISC 0x19
5373 #define SLI4_FC_WCQE_STATUS_RX_ERROR_DETECT 0x1a
5374 #define SLI4_FC_WCQE_STATUS_RX_ABORT_REQUEST 0x1b
5375
5376 /* driver generated status codes; better not overlap with chip's status codes! */
5377 #define SLI4_FC_WCQE_STATUS_TARGET_WQE_TIMEOUT 0xff
5378 #define SLI4_FC_WCQE_STATUS_SHUTDOWN 0xfe
5379 #define SLI4_FC_WCQE_STATUS_DISPATCH_ERROR 0xfd
5380
5381 /**
5382 * @brief DI_ERROR Extended Status
5383 */
5384 #define SLI4_FC_DI_ERROR_GE (1 << 0) /* Guard Error */
5385 #define SLI4_FC_DI_ERROR_AE (1 << 1) /* Application Tag Error */
5386 #define SLI4_FC_DI_ERROR_RE (1 << 2) /* Reference Tag Error */
5387 #define SLI4_FC_DI_ERROR_TDPV (1 << 3) /* Total Data Placed Valid */
5388 #define SLI4_FC_DI_ERROR_UDB (1 << 4) /* Uninitialized DIF Block */
5389 #define SLI4_FC_DI_ERROR_EDIR (1 << 5) /* Error direction */
5390
5391 /**
5392 * @brief Local Reject Reason Codes.
5393 */
5394 #define SLI4_FC_LOCAL_REJECT_MISSING_CONTINUE 0x01
5395 #define SLI4_FC_LOCAL_REJECT_SEQUENCE_TIMEOUT 0x02
5396 #define SLI4_FC_LOCAL_REJECT_INTERNAL_ERROR 0x03
5397 #define SLI4_FC_LOCAL_REJECT_INVALID_RPI 0x04
5398 #define SLI4_FC_LOCAL_REJECT_NO_XRI 0x05
5399 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_COMMAND 0x06
5400 #define SLI4_FC_LOCAL_REJECT_XCHG_DROPPED 0x07
5401 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_FIELD 0x08
5402 #define SLI4_FC_LOCAL_REJECT_NO_ABORT_MATCH 0x0c
5403 #define SLI4_FC_LOCAL_REJECT_TX_DMA_FAILED 0x0d
5404 #define SLI4_FC_LOCAL_REJECT_RX_DMA_FAILED 0x0e
5405 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_FRAME 0x0f
5406 #define SLI4_FC_LOCAL_REJECT_NO_RESOURCES 0x11
5407 #define SLI4_FC_LOCAL_REJECT_FCP_CONF_FAILURE 0x12
5408 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_LENGTH 0x13
5409 #define SLI4_FC_LOCAL_REJECT_UNSUPPORTED_FEATURE 0x14
5410 #define SLI4_FC_LOCAL_REJECT_ABORT_IN_PROGRESS 0x15
5411 #define SLI4_FC_LOCAL_REJECT_ABORT_REQUESTED 0x16
5412 #define SLI4_FC_LOCAL_REJECT_RCV_BUFFER_TIMEOUT 0x17
5413 #define SLI4_FC_LOCAL_REJECT_LOOP_OPEN_FAILURE 0x18
5414 #define SLI4_FC_LOCAL_REJECT_LINK_DOWN 0x1a
5415 #define SLI4_FC_LOCAL_REJECT_CORRUPTED_DATA 0x1b
5416 #define SLI4_FC_LOCAL_REJECT_CORRUPTED_RPI 0x1c
5417 #define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_DATA 0x1d
5418 #define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_ACK 0x1e
5419 #define SLI4_FC_LOCAL_REJECT_DUP_FRAME 0x1f
5420 #define SLI4_FC_LOCAL_REJECT_LINK_CONTROL_FRAME 0x20
5421 #define SLI4_FC_LOCAL_REJECT_BAD_HOST_ADDRESS 0x21
5422 #define SLI4_FC_LOCAL_REJECT_MISSING_HDR_BUFFER 0x23
5423 #define SLI4_FC_LOCAL_REJECT_MSEQ_CHAIN_CORRUPTED 0x24
5424 #define SLI4_FC_LOCAL_REJECT_ABORTMULT_REQUESTED 0x25
5425 #define SLI4_FC_LOCAL_REJECT_BUFFER_SHORTAGE 0x28
5426 #define SLI4_FC_LOCAL_REJECT_RCV_XRIBUF_WAITING 0x29
5427 #define SLI4_FC_LOCAL_REJECT_INVALID_VPI 0x2e
5428 #define SLI4_FC_LOCAL_REJECT_MISSING_XRIBUF 0x30
5429 #define SLI4_FC_LOCAL_REJECT_INVALID_RELOFFSET 0x40
5430 #define SLI4_FC_LOCAL_REJECT_MISSING_RELOFFSET 0x41
5431 #define SLI4_FC_LOCAL_REJECT_INSUFF_BUFFERSPACE 0x42
5432 #define SLI4_FC_LOCAL_REJECT_MISSING_SI 0x43
5433 #define SLI4_FC_LOCAL_REJECT_MISSING_ES 0x44
5434 #define SLI4_FC_LOCAL_REJECT_INCOMPLETE_XFER 0x45
5435 #define SLI4_FC_LOCAL_REJECT_SLER_FAILURE 0x46
5436 #define SLI4_FC_LOCAL_REJECT_SLER_CMD_RCV_FAILURE 0x47
5437 #define SLI4_FC_LOCAL_REJECT_SLER_REC_RJT_ERR 0x48
5438 #define SLI4_FC_LOCAL_REJECT_SLER_REC_SRR_RETRY_ERR 0x49
5439 #define SLI4_FC_LOCAL_REJECT_SLER_SRR_RJT_ERR 0x4a
5440 #define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RJT_ERR 0x4c
5441 #define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RETRY_ERR 0x4d
5442 #define SLI4_FC_LOCAL_REJECT_SLER_ABTS_ERR 0x4e
5443
5444 typedef struct sli4_fc_async_rcqe_s {
5445 #if BYTE_ORDER == LITTLE_ENDIAN
5446 uint32_t :8,
5447 status:8,
5448 rq_element_index:12,
5449 :4;
5450 uint32_t rsvd1;
5451 uint32_t fcfi:6,
5452 rq_id:10,
5453 payload_data_placement_length:16;
5454 uint32_t sof_byte:8,
5455 eof_byte:8,
5456 code:8,
5457 header_data_placement_length:6,
5458 :1,
5459 vld:1;
5460 #else
5461 #error big endian version not defined
5462 #endif
5463 } sli4_fc_async_rcqe_t;
5464
5465 typedef struct sli4_fc_async_rcqe_v1_s {
5466 #if BYTE_ORDER == LITTLE_ENDIAN
5467 uint32_t :8,
5468 status:8,
5469 rq_element_index:12,
5470 :4;
5471 uint32_t fcfi:6,
5472 :26;
5473 uint32_t rq_id:16,
5474 payload_data_placement_length:16;
5475 uint32_t sof_byte:8,
5476 eof_byte:8,
5477 code:8,
5478 header_data_placement_length:6,
5479 :1,
5480 vld:1;
5481 #else
5482 #error big endian version not defined
5483 #endif
5484 } sli4_fc_async_rcqe_v1_t;
5485
5486 #define SLI4_FC_ASYNC_RQ_SUCCESS 0x10
5487 #define SLI4_FC_ASYNC_RQ_BUF_LEN_EXCEEDED 0x11
5488 #define SLI4_FC_ASYNC_RQ_INSUFF_BUF_NEEDED 0x12
5489 #define SLI4_FC_ASYNC_RQ_INSUFF_BUF_FRM_DISC 0x13
5490 #define SLI4_FC_ASYNC_RQ_DMA_FAILURE 0x14
5491
5492 typedef struct sli4_fc_coalescing_rcqe_s {
5493 #if BYTE_ORDER == LITTLE_ENDIAN
5494 uint32_t :8,
5495 status:8,
5496 rq_element_index:12,
5497 :4;
5498 uint32_t rsvd1;
5499 uint32_t rq_id:16,
5500 sequence_reporting_placement_length:16;
5501 uint32_t :16,
5502 code:8,
5503 :7,
5504 vld:1;
5505 #else
5506 #error big endian version not defined
5507 #endif
5508 } sli4_fc_coalescing_rcqe_t;
5509
5510 #define SLI4_FC_COALESCE_RQ_SUCCESS 0x10
5511 #define SLI4_FC_COALESCE_RQ_INSUFF_XRI_NEEDED 0x18
5512
5513 typedef struct sli4_fc_optimized_write_cmd_cqe_s {
5514 #if BYTE_ORDER == LITTLE_ENDIAN
5515 uint32_t :8,
5516 status:8,
5517 rq_element_index:15,
5518 iv:1;
5519 uint32_t fcfi:6,
5520 :8,
5521 oox:1,
5522 agxr:1,
5523 xri:16;
5524 uint32_t rq_id:16,
5525 payload_data_placement_length:16;
5526 uint32_t rpi:16,
5527 code:8,
5528 header_data_placement_length:6,
5529 :1,
5530 vld:1;
5531 #else
5532 #error big endian version not defined
5533 #endif
5534 } sli4_fc_optimized_write_cmd_cqe_t;
5535
5536 typedef struct sli4_fc_optimized_write_data_cqe_s {
5537 #if BYTE_ORDER == LITTLE_ENDIAN
5538 uint32_t hw_status:8,
5539 status:8,
5540 xri:16;
5541 uint32_t total_data_placed;
5542 uint32_t extended_status;
5543 uint32_t :16,
5544 code:8,
5545 pri:3,
5546 pv:1,
5547 xb:1,
5548 rha:1,
5549 :1,
5550 vld:1;
5551 #else
5552 #error big endian version not defined
5553 #endif
5554 } sli4_fc_optimized_write_data_cqe_t;
5555
5556 typedef struct sli4_fc_xri_aborted_cqe_s {
5557 #if BYTE_ORDER == LITTLE_ENDIAN
5558 uint32_t :8,
5559 status:8,
5560 :16;
5561 uint32_t extended_status;
5562 uint32_t xri:16,
5563 remote_xid:16;
5564 uint32_t :16,
5565 code:8,
5566 xr:1,
5567 :3,
5568 eo:1,
5569 br:1,
5570 ia:1,
5571 vld:1;
5572 #else
5573 #error big endian version not defined
5574 #endif
5575 } sli4_fc_xri_aborted_cqe_t;
5576
5577 /**
5578 * Code definitions applicable to all FC/FCoE CQE types.
5579 */
5580 #define SLI4_CQE_CODE_OFFSET 14
5581
5582 #define SLI4_CQE_CODE_WORK_REQUEST_COMPLETION 0x01
5583 #define SLI4_CQE_CODE_RELEASE_WQE 0x02
5584 #define SLI4_CQE_CODE_RQ_ASYNC 0x04
5585 #define SLI4_CQE_CODE_XRI_ABORTED 0x05
5586 #define SLI4_CQE_CODE_RQ_COALESCING 0x06
5587 #define SLI4_CQE_CODE_RQ_CONSUMPTION 0x07
5588 #define SLI4_CQE_CODE_MEASUREMENT_REPORTING 0x08
5589 #define SLI4_CQE_CODE_RQ_ASYNC_V1 0x09
5590 #define SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD 0x0B
5591 #define SLI4_CQE_CODE_OPTIMIZED_WRITE_DATA 0x0C
5592
5593 extern int32_t sli_fc_process_link_state(sli4_t *, void *);
5594 extern int32_t sli_fc_process_link_attention(sli4_t *, void *);
5595 extern int32_t sli_fc_cqe_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *);
5596 extern uint32_t sli_fc_response_length(sli4_t *, uint8_t *);
5597 extern uint32_t sli_fc_io_length(sli4_t *, uint8_t *);
5598 extern int32_t sli_fc_els_did(sli4_t *, uint8_t *, uint32_t *);
5599 extern uint32_t sli_fc_ext_status(sli4_t *, uint8_t *);
5600 extern int32_t sli_fc_rqe_rqid_and_index(sli4_t *, uint8_t *, uint16_t *, uint32_t *);
5601 extern int32_t sli_fc_process_fcoe(sli4_t *, void *);
5602 extern int32_t sli_cmd_fcoe_wq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t);
5603 extern int32_t sli_cmd_fcoe_wq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t);
5604 extern int32_t sli_cmd_fcoe_wq_destroy(sli4_t *, void *, size_t, uint16_t);
5605 extern int32_t sli_cmd_fcoe_post_sgl_pages(sli4_t *, void *, size_t, uint16_t, uint32_t, ocs_dma_t **, ocs_dma_t **,
5606 ocs_dma_t *);
5607 extern int32_t sli_cmd_fcoe_rq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t);
5608 extern int32_t sli_cmd_fcoe_rq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t);
5609 extern int32_t sli_cmd_fcoe_rq_destroy(sli4_t *, void *, size_t, uint16_t);
5610 extern int32_t sli_cmd_fcoe_read_fcf_table(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t);
5611 extern int32_t sli_cmd_fcoe_post_hdr_templates(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, ocs_dma_t *);
5612 extern int32_t sli_cmd_fcoe_rediscover_fcf(sli4_t *, void *, size_t, uint16_t);
5613 extern int32_t sli_fc_rq_alloc(sli4_t *, sli4_queue_t *, uint32_t, uint32_t, sli4_queue_t *, uint16_t, uint8_t);
5614 extern int32_t sli_fc_rq_set_alloc(sli4_t *, uint32_t, sli4_queue_t *[], uint32_t, uint32_t, uint32_t, uint32_t, uint16_t);
5615 extern uint32_t sli_fc_get_rpi_requirements(sli4_t *, uint32_t);
5616 extern int32_t sli_abort_wqe(sli4_t *, void *, size_t, sli4_abort_type_e, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t);
5617
5618 extern int32_t sli_els_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint8_t, uint32_t, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *);
5619 extern int32_t sli_fcp_iread64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5620 extern int32_t sli_fcp_iwrite64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5621 extern int32_t sli_fcp_icmnd64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t);
5622
5623 extern int32_t sli_fcp_treceive64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t);
5624 extern int32_t sli_fcp_trsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint32_t);
5625 extern int32_t sli_fcp_tsend64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t);
5626 extern int32_t sli_fcp_cont_treceive64_wqe(sli4_t *, void*, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t);
5627 extern int32_t sli_gen_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t,uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5628 extern int32_t sli_send_frame_wqe(sli4_t *sli4, void *buf, size_t size, uint8_t sof, uint8_t eof, uint32_t *hdr,
5629 ocs_dma_t *payload, uint32_t req_len, uint8_t timeout,
5630 uint16_t xri, uint16_t req_tag);
5631 extern int32_t sli_xmit_sequence64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5632 extern int32_t sli_xmit_bcast64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t);
5633 extern int32_t sli_xmit_bls_rsp64_wqe(sli4_t *, void *, size_t, sli_bls_payload_t *, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t);
5634 extern int32_t sli_xmit_els_rsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t, uint32_t);
5635 extern int32_t sli_requeue_xri_wqe(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t);
5636 extern void sli4_cmd_lowlevel_set_watchdog(sli4_t *sli4, void *buf, size_t size, uint16_t timeout);
5637 extern bool sli_persist_topology_enabled(sli4_t *sli4);
5638
5639
5640 /**
5641 * @ingroup sli_fc
5642 * @brief Retrieve the received header and payload length.
5643 *
5644 * @param sli4 SLI context.
5645 * @param cqe Pointer to the CQ entry.
5646 * @param len_hdr Pointer where the header length is written.
5647 * @param len_data Pointer where the payload length is written.
5648 *
5649 * @return Returns 0 on success, or a non-zero value on failure.
5650 */
5651 static inline int32_t
sli_fc_rqe_length(sli4_t * sli4,void * cqe,uint32_t * len_hdr,uint32_t * len_data)5652 sli_fc_rqe_length(sli4_t *sli4, void *cqe, uint32_t *len_hdr, uint32_t *len_data)
5653 {
5654 sli4_fc_async_rcqe_t *rcqe = cqe;
5655
5656 *len_hdr = *len_data = 0;
5657
5658 if (SLI4_FC_ASYNC_RQ_SUCCESS == rcqe->status) {
5659 *len_hdr = rcqe->header_data_placement_length;
5660 *len_data = rcqe->payload_data_placement_length;
5661 return 0;
5662 } else {
5663 return -1;
5664 }
5665 }
5666
5667 /**
5668 * @ingroup sli_fc
5669 * @brief Retrieve the received FCFI.
5670 *
5671 * @param sli4 SLI context.
5672 * @param cqe Pointer to the CQ entry.
5673 *
5674 * @return Returns the FCFI in the CQE. or UINT8_MAX if invalid CQE code.
5675 */
5676 static inline uint8_t
sli_fc_rqe_fcfi(sli4_t * sli4,void * cqe)5677 sli_fc_rqe_fcfi(sli4_t *sli4, void *cqe)
5678 {
5679 uint8_t code = ((uint8_t*)cqe)[SLI4_CQE_CODE_OFFSET];
5680 uint8_t fcfi = UINT8_MAX;
5681
5682 switch(code) {
5683 case SLI4_CQE_CODE_RQ_ASYNC: {
5684 sli4_fc_async_rcqe_t *rcqe = cqe;
5685 fcfi = rcqe->fcfi;
5686 break;
5687 }
5688 case SLI4_CQE_CODE_RQ_ASYNC_V1: {
5689 sli4_fc_async_rcqe_v1_t *rcqev1 = cqe;
5690 fcfi = rcqev1->fcfi;
5691 break;
5692 }
5693 case SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD: {
5694 sli4_fc_optimized_write_cmd_cqe_t *opt_wr = cqe;
5695 fcfi = opt_wr->fcfi;
5696 break;
5697 }
5698 }
5699
5700 return fcfi;
5701 }
5702
5703 extern const char *sli_fc_get_status_string(uint32_t status);
5704
5705 #endif /* !_SLI4_H */
5706
5707