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Searched refs:regVal (Results 1 – 5 of 5) sorted by relevance

/freebsd-12-stable/sys/dev/ath/ath_hal/ar9002/
Dar9285_diversity.c66 int regVal; in ar9285SetAntennaSwitch() local
88 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9285SetAntennaSwitch()
89 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); in ar9285SetAntennaSwitch()
93 regVal |= SM(ant_div_control1, AR_PHY_9285_ANT_DIV_CTL); in ar9285SetAntennaSwitch()
98 regVal |= SM(ant_div_control2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9285SetAntennaSwitch()
99 regVal |= SM((ant_div_control2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); in ar9285SetAntennaSwitch()
100 regVal |= SM((ant_div_control1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); in ar9285SetAntennaSwitch()
101 regVal |= SM((ant_div_control1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB); in ar9285SetAntennaSwitch()
107 regVal |= SM(HAL_ANT_DIV_COMB_LNA2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9285SetAntennaSwitch()
108 regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_MAIN_LNACONF); in ar9285SetAntennaSwitch()
[all …]
Dar9285_btcoex.c49 u_int32_t regVal; in ar9285BTCoexAntennaDiversity() local
107 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9285BTCoexAntennaDiversity()
108 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); in ar9285BTCoexAntennaDiversity()
113 regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS)); in ar9285BTCoexAntennaDiversity()
115 regVal |= SM(ant_div_control1, AR_PHY_9285_ANT_DIV_CTL); in ar9285BTCoexAntennaDiversity()
116 regVal |= SM(ant_div_control2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9285BTCoexAntennaDiversity()
117 regVal |= SM((ant_div_control2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); in ar9285BTCoexAntennaDiversity()
118 regVal |= SM((ant_div_control1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); in ar9285BTCoexAntennaDiversity()
119 regVal |= SM((ant_div_control1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB); in ar9285BTCoexAntennaDiversity()
120 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); in ar9285BTCoexAntennaDiversity()
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Dar9285_cal.c53 uint32_t regVal; in ar9285_hw_pa_cal() local
76 regVal = OS_REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
77 regVal &= (~(0x1)); in ar9285_hw_pa_cal()
78 OS_REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
79 regVal = OS_REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
80 regVal |= (0x1 << 27); in ar9285_hw_pa_cal()
81 OS_REG_WRITE(ah, 0x9808, regVal); in ar9285_hw_pa_cal()
104 regVal = OS_REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
105 regVal |= (1 << (19 + i)); in ar9285_hw_pa_cal()
106 OS_REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
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/freebsd-12-stable/sys/dev/pms/RefTisa/sallsdk/spc/
Dsahw.c574 bit32 regVal; in siChipResetV() local
579 regVal = ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister ); in siChipResetV()
581 SA_DBG1(("siChipResetV: signature %X V_SoftResetRegister %X\n",signature,regVal)); in siChipResetV()
585 SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE 0x%X\n",regVal)); in siChipResetV()
586 regVal = SPCv_Reset_Write_NormalReset; in siChipResetV()
590 SA_DBG1(("siChipResetV: SPCv load HDA 0x%X\n",regVal)); in siChipResetV()
591 regVal = SPCv_Reset_Write_SoftResetHDA; in siChipResetV()
595 SA_DBG1(("siChipResetV: Invalid SIGNATURE 0x%X regVal 0x%X a\n",signature ,regVal)); in siChipResetV()
596 regVal = 1; in siChipResetV()
600 ossaHwRegWriteExt(agRoot, PCIBAR0, V_SoftResetRegister, regVal); /* siChipResetV */ in siChipResetV()
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/freebsd-12-stable/contrib/sqlite3/
Dsqlite3.c169303 int regVal, /* Register containing non-negative number */
169334 reg1, (arith==OP_Add ? "+" : "-"), regVal,
169402 sqlite3VdbeAddOp3(v, arith, regVal, reg1, reg1);