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Searched refs:regB (Results 1 – 2 of 2) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DTwoAddressInstructionPass.cpp1139 Register regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform() local
1141 assert(regB.isVirtual() && "cannot make instruction into two-address form"); in tryInstructionTransform()
1142 bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true); in tryInstructionTransform()
1165 if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) { in tryInstructionTransform()
1173 regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1174 regBKilled = isKilled(MI, regB, MRI, TII, LIS, true); in tryInstructionTransform()
1180 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) { in tryInstructionTransform()
1182 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) { in tryInstructionTransform()
1195 if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) { in tryInstructionTransform()
1247 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); in tryInstructionTransform()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h416 bool regsOverlap(Register regA, Register regB) const { in regsOverlap() argument
417 if (regA == regB) return true; in regsOverlap()
418 if (!regA.isPhysical() || !regB.isPhysical()) in regsOverlap()
423 MCRegUnitIterator RUB(regB.asMCReg(), this); in regsOverlap()