| /freebsd-12-stable/usr.bin/man/ |
| D | man.sh | 307 local IFS pipeline testline
344 pipeline="mandoc -Tps $mandoc_args"
346 pipeline="mandoc $mandoc_args | $MANPAGER"
362 decho "Command: $cattool $manpage | $pipeline"
365 eval "$cattool $manpage | $pipeline"
374 local IFS l nroff_dev pipeline preproc_arg tool
433 e) pipeline="$pipeline | $EQN" ;;
435 p) pipeline="$pipeline | $PIC" ;;
436 r) pipeline="$pipeline | $REFER" ;;
437 t) pipeline="$pipeline | $TBL" ;;
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| /freebsd-12-stable/sbin/hastd/ |
| D | hast_proto.c | 69 static struct hast_pipe_stage pipeline[] = { variable
97 for (ii = 0; ii < sizeof(pipeline) / sizeof(pipeline[0]); in hast_proto_send()
99 (void)pipeline[ii].hps_send(res, nv, &dptr, &size, in hast_proto_send()
199 for (ii = sizeof(pipeline) / sizeof(pipeline[0]); ii > 0; in hast_proto_recv_data()
201 ret = pipeline[ii - 1].hps_recv(res, nv, &dptr, in hast_proto_recv_data()
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| /freebsd-12-stable/tools/tools/netrate/juggle/ |
| D | juggle.c | 235 juggle(int fd1, int fd2, int pipeline) in juggle() argument
245 for (j = 0; j < pipeline; j++) { in juggle()
250 for (j = 0; j < pipeline; j++) { in juggle()
258 for (j = 0; j < pipeline; j++) { in juggle()
317 thread_juggle(int fd1, int fd2, int pipeline) in thread_juggle() argument
323 threaded_pipeline = pipeline; in thread_juggle()
346 for (j = 0; j < pipeline; j++) { in thread_juggle()
351 for (j = 0; j < pipeline; j++) { in thread_juggle()
376 process_juggle(int fd1, int fd2, int pipeline) in process_juggle() argument
397 for (j = 0; j < pipeline; j++) { in process_juggle()
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCSchedule440.td | 13 // The basic PPC 440 does not include a floating-point unit; the pipeline
34 // the complex integer (I-pipe) pipeline
36 // the floating-point execution (F-pipe) pipeline
37 def P440_IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline
38 def P440_IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline
39 def P440_IWB : FuncUnit; // Write-back unit for the I pipeline
40 def P440_JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline
41 def P440_JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline
42 def P440_JWB : FuncUnit; // Write-back unit for the J pipeline
43 def P440_AGEN : FuncUnit; // Address generation for the L pipeline
[all …]
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| D | PPCScheduleP7.td | 30 def P7_LS1 : FuncUnit; // Load/Store pipeline 1
31 def P7_LS2 : FuncUnit; // Load/Store pipeline 2
33 def P7_FX1 : FuncUnit; // FX pipeline 1
34 def P7_FX2 : FuncUnit; // FX pipeline 2
36 // VS pipeline 1 (vector integer ops. always here)
37 def P7_VS1 : FuncUnit; // VS pipeline 1
38 // VS pipeline 2 (128-bit stores and perms. here)
39 def P7_VS2 : FuncUnit; // VS pipeline 2
45 // Each LSU pipeline can also execute FX add and logical instructions.
46 // Each LSU pipeline can complete a load or store in one cycle.
[all …]
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| D | PPCScheduleP8.td | 34 def P8_LSU1 : FuncUnit; // Load/Store pipeline 1
35 def P8_LSU2 : FuncUnit; // Load/Store pipeline 2
38 def P8_FXU1 : FuncUnit; // FX pipeline 1
39 def P8_FXU2 : FuncUnit; // FX pipeline 2
47 def P8_FPU1 : FuncUnit; // VS pipeline 1
48 def P8_FPU2 : FuncUnit; // VS pipeline 2
|
| D | PPCScheduleA2.td | 16 def A2_XU : FuncUnit; // A2_XU pipeline
17 def A2_FU : FuncUnit; // FI pipeline
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| D | PPCScheduleE5500.td | 34 def E5500_CFX_0 : FuncUnit; // CFX pipeline stage 0
36 def E5500_CFX_1 : FuncUnit; // CFX pipeline stage 1
38 def E5500_LSU_0 : FuncUnit; // LSU pipeline
39 def E5500_FPU_0 : FuncUnit; // FPU pipeline
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| /freebsd-12-stable/contrib/gcc/config/arm/ |
| D | arm1026ejs.md | 27 ;; This automaton provides a pipeline description for the ARM
42 ;; - An Arithmetic Logic Unit (ALU) pipeline.
44 ;; The ALU pipeline has fetch, issue, decode, execute, memory, and
48 ;; - A Load-Store Unit (LSU) pipeline.
50 ;; The LSU pipeline has decode, execute, memory, and write stages.
61 ;; pipeline in each of the three stages. The results are available
160 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
181 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
191 ;; The ALU pipeline is stalled until the completion of the last memory
192 ;; stage in the LSU pipeline. That is modeled by keeping the ALU
|
| D | arm1020e.md | 27 ;; This automaton provides a pipeline description for the ARM
42 ;; - An Arithmetic Logic Unit (ALU) pipeline.
44 ;; The ALU pipeline has fetch, issue, decode, execute, memory, and
48 ;; - A Load-Store Unit (LSU) pipeline.
50 ;; The LSU pipeline has decode, execute, memory, and write stages.
61 ;; pipeline in each of the three stages. The results are available
160 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
181 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
191 ;; The ALU pipeline is decoupled after the first cycle unless there is
327 ;; Moves to/from arm regs also use the load/store pipeline.
|
| D | arm1136jfs.md | 27 ;; This automaton provides a pipeline description for the ARM
42 ;; - A 4-stage decode pipeline, shared by all three. It has fetch (1),
46 ;; - A 4-stage ALU pipeline. It has shifter, ALU (main integer operations),
49 ;; - A 4-stage multiply-accumulate pipeline. It has three stages, called
53 ;; which operate in lockstep. Results from either pipeline will be
55 ;; in lockstep, we schedule them as a single "execute" pipeline.
57 ;; - A 4-stage LSU pipeline. It has address generation, data cache (1),
58 ;; data cache (2), and writeback stages. (Note that this pipeline,
70 ;; pipeline in each of the eight stages. The results are available
190 ;; pass through the pipeline and make the result available after three
|
| D | arm926ejs.md | 27 ;; This automaton provides a pipeline description for the ARM
40 ;; There is a single pipeline
42 ;; The ALU pipeline has fetch, decode, execute, memory, and
53 ;; pipeline in each of the three stages. The results are available
81 ;; stages of the pipeline
|
| D | vfp.md | 35 ;; - A 8-stage FMAC pipeline (7 execute + writeback) with forward from
38 ;; - A 5-stage DS pipeline (4 execute + writeback) for divide/sqrt insns.
39 ;; These insns also uses first execute stage of FMAC pipeline.
41 ;; - A 4-stage LS pipeline (execute + 2 memory + writeback) with forward from
46 ;; to model the first stage of each pipeline
47 ;; ??? Need to model LS pipeline properly for load/store multiple?
100 ;; Moves to/from arm regs also use the load/store pipeline.
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleV6.td | 16 def V6_Pipe : FuncUnit; // pipeline
87 // Integer multiply pipeline
96 // Integer load pipeline
149 // Integer store pipeline
190 // Issue through integer pipeline, and execute in NEON unit. We assume
191 // RunFast mode so that NFP pipeline is used for single-precision when
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| D | ARMScheduleA8.td | 16 def A8_Pipe0 : FuncUnit; // pipeline 0
17 def A8_Pipe1 : FuncUnit; // pipeline 1
18 def A8_LSPipe : FuncUnit; // Load / store pipeline
22 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
94 // Integer multiply pipeline
105 // Integer load pipeline
184 // Integer store pipeline
248 // Issue through integer pipeline, and execute in NEON unit. We assume
249 // RunFast mode so that NFP pipeline is used for single-precision when
437 // Issue through integer pipeline, and execute in NEON unit.
[all …]
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| D | ARMScheduleM7.td | 116 // The FP pipeline has a latency of 3 cycles.
117 // ALU operations (32/64-bit). These go down the FP pipeline.
173 // What pipeline stage operands need to be ready for depending on
188 // Assume that these will go down the main ALU pipeline.
189 // In reality, many look likely to stall the whole pipeline.
469 // Double-precision chained MAC stalls the pipeline behind it for 3 cycles,
488 // Double-precision fused MAC stalls the pipeline behind it for 2 cycles, making
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| /freebsd-12-stable/contrib/gcclibs/libiberty/ |
| D | pexecute.txh | 6 independent interface to execute a pipeline.
35 Execute one program in a pipeline. On success this returns
47 This must be set on the last program in the pipeline. In particular,
135 Execute one program in a pipeline, permitting the environment for the
149 the pipeline as input.
166 the first program in the pipeline; @var{fp} is opened for writing.
171 finished writing data to the pipeline.
192 before starting the first process in the pipeline, consider using
198 program in the pipeline is waiting for the next to read more data, and
210 output of the last program in the pipeline. When this is used,
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| /freebsd-12-stable/contrib/gcc/config/s390/ |
| D | 2064.md | 29 ;; z900 (cpu 2064) pipeline
119 ;; to the address generation pipeline stage.
127 ;; result back to the address generation pipeline stage.
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| /freebsd-12-stable/bin/sh/ |
| D | nodetypes | 62 NPIPE npipe # a pipeline
64 backgnd int # set to run pipeline in background
65 cmdlist nodelist # the commands in the pipeline
143 NNOT nnot # ! command (actually pipeline)
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| /freebsd-12-stable/contrib/gcc/config/mips/ |
| D | 4k.md | 1 ;; DFA-based pipeline descriptions for MIPS32 4K processor family
80 ;; stall the integer unit pipeline. MUL 16x16 or 32x16 forces 1 cycle stall,
99 ;; Latency of 32 cycles, but stalls the whole pipeline until complete.
|
| D | sr71k.md | 3 ;; DFA-based pipeline description for Sandcraft SR3 (MIPS64 based)
6 ;; - nine-stage pipeline, insn buffering with out-of-order issue to
49 ;; pipeline.
52 ;; pipeline.
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| /freebsd-12-stable/crypto/openssl/doc/man3/ |
| D | SSL_CTX_set_split_send_fragment.pod | 55 "read" pipelining and "write" pipelining. By default only one pipeline will be
59 explained further below. OpenSSL will only every use more than one pipeline if
60 a cipher suite is negotiated that uses a pipeline capable cipher provided by an
73 SSL_write/SSL_write_ex called with 0-2000 bytes == 1 pipeline used
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| /freebsd-12-stable/contrib/gcc/config/i386/ |
| D | k6.md | 117 ;; ??? Guessed latencies based on the old pipeline description.
194 ;; The load and units have two pipeline stages. The load latency is
207 ;; ??? From the old pipeline description. Egad!
263 ;; ??? Guessed latencies from the old pipeline description.
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| D | geode.md | 35 ;; issue describes the issue pipeline.
40 ;; There is also memory management unit and execution pipeline for
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| /freebsd-12-stable/release/picobsd/tinyware/msh/ |
| D | sh2.c | 51 _PROTOTYPE(static struct op *pipeline, (int cf ));
95 pipeline(cf) in pipeline() function
123 t = pipeline(0); in andor()
126 if ((p = pipeline(CONTIN)) == NULL) in andor()
|