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Searched refs:opc2 (Results 1 – 9 of 9) sorted by relevance

/freebsd-12-stable/contrib/binutils/opcodes/
Dia64-gen.c2634 opcodes_eq (opc1, opc2) in opcodes_eq() argument
2636 struct ia64_opcode *opc2;
2641 if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type)
2642 || (opc1->num_outputs != opc2->num_outputs)
2643 || (opc1->flags != opc2->flags))
2647 if (opc1->operands[x] != opc2->operands[x])
2651 plen2 = get_prefix_len (opc2->name);
2653 if (plen1 == plen2 && (memcmp (opc1->name, opc2->name, plen1) == 0))
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/XCore/
DXCoreInstrInfo.td213 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
217 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
222 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
225 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
229 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
234 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
250 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
255 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
261 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
266 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMInstrInfo.td5345 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5346 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5348 timm:$CRm, timm:$opc2)]>,
5354 bits<3> opc2;
5359 let Inst{7-5} = opc2;
5369 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5370 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5372 timm:$CRm, timm:$opc2)]>,
5379 bits<3> opc2;
5384 let Inst{7-5} = opc2;
[all …]
DARMInstrThumb2.td4502 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4511 bits<3> opc2;
4518 let Inst{7-5} = opc2;
4551 c_imm:$CRm, imm0_7:$opc2),
4553 timm:$CRm, timm:$opc2)]>,
4560 c_imm:$CRm, imm0_7:$opc2),
4562 timm:$CRm, timm:$opc2)]> {
4572 c_imm:$CRm, imm0_7:$opc2), []>;
4579 c_imm:$CRm, imm0_7:$opc2), []> {
4586 def : T2v6Pat<(int_arm_mrc timm:$cop, timm:$opc1, timm:$CRn, timm:$CRm, timm:$opc2),
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86InstrMMX.td51 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
65 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
DX86InstrSSE.td3513 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3536 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3545 multiclass PDI_binop_rmi_all<bits<8> opc, bits<8> opc2, Format ImmForm,
3552 defm V#NAME : PDI_binop_rmi<opc, opc2, ImmForm, !strconcat("v", OpcodeStr),
3556 defm V#NAME#Y : PDI_binop_rmi<opc, opc2, ImmForm, !strconcat("v", OpcodeStr),
3561 defm NAME : PDI_binop_rmi<opc, opc2, ImmForm, OpcodeStr, OpNode, OpNode2,
DX86InstrAVX512.td3077 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
3085 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode,
3087 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td4392 class BaseMemTag<bits<2> opc1, bits<2> opc2, string asm_insn,
4402 let Inst{11-10} = opc2;
4432 class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn,
4434 : BaseMemTag<opc1, opc2, asm_insn, asm_opnds, cstr, oops, iops> {
10787 bit opc1, bit opc2, RegisterOperand dst_reg,
10815 let Inst{12} = opc2;
10825 multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype,
10828 def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64,
10836 def v8f16_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b01, opc1, opc2,
10846 def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2,
DSVEInstrFormats.td2352 class sve_int_read_vl_a<bit op, bits<5> opc2, string asm>
2362 let Inst{20-16} = opc2{4-0};