Searched refs:max_lanes (Results 1 – 7 of 7) sorted by relevance
285 uint8_t max_lanes; member332 uint8_t max_lanes; member
178 uint8_t max_lanes = pcie_port->max_lanes; in al_pcie_port_link_config() local215 max_lanes << PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_SHIFT); in al_pcie_port_link_config()218 (max_lanes + (max_lanes-1)) in al_pcie_port_link_config()989 pcie_port->max_lanes = 0; in al_pcie_port_handle_init()1399 pcie_port->max_lanes = lanes; in al_pcie_port_max_lanes_set()1701 if (pcie_port->max_lanes == 0) { in al_pcie_port_config()1711 pcie_port->max_lanes = 1; in al_pcie_port_config()1714 pcie_port->max_lanes = 2; in al_pcie_port_config()1717 pcie_port->max_lanes = 4; in al_pcie_port_config()1720 pcie_port->max_lanes = 8; in al_pcie_port_config()[all …]
232 nvmex->max_lanes = (caps & PCIEM_LINK_CAP_MAX_WIDTH) >> 4; in nvme_sim_action()
184 intel_dp_max_data_rate(int max_link_clock, int max_lanes) in intel_dp_max_data_rate() argument186 return (max_link_clock * max_lanes * 8) / 10; in intel_dp_max_data_rate()195 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); in intel_dp_adjust_dithering() local199 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); in intel_dp_adjust_dithering()
819 nvmex->lanes, nvmex->max_lanes, in nvme_announce_periph()
1039 uint8_t max_lanes; /* Number of PCIe lanes */ member
5357 nvmex->lanes, nvmex->max_lanes); in cts_print()