Searched refs:isZeroExtended (Results 1 – 6 of 6) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64PostLegalizerCombiner.cpp | 117 static bool isZeroExtended(Register R, MachineRegisterInfo &MRI) { in isZeroExtended() function
155 (isSignExtended(LHS, MRI) || isZeroExtended(LHS, MRI))) in matchAArch64MulConstCombine()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 606 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
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| D | PPCMIPeephole.cpp | 214 if (TII->isZeroExtended(*MI)) in getKnownLeadingZeroCount()
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| D | PPCInstrInfo.cpp | 2424 if (isZeroExtended(*MI)) { in optimizeCompareInstr()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 3653 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() function
3676 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
3770 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
3771 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
12654 isZeroExtended(N0.getNode(), DAG))) in performMulCombine()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 9113 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() function
9256 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
9276 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
9277 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
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