| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 33 bool isWave32; variable
279 return isWave32 ? &AMDGPU::SReg_32RegClass in getBoolRC()
284 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getWaveMaskRegClass()
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| D | SIOptimizeExecMasking.cpp | 64 Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC)) in isCopyFromExec()
80 Dst.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) && in isCopyToExec()
302 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
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| D | SILateBranchLowering.cpp | 135 MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in runOnMachineFunction()
136 ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
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| D | AMDGPUAtomicOptimizer.cpp | 311 if (ST->isWave32()) in buildReduction()
366 if (!ST->isWave32()) { in buildScan()
411 if (!ST->isWave32()) { in buildShiftRight()
504 if (ST->isWave32()) { in optimizeAtomic()
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| D | SIRegisterInfo.cpp | 275 SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) { in SIRegisterInfo()
492 if (isWave32) { in getReservedRegs()
1327 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in spillSGPR()
1443 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in restoreSGPR()
1835 if (!isWave32) in eliminateFrameIndex()
2412 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClassForSizeOnBank()
2435 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in getVCC()
2450 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClass()
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| D | SIFrameLowering.cpp | 571 if (ST.isWave32()) { in emitEntryFunctionScratchRsrcRegSetup()
722 ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64; in buildScratchExecCopy()
799 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitPrologue()
800 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitPrologue()
1102 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitEpilogue()
1103 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitEpilogue()
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| D | SIInstrInfo.cpp | 1075 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1089 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1132 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 in insertVectorSelect()
1135 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1150 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 in insertVectorSelect()
1153 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1797 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; in expandPostRAPseudo()
1798 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in expandPostRAPseudo()
1809 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; in expandPostRAPseudo()
1810 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in expandPostRAPseudo()
[all …]
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| D | SILowerI1Copies.cpp | 420 return MRI.createVirtualRegister(ST.isWave32() ? &AMDGPU::SReg_32RegClass in createLaneMaskReg()
456 IsWave32 = ST->isWave32(); in runOnMachineFunction()
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| D | SILowerControlFlow.cpp | 641 bool IsWave32 = ST.isWave32(); in lowerInitExec()
786 if (ST.isWave32()) { in runOnMachineFunction()
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| D | SIPreEmitPeephole.cpp | 80 const bool IsWave32 = ST.isWave32(); in optimizeVccBranch()
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| D | SIAnnotateControlFlow.cpp | 128 IntMask = ST.isWave32() ? Type::getInt32Ty(Context) in initialize()
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| D | SIWholeQuadMode.cpp | 873 Register VCC = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in lowerKillF32()
976 unsigned MovOpc = ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in lowerKillI1()
1522 if (ST->isWave32()) { in runOnMachineFunction()
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| D | SIOptimizeExecMaskingPreRA.cpp | 314 const bool Wave32 = ST.isWave32(); in runOnMachineFunction()
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| D | AMDGPUAsmPrinter.cpp | 398 if (MF.getSubtarget<GCNSubtarget>().isWave32()) { in getAmdhsaKernelCodeProperties()
949 if (STM.isWave32()) in EmitPALMetadata()
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| D | GCNSubtarget.h | 1142 bool isWave32() const { in isWave32() function
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| D | VOP2Instructions.td | 217 let WaveSizePredicate = isWave32 in {
264 let WaveSizePredicate = isWave32 in {
1085 let WaveSizePredicate = isWave32;
1112 let WaveSizePredicate = isWave32;
1137 let WaveSizePredicate = isWave32;
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| D | VOPCInstructions.td | 173 let WaveSizePredicate = isWave32 in {
773 let WaveSizePredicate = isWave32 in
822 let WaveSizePredicate = isWave32 in
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| D | SIShrinkInstructions.cpp | 606 unsigned VCCReg = ST.isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in runOnMachineFunction()
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| D | AMDGPURegisterBankInfo.cpp | 722 const unsigned WaveAndOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
724 const unsigned MovTermOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
726 const unsigned XorTermOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
728 const unsigned AndSaveExecOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
730 const unsigned ExecReg = Subtarget.isWave32() ? in executeInWaterfallLoop()
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| D | SIInstrInfo.h | 1052 bool isWave32() const;
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| D | SIInstructions.td | 271 let WaveSizePredicate = isWave32 in {
1661 let WaveSizePredicate = isWave32;
1994 let WaveSizePredicate = isWave32 in {
2031 } // end isWave32
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| D | SIInsertWaitcnts.cpp | 1562 TII->get(ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64), in insertWaitcntInBlock()
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| D | AMDGPUISelDAGToDAG.cpp | 2375 Cond = SDValue(CurDAG->getMachineNode(ST->isWave32() ? AMDGPU::S_AND_B32 in SelectBRCOND()
2378 CurDAG->getRegister(ST->isWave32() ? AMDGPU::EXEC_LO in SelectBRCOND()
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| D | SIISelLowering.cpp | 3576 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32 in emitLoadM0FromVGPRLoop()
3605 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitLoadM0FromVGPRLoop()
3607 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term in emitLoadM0FromVGPRLoop()
3642 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in loadM0FromVGPR()
3643 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in loadM0FromVGPR()
11768 if (ST.isWave32() && !MF.empty()) { in finalizeLowering()
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| D | VOP3Instructions.td | 763 let WaveSizePredicate = isWave32 in {
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