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Searched refs:isImm (Results 1 – 25 of 217) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
DVEInstPrinter.cpp64 if (MO.isImm()) { in printOperand()
89 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
95 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
97 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
98 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
106 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
112 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
133 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandASX()
139 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandASX()
140 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandASX()
[all …]
DVEMCCodeEmitter.cpp106 if (MO.isImm()) in getMachineOpValue()
130 if (MO.isReg() || MO.isImm()) in getBranchTargetOpValue()
142 if (MO.isImm()) in getCCOpValue()
152 if (MO.isImm()) in getRDOpValue()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp214 assert(MO.isImm() && "did not expect relocated expression"); in getMachineOpValue()
225 if (MO.isImm()) in getLdStUImm12OpValue()
246 if (MO.isImm()) in getAdrLabelOpValue()
277 if (MO.isImm()) in getAddSubImmOpValue()
308 if (MO.isImm()) in getCondBranchTargetOpValue()
330 if (MO.isImm()) in getLoadLiteralOpValue()
358 if (MO.isImm()) in getMoveWideImmOpValue()
378 if (MO.isImm()) in getTestBranchTargetOpValue()
400 if (MO.isImm()) in getBranchTargetOpValue()
426 assert(MO.isImm() && "Expected an immediate value for the shift amount!"); in getVecShifterOpValue()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp62 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
242 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTargetOpValue()
264 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValue1SImm16()
286 if (MO.isImm()) in getBranchTargetOpValueMMR6()
309 if (MO.isImm()) in getBranchTargetOpValueLsl2MMR6()
332 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTarget7OpValueMM()
353 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValueMMPC10()
374 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValueMM()
396 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTarget21OpValue()
418 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTarget21OpValueMM()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp48 if (MO.isReg() || MO.isImm()) in getDirectBrEncoding()
63 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
76 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
89 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
111 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
125 if (MO.isImm()) in getImm34Encoding()
158 if (MO.isImm()) in getMemRIEncoding()
176 if (MO.isImm()) in getMemRIXEncoding()
194 if (MO.isImm()) { in getMemRIX16Encoding()
216 assert(MO.isImm() && "Expecting an immediate operand."); in getMemRIHashEncoding()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiMCCodeEmitter.cpp114 if (MCOp.isImm()) in getMachineOpValue()
145 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
153 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
194 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
200 if (Op2.isImm()) { in getRiMemoryOpValue()
230 assert(AluMCOp.isImm() && "Third operator is not immediate."); in getRrMemoryOpValue()
265 assert((Op2.isImm() || Op2.isExpr()) && in getSplsOpValue()
271 if (Op2.isImm()) { in getSplsOpValue()
292 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
DLanaiInstPrinter.cpp155 else if (Op.isImm()) in printOperand()
166 if (Op.isImm()) { in printMemImmOperand()
180 if (Op.isImm()) { in printHi16ImmOperand()
192 if (Op.isImm()) { in printHi16AndImmOperand()
204 if (Op.isImm()) { in printLo16AndImmOperand()
229 assert((OffsetOp.isImm() || OffsetOp.isExpr()) && "Immediate expected"); in printMemoryImmediateOffset()
230 if (OffsetOp.isImm()) { in printMemoryImmediateOffset()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCTargetDesc.cpp42 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo()
43 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
46 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo()
47 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo()
48 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo()
55 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo()
62 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo()
63 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo()
69 ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) || in getMCRDeprecationInfo()
70 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) { in getMCRDeprecationInfo()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
DBPFInstPrinter.cpp57 } else if (Op.isImm()) { in printOperand()
75 if (OffsetOp.isImm()) { in printMemOperand()
89 if (Op.isImm()) in printImm64Operand()
100 if (Op.isImm()) { in printBrTargetOperand()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
DLanaiMemAluCombiner.cpp186 (Op.isImm() && Op.getImm() == 0)); in isZeroOperand()
247 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction()
252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction()
266 else if (AluOffset.isImm()) in insertMergedInstruction()
301 if (Op2.isImm()) { in isSuitableAluInstr()
310 if (Offset.isImm() && in isSuitableAluInstr()
375 assert(AluOperand.isImm() && "Unexpected memory operator type"); in combineMemAluInBasicBlock()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
DLanaiAsmParser.cpp162 assert(isImm() && "Invalid type access!"); in getImm()
194 bool isImm() const override { return Kind == IMMEDIATE; } in isImm() function
211 if (!isImm()) in isBrImm()
225 bool isCallTarget() { return isImm() || isToken(); } in isCallTarget()
228 if (!isImm()) in isHiImm16()
251 if (!isImm()) in isHiImm16And()
264 if (!isImm()) in isLoImm16()
288 if (!isImm()) in isLoImm16Signed()
312 if (!isImm()) in isLoImm16And()
325 if (!isImm()) in isImmShift()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
DMSP430MCCodeEmitter.cpp108 if (MO.isImm()) { in getMachineOpValue()
128 if (MO2.isImm()) { in getMemOpValue()
156 if (MO.isImm()) in getPCRelImmOpValue()
169 assert(MO.isImm() && "Expr operand expected"); in getCGImmOpValue()
188 assert(MO.isImm() && "Immediate operand expected"); in getCCOpValue()
DMSP430InstPrinter.cpp40 if (Op.isImm()) { in printPCRelImmOperand()
58 } else if (Op.isImm()) { in printOperand()
87 assert(Disp.isImm() && "Expected immediate in displacement field"); in printSrcMemOperand()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/MCTargetDesc/
DARCInstPrinter.cpp148 if (Op.isImm()) { in printOperand()
162 assert(offset.isImm() && "Offset should be immediate."); in printMemOperandRI()
171 assert(Op.isImm() && "Predicate operand is immediate."); in printPredicateOperand()
178 assert(Op.isImm() && "Predicate operand is immediate."); in printBRCCPredicateOperand()
190 if (MO.isImm()) { in printU6ShiftedBy()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
DAVRMCCodeEmitter.cpp104 assert(MO.isImm()); in encodeRelCondBrTarget()
157 if (OffsetOp.isImm()) { in encodeMemri()
174 assert(MI.getOperand(OpNo).isImm()); in encodeComplement()
201 assert(MO.isImm()); in encodeImm()
216 assert(MO.isImm()); in encodeCallTarget()
255 if (MO.isImm()) return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
DAVRInstPrinter.cpp133 } else if (Op.isImm()) { in printOperand()
157 if (Op.isImm()) { in printPCRelImm()
183 if (OffsetOp.isImm()) { in printMemri()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp375 bool isImm = fieldFromInstruction(insn, 13, 1); in DecodeMem() local
380 if (isImm) in DecodeMem()
398 if (isImm) in DecodeMem()
532 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeJMPL() local
535 if (isImm) in DecodeJMPL()
551 if (isImm) in DecodeJMPL()
565 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeReturn() local
568 if (isImm) in DecodeReturn()
579 if (isImm) in DecodeReturn()
594 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeSWAP() local
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DSIFoldOperands.cpp41 if (FoldOp->isImm()) { in FoldCandidate()
55 bool isImm() const { in isImm() function
210 if (Fold.isImm()) { in updateOperand()
258 if ((Fold.isImm() || Fold.isFI() || Fold.isGlobal()) && Fold.needsShrink()) { in updateOperand()
302 if (Fold.isImm()) { in updateOperand()
367 if (OpToFold->isImm()) { in tryAddToFoldList()
418 (OpToFold->isImm() || OpToFold->isFI() || OpToFold->isGlobal())) { in tryAddToFoldList()
455 if (OpToFold->isImm()) { in tryAddToFoldList()
514 if (Op->isImm()) { in getRegSeqInit()
547 if (OpToFold.isImm() && TII->isInlineConstant(OpToFold, OpTy) && in tryToFoldACImm()
[all …]
DGCNDPPCombine.cpp172 if (Op1.isImm()) in getOldOpndValue()
296 assert(OldOpnd->isImm()); in isIdentityValue()
351 if (!CombBCZ && OldOpndValue && OldOpndValue->isImm()) { in createDPPInst()
380 assert(Imm->isImm()); in hasNoImmOrEqual()
404 assert(DppCtrl && DppCtrl->isImm()); in combineDPPMov()
414 assert(RowMaskOpnd && RowMaskOpnd->isImm()); in combineDPPMov()
416 assert(BankMaskOpnd && BankMaskOpnd->isImm()); in combineDPPMov()
421 assert(BCZOpnd && BCZOpnd->isImm()); in combineDPPMov()
438 assert(!OldOpndValue || OldOpndValue->isImm() || OldOpndValue == OldOpnd); in combineDPPMov()
445 if (!OldOpndValue || !OldOpndValue->isImm()) { in combineDPPMov()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
DSparcMCCodeEmitter.cpp133 if (MO.isImm()) in getMachineOpValue()
158 if (MO.isImm()) in getSImm13OpValue()
215 if (MO.isReg() || MO.isImm()) in getBranchTargetOpValue()
228 if (MO.isReg() || MO.isImm()) in getBranchPredTargetOpValue()
241 if (MO.isReg() || MO.isImm()) in getBranchOnRegTargetOpValue()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/
DM68kInstPrinter.cpp65 if (MO.isImm()) { in printOperand()
77 if (MO.isImm()) in printImmediate()
142 if (Op.isImm()) { in printDisp()
201 assert(MO.isImm() && "absolute memory addressing needs an immediate"); in printAbsMem()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86InstComments.cpp662 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
678 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
694 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
708 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
726 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
820 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
838 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
852 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
870 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
888 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonHardwareLoops.cpp342 bool isImm() const { return Kind == CV_Immediate; } in isImm() function in __anon8f2b48bc0111::CountValue
355 assert(isImm() && "Wrong CountValue accessor"); in getImm()
361 if (isImm()) { OS << Contents.ImmVal; } in print()
678 if (Op2.isImm() || Op1.getReg() == IVReg) in getLoopTripCount()
750 if (!Start->isReg() && !Start->isImm()) in computeCount()
752 if (!End->isReg() && !End->isImm()) in computeCount()
778 if (Start->isImm() && End->isImm()) { in computeCount()
850 bool RegToImm = Start->isReg() && End->isImm(); // for (reg..imm) in computeCount()
854 if (Start->isImm()) in computeCount()
856 if (End->isImm()) in computeCount()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
DRISCVAsmParser.cpp330 bool isImm() const override { return Kind == KindTy::Immediate; } in isImm() function
361 if (!isImm()) in isBareSimmNLsb0()
378 if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) in isBareSymbol()
388 if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) in isCallSymbol()
399 if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) in isPseudoJumpSymbol()
409 if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) in isTPRelAddSymbol()
422 if (!isImm()) in isFenceArg()
446 if (!isImm()) in isFRMArg()
461 if (!isImm()) in isImmXLenLI()
475 if (!isImm()) in isUImmLog2XLen()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
DX86Operand.h210 bool isImm() const override { return Kind == Immediate; } in isImm() function
213 if (!isImm()) in isImmSExti16i8()
227 if (!isImm()) in isImmSExti32i8()
241 if (!isImm()) in isImmSExti64i8()
255 if (!isImm()) in isImmSExti64i32()
270 if (!isImm()) return false; in isImmUnsignedi4()
279 if (!isImm()) return false; in isImmUnsignedi8()
287 bool isOffsetOfLocal() const override { return isImm() && Imm.LocalRef; } in isOffsetOfLocal()
375 return isImm(); in isAVX512RC()

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