Home
last modified time | relevance | path

Searched refs:imm5 (Results 1 – 19 of 19) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
DARMUtils.h24 static inline uint32_t DecodeImmShift(const uint32_t type, const uint32_t imm5, in DecodeImmShift() argument
31 return imm5; in DecodeImmShift()
34 return (imm5 == 0 ? 32 : imm5); in DecodeImmShift()
37 return (imm5 == 0 ? 32 : imm5); in DecodeImmShift()
39 if (imm5 == 0) { in DecodeImmShift()
44 return imm5; in DecodeImmShift()
68 const uint32_t imm5) { in DecodeImmShift() argument
70 return DecodeImmShift(shift_t, imm5, dont_care); in DecodeImmShift()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/CSKY/
DCSKYInstrFormats.td259 (ins GPR:$false, GPR:$rx, ImmType:$imm5),
260 !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
263 bits<5> imm5;
268 let Inst{4 - 0} = imm5;
278 !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
279 bits<5> imm5;
282 let Inst{25 - 21} = imm5;
292 bits<5> imm5>
294 op #"\t${ry}, (${rx}), " #!cast<int>(imm5), pattern> {
301 let Inst{4 - 0} = imm5{4 - 0}; // imm5
[all …]
DCSKYInstrInfo.td162 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
163 [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
165 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
166 [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
168 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
169 [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
171 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
172 [(set GPR:$rz, (rotl GPR:$rx, uimm5:$imm5))]>;
225 (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
227 (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb.td239 // t_addrmode_is4 := reg + imm5 * 4
251 // t_addrmode_is2 := reg + imm5 * 2
263 // t_addrmode_is1 := reg + imm5
716 // Loads: reg/reg and reg/imm5
726 def i : // reg/imm5
738 // Stores: reg/reg and reg/imm5
744 def i : // reg/imm5
1078 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1080 "asr", "\t$Rd, $Rm, $imm5",
1081 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
[all …]
DARMInstrFormats.td1317 let Inst{10-6} = addr{7-3}; // imm5
DARMInstrInfo.td738 // {4-0} imm5 shift amount.
739 // asr #32 encoded as imm5 == 0.
DARMInstrThumb2.td35 // {4-0} imm5 shift amount.
/freebsd-12-stable/contrib/llvm-project/lld/ELF/Arch/
DRISCV.cpp313 uint16_t imm5 = extractBits(val, 5, 5) << 2; in relocate() local
314 insn |= imm8 | imm4_3 | imm7_6 | imm2_1 | imm5; in relocate()
331 uint16_t imm5 = extractBits(val, 5, 5) << 2; in relocate() local
332 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5; in relocate()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DSVEInstrFormats.td4571 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm5),
4572 asm, "\t$Pd, $Pg/z, $Zn, $imm5",
4578 bits<5> imm5;
4582 let Inst{20-16} = imm5;
4974 : I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b),
4975 asm, "\t$Zd, $imm5, $imm5b",
4978 bits<5> imm5;
4985 let Inst{9-5} = imm5;
5005 …t<(add (nxv16i8 (step_vector_oneuse simm5_8b_tgt:$imm5b)), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
5006 … (!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, (!cast<SDNodeXForm>("trunc_imm") $imm5b))>;
[all …]
DAArch64SchedA64FX.td2427 // [45] "cmpeq $Pd, $Pg/z, $Zn, $imm5";
2433 // [47] "cmpge $Pd, $Pg/z, $Zn, $imm5";
2439 // [49] "cmpgt $Pd, $Pg/z, $Zn, $imm5";
2457 // [55] "cmple $Pd, $Pg/z, $Zn, $imm5";
2475 // [61] "cmplt $Pd, $Pg/z, $Zn, $imm5";
2481 // [63] "cmpne $Pd, $Pg/z, $Zn, $imm5";
2861 // [190] "index $Zd, $Rn, $imm5";
2864 // [191] "index $Zd, $imm5, $Rm";
2867 // [192] "index $Zd, $imm5, $imm5b";
2897 // [202] "ld1b $Zt, $Pg/z, [$Zn, $imm5]";
[all …]
DAArch64InstrFormats.td7218 class SIMDDupFromMain<bit Q, bits<5> imm5, string size, ValueType vectype,
7224 let Inst{20-16} = imm5;
/freebsd-12-stable/contrib/binutils/include/opcode/
Dcr16.h122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMips16InstrFormats.td228 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
237 bits<5> imm5;
244 let Inst{4-0} = imm5;
DMips64InstrInfo.td926 def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, immZExt5:$imm5)))),
928 (SLL GPR32:$src, immZExt5:$imm5), sub_32)>;
932 def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, immZExt5:$imm5)))),
934 (SRL GPR32:$src, immZExt5:$imm5), sub_32)>;
938 def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, immZExt5:$imm5)))),
940 (SRA GPR32:$src, immZExt5:$imm5), sub_32)>;
/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/MIPS/
DEmulateInstructionMIPS.cpp1503 uint32_t imm5 = insn.getOperand(2).getImm(); in Emulate_SWSP() local
1524 address = address + imm5; in Emulate_SWSP()
1647 uint32_t imm5 = insn.getOperand(2).getImm(); in Emulate_LWSP() local
1661 base_address = base_address + imm5; in Emulate_LWSP()
1753 int32_t imm5 = insn.getOperand(0).getImm(); in Emulate_JRADDIUSP() local
1772 int32_t result = src_opd_val + imm5; in Emulate_JRADDIUSP()
1783 context.SetRegisterPlusOffset(reg_info_sp, imm5); in Emulate_JRADDIUSP()
/freebsd-12-stable/contrib/binutils/opcodes/
Dcr16-opc.c148 SHIFT_INST_A("ashuw", 0x42, 0x45, 24, imm5, regr),
158 SHIFT_INST_L("lshw", 0x49, 0x46, 24, imm5, regr),
Darm-dis.c2094 long imm5; in print_insn_coprocessor() local
2095 imm5 = ((given & 0x100) >> 4) | (given & 0xf); in print_insn_coprocessor()
2096 func (stream, "%ld", (imm5 == 0) ? 32 : imm5); in print_insn_coprocessor()
/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp3761 uint32_t imm5; // encoding for the shift amount in EmulateShiftImm() local
3784 imm5 = Bits32(opcode, 10, 6); in EmulateShiftImm()
3795 imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6); in EmulateShiftImm()
3803 imm5 = Bits32(opcode, 11, 7); in EmulateShiftImm()
3810 if (shift_type == SRType_ROR && imm5 == 0) in EmulateShiftImm()
3820 (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5)); in EmulateShiftImm()
5389 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateSTRRegister() local
5390 shift_n = DecodeImmShift(typ, imm5, shift_t); in EmulateSTRRegister()
6581 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateLDRRegister() local
6582 shift_n = DecodeImmShift(type, imm5, shift_t); in EmulateLDRRegister()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoVVLPatterns.td914 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (ImmPat XLenVT:$imm5),
917 XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>;